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Searched refs:regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h13058 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12921 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h12453 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h12305 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h12296 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13654 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX … macro