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Searched refs:regDPP_TOP0_DPP_CONTROL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h4339 #define regDPP_TOP0_DPP_CONTROL … macro
H A Ddcn_3_1_5_offset.h4098 #define regDPP_TOP0_DPP_CONTROL … macro
H A Ddcn_3_1_4_offset.h4582 #define regDPP_TOP0_DPP_CONTROL … macro
H A Ddcn_3_2_1_offset.h3580 #define regDPP_TOP0_DPP_CONTROL … macro
H A Ddcn_3_2_0_offset.h3581 #define regDPP_TOP0_DPP_CONTROL … macro
H A Ddcn_3_1_6_offset.h4559 #define regDPP_TOP0_DPP_CONTROL … macro