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Searched refs:regCP_MEC_ME1_UCODE_ADDR (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c3423 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v11_0_cp_compute_load_microcode()
3429 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
H A Dgfx_v9_4_3.c1426 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h3422 #define regCP_MEC_ME1_UCODE_ADDR … macro
H A Dgc_9_4_3_offset.h7100 #define regCP_MEC_ME1_UCODE_ADDR … macro
H A Dgc_11_0_0_offset.h9696 #define regCP_MEC_ME1_UCODE_ADDR … macro
H A Dgc_11_0_3_offset.h10248 #define regCP_MEC_ME1_UCODE_ADDR … macro