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Searched refs:regCP_ME1_PIPE3_INT_CNTL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h485 #define regCP_ME1_PIPE3_INT_CNTL … macro
H A Dgc_9_4_3_offset.h2946 #define regCP_ME1_PIPE3_INT_CNTL … macro
H A Dgc_11_0_0_offset.h4238 #define regCP_ME1_PIPE3_INT_CNTL … macro
H A Dgc_11_0_3_offset.h4458 #define regCP_ME1_PIPE3_INT_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c2728 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v11_0.c5779 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()