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Searched refs:regCP_INT_CNTL_RING0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c1751 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_enable_gui_idle_interrupt()
1762 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); in gfx_v11_0_enable_gui_idle_interrupt()
5719 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
H A Dgfx_v9_4_3.c1165 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
1171 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h437 #define regCP_INT_CNTL_RING0 … macro
H A Dgc_9_4_3_offset.h2890 #define regCP_INT_CNTL_RING0 … macro
H A Dgc_11_0_0_offset.h4198 #define regCP_INT_CNTL_RING0 … macro
H A Dgc_11_0_3_offset.h4416 #define regCP_INT_CNTL_RING0 … macro