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Searched refs:regCNVC_CFG3_PRE_CSC_B_C31_C32 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h5813 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_1_5_offset.h5572 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_1_4_offset.h6726 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_2_1_offset.h4420 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_2_0_offset.h4421 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_1_6_offset.h6033 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 … macro