Home
last modified time | relevance | path

Searched refs:regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h5122 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4881 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6035 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4035 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h4036 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h5342 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX … macro