Home
last modified time | relevance | path

Searched refs:regCNVC_CFG0_PRE_CSC_C31_C32 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h3725 #define regCNVC_CFG0_PRE_CSC_C31_C32 … macro
H A Ddcn_3_1_5_offset.h3484 #define regCNVC_CFG0_PRE_CSC_C31_C32 … macro
H A Ddcn_3_1_4_offset.h4638 #define regCNVC_CFG0_PRE_CSC_C31_C32 … macro
H A Ddcn_3_2_1_offset.h3250 #define regCNVC_CFG0_PRE_CSC_C31_C32 … macro
H A Ddcn_3_2_0_offset.h3251 #define regCNVC_CFG0_PRE_CSC_C31_C32 … macro
H A Ddcn_3_1_6_offset.h3945 #define regCNVC_CFG0_PRE_CSC_C31_C32 … macro