Home
last modified time | relevance | path

Searched refs:regCNVC_CFG0_PRE_CSC_B_C11_C12 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h3729 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_1_5_offset.h3488 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_1_4_offset.h4642 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_2_1_offset.h3254 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_2_0_offset.h3255 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_1_6_offset.h3949 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 … macro