Home
last modified time | relevance | path

Searched refs:regCM0_CM_POST_CSC_C11_C12_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h3840 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h3599 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h4753 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3365 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3366 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4060 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX … macro