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Searched refs:regCM0_CM_MEM_PWR_STATUS (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h4193 #define regCM0_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_1_5_offset.h3952 #define regCM0_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_1_4_offset.h5106 #define regCM0_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_2_1_offset.h3570 #define regCM0_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_2_0_offset.h3571 #define regCM0_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_1_6_offset.h4413 #define regCM0_CM_MEM_PWR_STATUS … macro