Home
last modified time | relevance | path

Searched refs:regCC_RB_BACKEND_DISABLE (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0.c205 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0x0fffff01, 0xe0000000),
276 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0x00000f01, 0xe0000000),
H A Dimu_v11_0_3.c59 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0xffffff01, 0xe0000000),
H A Dgfx_v11_0.c1581 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h4758 #define regCC_RB_BACKEND_DISABLE … macro
H A Dgc_9_4_3_offset.h1046 #define regCC_RB_BACKEND_DISABLE … macro
H A Dgc_11_0_0_offset.h2388 #define regCC_RB_BACKEND_DISABLE … macro
H A Dgc_11_0_3_offset.h2496 #define regCC_RB_BACKEND_DISABLE … macro