1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _nbio_4_3_0_OFFSET_HEADER 24 #define _nbio_4_3_0_OFFSET_HEADER 25 26 27 28 // addressBlock: nbio_nbif0_bif_bx_SYSDEC 29 // base address: 0x0 30 #define regBIF_BX0_PCIE_INDEX 0x000c 31 #define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 32 #define regBIF_BX0_PCIE_DATA 0x000d 33 #define regBIF_BX0_PCIE_DATA_BASE_IDX 0 34 #define regBIF_BX0_PCIE_INDEX2 0x000e 35 #define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 36 #define regBIF_BX0_PCIE_DATA2 0x000f 37 #define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 38 #define regBIF_BX0_PCIE_INDEX_HI 0x0010 39 #define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 40 #define regBIF_BX0_PCIE_INDEX2_HI 0x0011 41 #define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 42 #define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 43 #define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 44 #define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 45 #define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 46 #define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 47 #define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 48 #define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 49 #define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 50 #define regBIF_BX0_BIOS_SCRATCH_0 0x0038 51 #define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 52 #define regBIF_BX0_BIOS_SCRATCH_1 0x0039 53 #define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 54 #define regBIF_BX0_BIOS_SCRATCH_2 0x003a 55 #define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 56 #define regBIF_BX0_BIOS_SCRATCH_3 0x003b 57 #define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 58 #define regBIF_BX0_BIOS_SCRATCH_4 0x003c 59 #define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 60 #define regBIF_BX0_BIOS_SCRATCH_5 0x003d 61 #define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 62 #define regBIF_BX0_BIOS_SCRATCH_6 0x003e 63 #define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 64 #define regBIF_BX0_BIOS_SCRATCH_7 0x003f 65 #define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 66 #define regBIF_BX0_BIOS_SCRATCH_8 0x0040 67 #define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 68 #define regBIF_BX0_BIOS_SCRATCH_9 0x0041 69 #define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 70 #define regBIF_BX0_BIOS_SCRATCH_10 0x0042 71 #define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 72 #define regBIF_BX0_BIOS_SCRATCH_11 0x0043 73 #define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 74 #define regBIF_BX0_BIOS_SCRATCH_12 0x0044 75 #define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 76 #define regBIF_BX0_BIOS_SCRATCH_13 0x0045 77 #define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 78 #define regBIF_BX0_BIOS_SCRATCH_14 0x0046 79 #define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 80 #define regBIF_BX0_BIOS_SCRATCH_15 0x0047 81 #define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 82 #define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c 83 #define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 84 #define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d 85 #define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 86 #define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e 87 #define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 88 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c 89 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 90 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 91 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 92 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e 93 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 94 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 95 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 96 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 97 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 98 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 99 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 100 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 101 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 102 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 103 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 104 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 105 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 106 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 107 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 108 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 109 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 110 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 111 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 112 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 113 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 114 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 115 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 116 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a 117 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 118 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 119 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 120 #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c 121 #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 122 #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d 123 #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 124 #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e 125 #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 126 #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 127 #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 128 #define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 129 #define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 130 #define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 131 #define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 132 #define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 133 #define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 134 #define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 135 #define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 136 #define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 137 #define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 138 #define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 139 #define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 140 #define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 141 #define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 142 #define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 143 #define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 144 #define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 145 #define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 146 #define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 147 #define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 148 #define regBIF_BX0_DRIVER_SCRATCH_10 0x008a 149 #define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 150 #define regBIF_BX0_DRIVER_SCRATCH_11 0x008b 151 #define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 152 #define regBIF_BX0_DRIVER_SCRATCH_12 0x008c 153 #define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 154 #define regBIF_BX0_DRIVER_SCRATCH_13 0x008d 155 #define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 156 #define regBIF_BX0_DRIVER_SCRATCH_14 0x008e 157 #define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 158 #define regBIF_BX0_DRIVER_SCRATCH_15 0x008f 159 #define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 160 #define regBIF_BX0_FW_SCRATCH_0 0x0090 161 #define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 162 #define regBIF_BX0_FW_SCRATCH_1 0x0091 163 #define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 164 #define regBIF_BX0_FW_SCRATCH_2 0x0092 165 #define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 166 #define regBIF_BX0_FW_SCRATCH_3 0x0093 167 #define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 168 #define regBIF_BX0_FW_SCRATCH_4 0x0094 169 #define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 170 #define regBIF_BX0_FW_SCRATCH_5 0x0095 171 #define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 172 #define regBIF_BX0_FW_SCRATCH_6 0x0096 173 #define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 174 #define regBIF_BX0_FW_SCRATCH_7 0x0097 175 #define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 176 #define regBIF_BX0_FW_SCRATCH_8 0x0098 177 #define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 178 #define regBIF_BX0_FW_SCRATCH_9 0x0099 179 #define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 180 #define regBIF_BX0_FW_SCRATCH_10 0x009a 181 #define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 182 #define regBIF_BX0_FW_SCRATCH_11 0x009b 183 #define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 184 #define regBIF_BX0_FW_SCRATCH_12 0x009c 185 #define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 186 #define regBIF_BX0_FW_SCRATCH_13 0x009d 187 #define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 188 #define regBIF_BX0_FW_SCRATCH_14 0x009e 189 #define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 190 #define regBIF_BX0_FW_SCRATCH_15 0x009f 191 #define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 192 #define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 193 #define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 194 #define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 195 #define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 196 #define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 197 #define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 198 #define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 199 #define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 200 #define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 201 #define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 202 #define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 203 #define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 204 #define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 205 #define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 206 #define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 207 #define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 208 #define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 209 #define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 210 #define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 211 #define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 212 #define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa 213 #define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 214 #define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab 215 #define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 216 217 218 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 219 // base address: 0x0 220 #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060 221 #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 222 #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061 223 #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 224 #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063 225 #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 226 #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064 227 #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 228 #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065 229 #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 230 #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066 231 #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 232 #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067 233 #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 234 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068 235 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 236 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069 237 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 238 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a 239 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 240 241 242 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 243 // base address: 0x0 244 #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c 245 #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 246 #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d 247 #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 248 #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e 249 #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 250 #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f 251 #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 252 #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070 253 #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 254 #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071 255 #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 256 257 258 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 259 // base address: 0x0 260 #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0040 261 #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 262 #define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0042 263 #define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 264 #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0043 265 #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 266 #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0044 267 #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 268 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0045 269 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 270 #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0046 271 #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 272 #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0047 273 #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 274 #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0049 275 #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 276 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004a 277 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 278 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004a 279 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 280 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004a 281 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 282 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004a 283 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 284 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004b 285 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 286 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004b 287 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 288 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004b 289 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 290 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004b 291 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 292 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004c 293 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 294 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004d 295 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 296 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x004f 297 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 298 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0050 299 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 300 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0050 301 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 302 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0050 303 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 304 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0051 305 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 306 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0051 307 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 308 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0051 309 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 310 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0051 311 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 312 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0052 313 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 314 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0052 315 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 316 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0052 317 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 318 #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0052 319 #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 320 #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0053 321 #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 322 #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0055 323 #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 324 #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0056 325 #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 326 #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0057 327 #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 328 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0058 329 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 330 #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0059 331 #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 332 333 334 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 335 // base address: 0x0 336 #define regBIF_BX_PF0_MM_INDEX 0x0000 337 #define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 338 #define regBIF_BX_PF0_MM_DATA 0x0001 339 #define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 340 #define regBIF_BX_PF0_MM_INDEX_HI 0x0006 341 #define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 342 #define regBIF_BX_PF0_RSMU_INDEX 0x0000 343 #define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 344 #define regBIF_BX_PF0_RSMU_DATA 0x0001 345 #define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 346 #define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 347 #define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 348 349 350 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 351 // base address: 0x0 352 #define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 353 #define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 354 #define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 355 #define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 356 #define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 357 #define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 358 #define regBIF_BX0_BUS_CNTL 0x00e7 359 #define regBIF_BX0_BUS_CNTL_BASE_IDX 2 360 #define regBIF_BX0_BIF_SCRATCH0 0x00e8 361 #define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 362 #define regBIF_BX0_BIF_SCRATCH1 0x00e9 363 #define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 364 #define regBIF_BX0_BX_RESET_EN 0x00ed 365 #define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 366 #define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee 367 #define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 368 #define regBIF_BX0_BX_RESET_CNTL 0x00f0 369 #define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 370 #define regBIF_BX0_INTERRUPT_CNTL 0x00f1 371 #define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 372 #define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 373 #define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 374 #define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 375 #define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 376 #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb 377 #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 378 #define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc 379 #define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 380 #define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd 381 #define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 382 #define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe 383 #define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 384 #define regBIF_BX0_BIF_FB_EN 0x0100 385 #define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 386 #define regBIF_BX0_BIF_INTR_CNTL 0x0101 387 #define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 388 #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 389 #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 390 #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a 391 #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 392 #define regBIF_BX0_MEM_TYPE_CNTL 0x0111 393 #define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 394 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 395 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 396 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 397 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 398 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 399 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 400 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 401 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 402 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 403 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 404 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 405 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 406 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 407 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 408 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a 409 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 410 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b 411 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 412 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c 413 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 414 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d 415 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 416 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e 417 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 418 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f 419 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 420 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 421 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 422 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 423 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 424 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 425 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 426 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 427 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 428 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d 429 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 430 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e 431 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 432 #define regBIF_BX0_BIF_RB_CNTL 0x012f 433 #define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 434 #define regBIF_BX0_BIF_RB_BASE 0x0130 435 #define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 436 #define regBIF_BX0_BIF_RB_RPTR 0x0131 437 #define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 438 #define regBIF_BX0_BIF_RB_WPTR 0x0132 439 #define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 440 #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 441 #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 442 #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 443 #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 444 #define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 445 #define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 446 447 448 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 449 // base address: 0x0 450 #define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 451 #define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 452 #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 453 #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 454 #define regRCC_DEV0_0_RCC_RESET_EN 0x0088 455 #define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 456 #define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 457 #define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 458 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a 459 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 460 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b 461 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 462 #define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c 463 #define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 464 #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d 465 #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 466 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e 467 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 468 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f 469 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 470 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f 471 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 472 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be 473 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 474 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf 475 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 476 #define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 477 #define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 478 #define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 479 #define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 480 #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 481 #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 482 #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 483 #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 484 #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 485 #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 486 #define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 487 #define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 488 #define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca 489 #define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 490 #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb 491 #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 492 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc 493 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 494 #define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd 495 #define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 496 #define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce 497 #define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 498 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf 499 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 500 #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 501 #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 502 #define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 503 #define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 504 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 505 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 506 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 507 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 508 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 509 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 510 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 511 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 512 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 513 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 514 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 515 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 516 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 517 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 518 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 519 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 520 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da 521 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 522 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db 523 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 524 #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd 525 #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 526 #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de 527 #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 528 #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df 529 #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 530 #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 531 #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 532 #define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 533 #define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 534 535 536 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 537 // base address: 0x0 538 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 539 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 540 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 541 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 542 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 543 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 544 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 545 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 546 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 547 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 548 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 549 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 550 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 551 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 552 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 553 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 554 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 555 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 556 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 557 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 558 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a 559 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 560 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b 561 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 562 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c 563 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 564 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d 565 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 566 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e 567 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 568 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f 569 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 570 #define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 571 #define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3 572 573 574 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 575 // base address: 0x0 576 #define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 577 #define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 578 #define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 579 #define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 580 #define regRCC_STRAP0_RCC_BIF_STRAP2 0x0002 581 #define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 582 #define regRCC_STRAP0_RCC_BIF_STRAP3 0x0003 583 #define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 584 #define regRCC_STRAP0_RCC_BIF_STRAP4 0x0004 585 #define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 586 #define regRCC_STRAP0_RCC_BIF_STRAP5 0x0005 587 #define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 588 #define regRCC_STRAP0_RCC_BIF_STRAP6 0x0006 589 #define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 590 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x0007 591 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 592 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x0008 593 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 594 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0009 595 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 596 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x000a 597 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 598 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x000b 599 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 600 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x000c 601 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 602 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x000d 603 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 604 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x000e 605 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 606 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x000f 607 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 608 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0010 609 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 610 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0011 611 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 612 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0012 613 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 614 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0013 615 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 616 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x0014 617 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 618 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0015 619 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 620 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0016 621 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 622 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0017 623 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 624 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0018 625 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 626 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0019 627 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 628 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x001a 629 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 630 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x001b 631 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 632 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x001c 633 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 634 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x001d 635 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 636 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x001e 637 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 638 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 0x001f 639 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX 2 640 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0020 641 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 642 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0021 643 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 644 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0022 645 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 646 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0023 647 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 648 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0024 649 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 650 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0025 651 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 652 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0031 653 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 654 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0032 655 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 656 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0033 657 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 658 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 0x0034 659 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX 2 660 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0035 661 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 662 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0036 663 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 664 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 0x0037 665 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX 2 666 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0038 667 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 668 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x0039 669 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 670 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003a 671 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 672 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003b 673 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 674 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003c 675 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 676 677 678 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 679 // base address: 0x0 680 #define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb 681 #define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 682 #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec 683 #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 684 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 685 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 686 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 687 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 688 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 689 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 690 #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 691 #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 692 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 693 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 694 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 695 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 696 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 697 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 698 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 699 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 700 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 701 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 702 #define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 703 #define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 704 #define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 705 #define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 706 707 708 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] 709 // base address: 0x3480 710 #define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 711 #define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 712 #define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 713 #define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 714 #define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 715 #define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 716 #define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 717 #define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 718 #define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 719 #define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 720 721 722 // addressBlock: nbio_nbif0_gdc_GDCDEC 723 // base address: 0x0 724 #define regGDC0_SHUB_REGS_IF_CTL 0x01c3 725 #define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 2 726 #define regGDC0_NBIF_GFX_DOORBELL_STATUS 0x01cf 727 #define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 2 728 #define regGDC0_ATDMA_MISC_CNTL 0x01dd 729 #define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 2 730 #define regGDC0_S2A_MISC_CNTL 0x01df 731 #define regGDC0_S2A_MISC_CNTL_BASE_IDX 2 732 733 734 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 735 // base address: 0x0 736 #define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb 737 #define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 738 #define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec 739 #define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 740 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 741 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 742 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 743 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 744 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 745 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 746 #define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 747 #define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 748 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 749 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 750 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 751 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 752 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 753 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 754 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 755 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 756 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 757 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 758 #define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 759 #define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 760 #define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 761 #define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 762 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 763 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 764 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 765 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 766 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 767 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 768 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 769 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 770 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 771 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 772 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 773 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 774 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 775 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 776 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 777 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 778 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e 779 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 780 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f 781 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 782 #define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 783 #define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 784 785 786 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 787 // base address: 0x0 788 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 789 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 790 #define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 791 #define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 792 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 793 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 794 795 796 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 797 // base address: 0x0 798 #define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 799 #define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 800 #define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 801 #define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 802 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 803 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 804 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 805 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 806 #define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 807 #define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 808 809 810 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 811 // base address: 0x0 812 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 813 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 814 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 815 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 816 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 817 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 818 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 819 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 820 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 821 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 822 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 823 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 824 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 825 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 826 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 827 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 828 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 829 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 830 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 831 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 832 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a 833 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 834 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b 835 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 836 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c 837 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 838 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d 839 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 840 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e 841 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 842 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f 843 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 844 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 845 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 846 847 848 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 849 // base address: 0x0 850 #define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb 851 #define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 852 #define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec 853 #define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 854 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 855 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 856 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 857 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 858 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 859 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 860 #define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 861 #define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 862 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 863 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 864 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 865 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 866 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 867 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 868 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 869 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 870 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 871 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 872 #define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 873 #define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 874 #define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 875 #define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 876 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 877 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 878 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 879 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 880 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 881 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 882 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 883 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 884 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a 885 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 886 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b 887 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 888 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c 889 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 890 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d 891 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 892 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e 893 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 894 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f 895 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 896 #define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 897 #define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 898 899 900 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 901 // base address: 0x0 902 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 903 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 904 #define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 905 #define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 906 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 907 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 908 909 910 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 911 // base address: 0x0 912 #define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 913 #define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 914 #define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 915 #define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 916 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 917 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 918 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 919 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 920 #define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 921 #define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 922 923 924 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 925 // base address: 0x0 926 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 927 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 928 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 929 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 930 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 931 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 932 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 933 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 934 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 935 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 936 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 937 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 938 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 939 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 940 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 941 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 942 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 943 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 944 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 945 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 946 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a 947 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 948 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b 949 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 950 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c 951 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 952 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d 953 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 954 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e 955 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 956 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f 957 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 958 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 959 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 960 961 962 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 963 // base address: 0x0 964 #define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb 965 #define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 966 #define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec 967 #define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 968 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 969 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 970 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 971 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 972 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 973 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 974 #define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 975 #define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 976 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 977 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 978 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 979 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 980 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 981 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 982 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 983 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 984 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 985 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 986 #define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 987 #define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 988 #define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 989 #define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 990 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 991 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 992 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 993 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 994 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 995 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 996 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 997 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 998 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a 999 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1000 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b 1001 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1002 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c 1003 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1004 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d 1005 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1006 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e 1007 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 1008 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f 1009 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 1010 #define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 1011 #define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 1012 1013 1014 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 1015 // base address: 0x0 1016 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 1017 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 1018 #define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 1019 #define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 1020 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 1021 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 1022 1023 1024 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 1025 // base address: 0x0 1026 #define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 1027 #define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 1028 #define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 1029 #define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 1030 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 1031 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1032 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 1033 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 1034 #define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1035 #define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1036 1037 1038 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 1039 // base address: 0x0 1040 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 1041 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1042 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 1043 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1044 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 1045 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1046 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 1047 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1048 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 1049 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1050 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 1051 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1052 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 1053 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1054 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 1055 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1056 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 1057 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1058 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 1059 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1060 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a 1061 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1062 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b 1063 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1064 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c 1065 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1066 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d 1067 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1068 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e 1069 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1070 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f 1071 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1072 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 1073 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 1074 1075 1076 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 1077 // base address: 0x0 1078 #define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb 1079 #define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 1080 #define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec 1081 #define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1082 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1083 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1084 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1085 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1086 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1087 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1088 #define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1089 #define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1090 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1091 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1092 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1093 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1094 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1095 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1096 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 1097 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1098 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 1099 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1100 #define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 1101 #define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 1102 #define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 1103 #define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 1104 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 1105 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1106 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 1107 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1108 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 1109 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1110 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 1111 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1112 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a 1113 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1114 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b 1115 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1116 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c 1117 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1118 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d 1119 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1120 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e 1121 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 1122 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f 1123 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 1124 #define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 1125 #define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 1126 1127 1128 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 1129 // base address: 0x0 1130 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 1131 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 1132 #define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 1133 #define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 1134 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 1135 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 1136 1137 1138 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 1139 // base address: 0x0 1140 #define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 1141 #define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 1142 #define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 1143 #define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 1144 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 1145 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1146 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 1147 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 1148 #define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1149 #define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1150 1151 1152 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 1153 // base address: 0x0 1154 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 1155 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1156 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 1157 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1158 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 1159 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1160 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 1161 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1162 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 1163 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1164 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 1165 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1166 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 1167 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1168 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 1169 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1170 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 1171 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1172 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 1173 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1174 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a 1175 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1176 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b 1177 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1178 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c 1179 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1180 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d 1181 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1182 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e 1183 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1184 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f 1185 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1186 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 1187 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 1188 1189 1190 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 1191 // base address: 0x0 1192 #define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb 1193 #define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 1194 #define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec 1195 #define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1196 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1197 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1198 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1199 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1200 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1201 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1202 #define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1203 #define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1204 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1205 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1206 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1207 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1208 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1209 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1210 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 1211 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1212 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 1213 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1214 #define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 1215 #define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 1216 #define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 1217 #define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 1218 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 1219 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1220 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 1221 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1222 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 1223 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1224 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 1225 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1226 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a 1227 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1228 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b 1229 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1230 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c 1231 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1232 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d 1233 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1234 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e 1235 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 1236 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f 1237 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 1238 #define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 1239 #define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 1240 1241 1242 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 1243 // base address: 0x0 1244 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 1245 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 1246 #define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 1247 #define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 1248 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 1249 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 1250 1251 1252 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 1253 // base address: 0x0 1254 #define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 1255 #define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 1256 #define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 1257 #define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 1258 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 1259 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1260 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 1261 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 1262 #define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1263 #define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1264 1265 1266 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 1267 // base address: 0x0 1268 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 1269 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1270 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 1271 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1272 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 1273 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1274 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 1275 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1276 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 1277 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1278 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 1279 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1280 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 1281 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1282 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 1283 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1284 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 1285 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1286 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 1287 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1288 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a 1289 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1290 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b 1291 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1292 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c 1293 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1294 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d 1295 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1296 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e 1297 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1298 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f 1299 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1300 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 1301 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 1302 1303 1304 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 1305 // base address: 0x0 1306 #define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb 1307 #define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 1308 #define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec 1309 #define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1310 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1311 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1312 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1313 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1314 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1315 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1316 #define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1317 #define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1318 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1319 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1320 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1321 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1322 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1323 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1324 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 1325 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1326 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 1327 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1328 #define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 1329 #define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 1330 #define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 1331 #define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 1332 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 1333 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1334 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 1335 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1336 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 1337 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1338 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 1339 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1340 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a 1341 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1342 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b 1343 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1344 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c 1345 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1346 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d 1347 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1348 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e 1349 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 1350 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f 1351 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 1352 #define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 1353 #define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 1354 1355 1356 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 1357 // base address: 0x0 1358 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 1359 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 1360 #define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 1361 #define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 1362 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 1363 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 1364 1365 1366 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 1367 // base address: 0x0 1368 #define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 1369 #define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 1370 #define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 1371 #define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 1372 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 1373 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1374 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 1375 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 1376 #define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1377 #define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1378 1379 1380 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 1381 // base address: 0x0 1382 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 1383 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1384 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 1385 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1386 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 1387 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1388 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 1389 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1390 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 1391 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1392 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 1393 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1394 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 1395 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1396 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 1397 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1398 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 1399 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1400 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 1401 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1402 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a 1403 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1404 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b 1405 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1406 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c 1407 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1408 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d 1409 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1410 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e 1411 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1412 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f 1413 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1414 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 1415 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 1416 1417 1418 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 1419 // base address: 0x0 1420 #define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb 1421 #define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 1422 #define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec 1423 #define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1424 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1425 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1426 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1427 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1428 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1429 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1430 #define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1431 #define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1432 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1433 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1434 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1435 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1436 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1437 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1438 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 1439 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1440 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 1441 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1442 #define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 1443 #define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 1444 #define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 1445 #define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 1446 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 1447 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1448 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 1449 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1450 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 1451 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1452 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 1453 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1454 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a 1455 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1456 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b 1457 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1458 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c 1459 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1460 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d 1461 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1462 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e 1463 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 1464 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f 1465 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 1466 #define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 1467 #define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 1468 1469 1470 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 1471 // base address: 0x0 1472 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 1473 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 1474 #define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 1475 #define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 1476 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 1477 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 1478 1479 1480 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 1481 // base address: 0x0 1482 #define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 1483 #define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 1484 #define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 1485 #define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 1486 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 1487 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1488 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 1489 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 1490 #define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1491 #define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1492 1493 1494 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 1495 // base address: 0x0 1496 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 1497 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1498 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 1499 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1500 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 1501 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1502 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 1503 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1504 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 1505 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1506 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 1507 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1508 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 1509 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1510 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 1511 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1512 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 1513 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1514 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 1515 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1516 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a 1517 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1518 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b 1519 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1520 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c 1521 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1522 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d 1523 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1524 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e 1525 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1526 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f 1527 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1528 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 1529 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 1530 1531 1532 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 1533 // base address: 0x0 1534 #define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb 1535 #define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 1536 #define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec 1537 #define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1538 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1539 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1540 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1541 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1542 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1543 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1544 #define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1545 #define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1546 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1547 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1548 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1549 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1550 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1551 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1552 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 1553 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1554 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 1555 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1556 #define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 1557 #define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 1558 #define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 1559 #define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 1560 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 1561 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1562 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 1563 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1564 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 1565 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1566 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 1567 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1568 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a 1569 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1570 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b 1571 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1572 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c 1573 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1574 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d 1575 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1576 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e 1577 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 1578 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f 1579 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 1580 #define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 1581 #define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 1582 1583 1584 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 1585 // base address: 0x0 1586 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 1587 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 1588 #define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 1589 #define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 1590 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 1591 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 1592 1593 1594 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 1595 // base address: 0x0 1596 #define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 1597 #define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 1598 #define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 1599 #define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 1600 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 1601 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1602 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 1603 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 1604 #define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1605 #define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1606 1607 1608 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 1609 // base address: 0x0 1610 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 1611 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1612 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 1613 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1614 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 1615 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1616 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 1617 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1618 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 1619 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1620 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 1621 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1622 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 1623 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1624 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 1625 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1626 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 1627 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1628 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 1629 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1630 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a 1631 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1632 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b 1633 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1634 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c 1635 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1636 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d 1637 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1638 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e 1639 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1640 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f 1641 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1642 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 1643 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 1644 1645 1646 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 1647 // base address: 0x0 1648 #define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb 1649 #define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 1650 #define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec 1651 #define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1652 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1653 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1654 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1655 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1656 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1657 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1658 #define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1659 #define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1660 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1661 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1662 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1663 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1664 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1665 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1666 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 1667 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1668 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 1669 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1670 #define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 1671 #define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 1672 #define regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 1673 #define regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 1674 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 1675 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1676 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 1677 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1678 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 1679 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1680 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 1681 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1682 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a 1683 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1684 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b 1685 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1686 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c 1687 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1688 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d 1689 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1690 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e 1691 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 1692 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f 1693 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 1694 #define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 1695 #define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 1696 1697 1698 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 1699 // base address: 0x0 1700 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 1701 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 1702 #define regBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 1703 #define regBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 1704 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 1705 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 1706 1707 1708 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 1709 // base address: 0x0 1710 #define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 1711 #define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 1712 #define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 1713 #define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 1714 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 1715 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1716 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 1717 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 1718 #define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1719 #define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1720 1721 1722 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 1723 // base address: 0x0 1724 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 1725 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1726 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 1727 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1728 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 1729 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1730 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 1731 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1732 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 1733 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1734 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 1735 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1736 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 1737 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1738 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 1739 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1740 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 1741 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1742 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 1743 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1744 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a 1745 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1746 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b 1747 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1748 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0x040c 1749 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1750 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0x040d 1751 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1752 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0x040e 1753 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1754 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0x040f 1755 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1756 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 1757 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 1758 1759 1760 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 1761 // base address: 0x0 1762 #define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb 1763 #define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 1764 #define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec 1765 #define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1766 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1767 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1768 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1769 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1770 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1771 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1772 #define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1773 #define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1774 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1775 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1776 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1777 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1778 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1779 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1780 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 1781 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1782 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 1783 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1784 #define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 1785 #define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 1786 #define regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 1787 #define regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 1788 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 1789 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1790 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 1791 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1792 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 1793 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1794 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 1795 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1796 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a 1797 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1798 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b 1799 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1800 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c 1801 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1802 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d 1803 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1804 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e 1805 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 1806 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f 1807 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 1808 #define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 1809 #define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 1810 1811 1812 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 1813 // base address: 0x0 1814 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 1815 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 1816 #define regBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 1817 #define regBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 1818 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 1819 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 1820 1821 1822 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 1823 // base address: 0x0 1824 #define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 1825 #define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 1826 #define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 1827 #define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 1828 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 1829 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1830 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 1831 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 1832 #define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1833 #define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1834 1835 1836 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 1837 // base address: 0x0 1838 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 1839 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1840 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 1841 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1842 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 1843 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1844 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 1845 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1846 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 1847 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1848 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 1849 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1850 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 1851 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1852 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 1853 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1854 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 1855 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1856 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 1857 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1858 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a 1859 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1860 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b 1861 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1862 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0x040c 1863 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1864 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0x040d 1865 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1866 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0x040e 1867 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1868 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0x040f 1869 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1870 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 1871 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 1872 1873 1874 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 1875 // base address: 0x0 1876 #define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb 1877 #define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 1878 #define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec 1879 #define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1880 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1881 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1882 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1883 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1884 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1885 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 1886 #define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 1887 #define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1888 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 1889 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 1890 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 1891 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 1892 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 1893 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 1894 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 1895 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 1896 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 1897 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 1898 #define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 1899 #define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 1900 #define regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 1901 #define regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 1902 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 1903 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 1904 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 1905 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 1906 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 1907 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 1908 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 1909 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 1910 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a 1911 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 1912 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b 1913 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 1914 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c 1915 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 1916 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d 1917 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 1918 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e 1919 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 1920 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f 1921 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 1922 #define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 1923 #define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 1924 1925 1926 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 1927 // base address: 0x0 1928 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 1929 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 1930 #define regBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 1931 #define regBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 1932 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 1933 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 1934 1935 1936 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 1937 // base address: 0x0 1938 #define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 1939 #define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 1940 #define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 1941 #define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 1942 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 1943 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 1944 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 1945 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 1946 #define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 1947 #define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 1948 1949 1950 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 1951 // base address: 0x0 1952 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 1953 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 1954 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 1955 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 1956 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 1957 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 1958 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 1959 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 1960 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 1961 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 1962 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 1963 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 1964 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 1965 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 1966 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 1967 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 1968 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 1969 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 1970 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 1971 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 1972 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a 1973 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 1974 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b 1975 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 1976 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0x040c 1977 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 1978 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0x040d 1979 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 1980 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0x040e 1981 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 1982 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0x040f 1983 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 1984 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 1985 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 1986 1987 1988 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 1989 // base address: 0x0 1990 #define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb 1991 #define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 1992 #define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec 1993 #define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 1994 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 1995 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 1996 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 1997 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 1998 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 1999 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2000 #define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2001 #define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2002 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2003 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2004 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 2005 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 2006 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 2007 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 2008 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 2009 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2010 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 2011 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2012 #define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 2013 #define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 2014 #define regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 2015 #define regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 2016 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 2017 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2018 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 2019 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2020 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 2021 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2022 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 2023 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2024 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a 2025 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2026 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b 2027 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2028 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c 2029 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2030 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d 2031 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2032 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e 2033 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 2034 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f 2035 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 2036 #define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 2037 #define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 2038 2039 2040 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 2041 // base address: 0x0 2042 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 2043 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 2044 #define regBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 2045 #define regBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 2046 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 2047 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 2048 2049 2050 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 2051 // base address: 0x0 2052 #define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 2053 #define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 2054 #define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 2055 #define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 2056 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 2057 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 2058 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 2059 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 2060 #define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 2061 #define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2062 2063 2064 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 2065 // base address: 0x0 2066 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 2067 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2068 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 2069 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2070 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 2071 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2072 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 2073 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 2074 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 2075 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2076 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 2077 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2078 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 2079 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2080 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 2081 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 2082 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 2083 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2084 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 2085 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2086 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a 2087 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2088 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b 2089 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 2090 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0x040c 2091 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 2092 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0x040d 2093 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 2094 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0x040e 2095 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 2096 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0x040f 2097 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 2098 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 2099 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 2100 2101 2102 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 2103 // base address: 0x0 2104 #define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb 2105 #define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 2106 #define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec 2107 #define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2108 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2109 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2110 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2111 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2112 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2113 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2114 #define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2115 #define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2116 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2117 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2118 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 2119 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 2120 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 2121 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 2122 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 2123 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2124 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 2125 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2126 #define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 2127 #define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 2128 #define regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 2129 #define regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 2130 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 2131 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2132 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 2133 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2134 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 2135 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2136 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 2137 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2138 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a 2139 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2140 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b 2141 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2142 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c 2143 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2144 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d 2145 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2146 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e 2147 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 2148 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f 2149 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 2150 #define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 2151 #define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 2152 2153 2154 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 2155 // base address: 0x0 2156 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 2157 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 2158 #define regBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 2159 #define regBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 2160 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 2161 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 2162 2163 2164 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 2165 // base address: 0x0 2166 #define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 2167 #define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 2168 #define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 2169 #define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 2170 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 2171 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 2172 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 2173 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 2174 #define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 2175 #define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2176 2177 2178 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 2179 // base address: 0x0 2180 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 2181 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2182 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 2183 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2184 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 2185 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2186 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 2187 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 2188 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 2189 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2190 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 2191 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2192 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 2193 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2194 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 2195 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 2196 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 2197 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2198 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 2199 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2200 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a 2201 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2202 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b 2203 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 2204 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0x040c 2205 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 2206 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0x040d 2207 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 2208 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0x040e 2209 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 2210 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0x040f 2211 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 2212 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 2213 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 2214 2215 2216 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 2217 // base address: 0x0 2218 #define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb 2219 #define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 2220 #define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec 2221 #define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2222 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2223 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2224 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2225 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2226 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2227 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2228 #define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2229 #define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2230 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2231 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2232 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 2233 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 2234 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 2235 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 2236 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 2237 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2238 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 2239 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2240 #define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 2241 #define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 2242 #define regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 2243 #define regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 2244 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 2245 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2246 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 2247 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2248 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 2249 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2250 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 2251 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2252 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a 2253 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2254 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b 2255 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2256 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c 2257 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2258 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d 2259 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2260 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e 2261 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 2262 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f 2263 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 2264 #define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 2265 #define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 2266 2267 2268 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 2269 // base address: 0x0 2270 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 2271 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 2272 #define regBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 2273 #define regBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 2274 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 2275 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 2276 2277 2278 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 2279 // base address: 0x0 2280 #define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 2281 #define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 2282 #define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 2283 #define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 2284 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 2285 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 2286 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 2287 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 2288 #define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 2289 #define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2290 2291 2292 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 2293 // base address: 0x0 2294 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 2295 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2296 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 2297 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2298 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 2299 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2300 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 2301 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 2302 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 2303 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2304 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 2305 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2306 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 2307 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2308 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 2309 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 2310 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 2311 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2312 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 2313 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2314 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a 2315 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2316 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b 2317 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 2318 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0x040c 2319 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 2320 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0x040d 2321 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 2322 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0x040e 2323 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 2324 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0x040f 2325 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 2326 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 2327 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 2328 2329 2330 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 2331 // base address: 0x0 2332 #define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb 2333 #define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 2334 #define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec 2335 #define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2336 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2337 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2338 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2339 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2340 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2341 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2342 #define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2343 #define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2344 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2345 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2346 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 2347 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 2348 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 2349 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 2350 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 2351 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2352 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 2353 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2354 #define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 2355 #define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 2356 #define regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 2357 #define regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 2358 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 2359 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2360 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 2361 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2362 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 2363 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2364 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 2365 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2366 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a 2367 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2368 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b 2369 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2370 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c 2371 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2372 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d 2373 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2374 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e 2375 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 2376 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f 2377 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 2378 #define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 2379 #define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 2380 2381 2382 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 2383 // base address: 0x0 2384 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 2385 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 2386 #define regBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 2387 #define regBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 2388 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 2389 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 2390 2391 2392 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 2393 // base address: 0x0 2394 #define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 2395 #define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 2396 #define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 2397 #define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 2398 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 2399 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 2400 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 2401 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 2402 #define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 2403 #define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2404 2405 2406 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 2407 // base address: 0x0 2408 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 2409 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2410 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 2411 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2412 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 2413 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2414 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 2415 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 2416 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 2417 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2418 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 2419 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2420 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 2421 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2422 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 2423 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 2424 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 2425 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2426 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 2427 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2428 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a 2429 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2430 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b 2431 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 2432 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0x040c 2433 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 2434 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0x040d 2435 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 2436 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0x040e 2437 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 2438 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0x040f 2439 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 2440 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 2441 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 2442 2443 2444 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 2445 // base address: 0x0 2446 #define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb 2447 #define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 2448 #define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec 2449 #define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2450 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2451 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2452 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2453 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2454 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2455 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2456 #define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2457 #define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2458 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2459 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2460 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 2461 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 2462 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 2463 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 2464 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 2465 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2466 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 2467 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2468 #define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 2469 #define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 2470 #define regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 2471 #define regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 2472 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 2473 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2474 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 2475 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2476 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 2477 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2478 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 2479 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2480 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a 2481 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2482 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b 2483 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2484 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c 2485 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2486 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d 2487 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2488 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e 2489 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 2490 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f 2491 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 2492 #define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 2493 #define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 2494 2495 2496 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 2497 // base address: 0x0 2498 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 2499 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 2500 #define regBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 2501 #define regBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 2502 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 2503 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 2504 2505 2506 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 2507 // base address: 0x0 2508 #define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 2509 #define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 2510 #define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 2511 #define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 2512 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 2513 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 2514 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 2515 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 2516 #define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 2517 #define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2518 2519 2520 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 2521 // base address: 0x0 2522 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 2523 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2524 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 2525 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2526 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 2527 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2528 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 2529 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 2530 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 2531 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2532 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 2533 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2534 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 2535 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2536 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 2537 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 2538 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 2539 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2540 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 2541 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2542 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a 2543 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2544 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b 2545 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 2546 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0x040c 2547 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 2548 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0x040d 2549 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 2550 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0x040e 2551 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 2552 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0x040f 2553 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 2554 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 2555 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 2556 2557 2558 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp 2559 // base address: 0xfffe00000000 2560 #define cfgPSWUSCFG0_0_VENDOR_ID 0xfffe00000000 2561 #define cfgPSWUSCFG0_0_DEVICE_ID 0xfffe00000002 2562 #define cfgPSWUSCFG0_0_COMMAND 0xfffe00000004 2563 #define cfgPSWUSCFG0_0_STATUS 0xfffe00000006 2564 #define cfgPSWUSCFG0_0_REVISION_ID 0xfffe00000008 2565 #define cfgPSWUSCFG0_0_PROG_INTERFACE 0xfffe00000009 2566 #define cfgPSWUSCFG0_0_SUB_CLASS 0xfffe0000000a 2567 #define cfgPSWUSCFG0_0_BASE_CLASS 0xfffe0000000b 2568 #define cfgPSWUSCFG0_0_CACHE_LINE 0xfffe0000000c 2569 #define cfgPSWUSCFG0_0_LATENCY 0xfffe0000000d 2570 #define cfgPSWUSCFG0_0_HEADER 0xfffe0000000e 2571 #define cfgPSWUSCFG0_0_BIST 0xfffe0000000f 2572 #define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY 0xfffe00000018 2573 #define cfgPSWUSCFG0_0_IO_BASE_LIMIT 0xfffe0000001c 2574 #define cfgPSWUSCFG0_0_SECONDARY_STATUS 0xfffe0000001e 2575 #define cfgPSWUSCFG0_0_MEM_BASE_LIMIT 0xfffe00000020 2576 #define cfgPSWUSCFG0_0_PREF_BASE_LIMIT 0xfffe00000024 2577 #define cfgPSWUSCFG0_0_PREF_BASE_UPPER 0xfffe00000028 2578 #define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER 0xfffe0000002c 2579 #define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI 0xfffe00000030 2580 #define cfgPSWUSCFG0_0_CAP_PTR 0xfffe00000034 2581 #define cfgPSWUSCFG0_0_ROM_BASE_ADDR 0xfffe00000038 2582 #define cfgPSWUSCFG0_0_INTERRUPT_LINE 0xfffe0000003c 2583 #define cfgPSWUSCFG0_0_INTERRUPT_PIN 0xfffe0000003d 2584 #define cfgPSWUSCFG0_0_VENDOR_CAP_LIST 0xfffe00000048 2585 #define cfgPSWUSCFG0_0_ADAPTER_ID_W 0xfffe0000004c 2586 #define cfgPSWUSCFG0_0_PMI_CAP_LIST 0xfffe00000050 2587 #define cfgPSWUSCFG0_0_PMI_CAP 0xfffe00000052 2588 #define cfgPSWUSCFG0_0_PMI_STATUS_CNTL 0xfffe00000054 2589 #define cfgPSWUSCFG0_0_PCIE_CAP_LIST 0xfffe00000058 2590 #define cfgPSWUSCFG0_0_PCIE_CAP 0xfffe0000005a 2591 #define cfgPSWUSCFG0_0_DEVICE_CAP 0xfffe0000005c 2592 #define cfgPSWUSCFG0_0_DEVICE_CNTL 0xfffe00000060 2593 #define cfgPSWUSCFG0_0_DEVICE_STATUS 0xfffe00000062 2594 #define cfgPSWUSCFG0_0_LINK_CAP 0xfffe00000064 2595 #define cfgPSWUSCFG0_0_LINK_CNTL 0xfffe00000068 2596 #define cfgPSWUSCFG0_0_LINK_STATUS 0xfffe0000006a 2597 #define cfgPSWUSCFG0_0_DEVICE_CAP2 0xfffe0000007c 2598 #define cfgPSWUSCFG0_0_DEVICE_CNTL2 0xfffe00000080 2599 #define cfgPSWUSCFG0_0_DEVICE_STATUS2 0xfffe00000082 2600 #define cfgPSWUSCFG0_0_LINK_CAP2 0xfffe00000084 2601 #define cfgPSWUSCFG0_0_LINK_CNTL2 0xfffe00000088 2602 #define cfgPSWUSCFG0_0_LINK_STATUS2 0xfffe0000008a 2603 #define cfgPSWUSCFG0_0_MSI_CAP_LIST 0xfffe000000a0 2604 #define cfgPSWUSCFG0_0_MSI_MSG_CNTL 0xfffe000000a2 2605 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO 0xfffe000000a4 2606 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI 0xfffe000000a8 2607 #define cfgPSWUSCFG0_0_MSI_MSG_DATA 0xfffe000000a8 2608 #define cfgPSWUSCFG0_0_MSI_MSG_DATA_64 0xfffe000000ac 2609 #define cfgPSWUSCFG0_0_SSID_CAP_LIST 0xfffe000000c0 2610 #define cfgPSWUSCFG0_0_SSID_CAP 0xfffe000000c4 2611 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe00000100 2612 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe00000104 2613 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 0xfffe00000108 2614 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 0xfffe0000010c 2615 #define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST 0xfffe00000110 2616 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 0xfffe00000114 2617 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 0xfffe00000118 2618 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL 0xfffe0000011c 2619 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS 0xfffe0000011e 2620 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP 0xfffe00000120 2621 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL 0xfffe00000124 2622 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS 0xfffe0000012a 2623 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP 0xfffe0000012c 2624 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL 0xfffe00000130 2625 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS 0xfffe00000136 2626 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe00000140 2627 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe00000144 2628 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe00000148 2629 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe00000150 2630 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS 0xfffe00000154 2631 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK 0xfffe00000158 2632 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe0000015c 2633 #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS 0xfffe00000160 2634 #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK 0xfffe00000164 2635 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe00000168 2636 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG0 0xfffe0000016c 2637 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG1 0xfffe00000170 2638 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG2 0xfffe00000174 2639 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG3 0xfffe00000178 2640 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 0xfffe00000188 2641 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 0xfffe0000018c 2642 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 0xfffe00000190 2643 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 0xfffe00000194 2644 #define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe00000270 2645 #define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3 0xfffe00000274 2646 #define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS 0xfffe00000278 2647 #define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe0000027c 2648 #define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe0000027e 2649 #define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe00000280 2650 #define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe00000282 2651 #define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe00000284 2652 #define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe00000286 2653 #define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe00000288 2654 #define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe0000028a 2655 #define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe0000028c 2656 #define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe0000028e 2657 #define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe00000290 2658 #define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe00000292 2659 #define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe00000294 2660 #define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe00000296 2661 #define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe00000298 2662 #define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe0000029a 2663 #define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST 0xfffe000002a0 2664 #define cfgPSWUSCFG0_0_PCIE_ACS_CAP 0xfffe000002a4 2665 #define cfgPSWUSCFG0_0_PCIE_ACS_CNTL 0xfffe000002a6 2666 #define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST 0xfffe000002f0 2667 #define cfgPSWUSCFG0_0_PCIE_MC_CAP 0xfffe000002f4 2668 #define cfgPSWUSCFG0_0_PCIE_MC_CNTL 0xfffe000002f6 2669 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR0 0xfffe000002f8 2670 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR1 0xfffe000002fc 2671 #define cfgPSWUSCFG0_0_PCIE_MC_RCV0 0xfffe00000300 2672 #define cfgPSWUSCFG0_0_PCIE_MC_RCV1 0xfffe00000304 2673 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 0xfffe00000308 2674 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 0xfffe0000030c 2675 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe00000310 2676 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe00000314 2677 #define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST 0xfffe00000320 2678 #define cfgPSWUSCFG0_0_PCIE_LTR_CAP 0xfffe00000324 2679 #define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe00000328 2680 #define cfgPSWUSCFG0_0_PCIE_ARI_CAP 0xfffe0000032c 2681 #define cfgPSWUSCFG0_0_PCIE_ARI_CNTL 0xfffe0000032e 2682 #define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST 0xfffe00000400 2683 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP 0xfffe00000404 2684 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS 0xfffe00000408 2685 #define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe00000410 2686 #define cfgPSWUSCFG0_0_LINK_CAP_16GT 0xfffe00000414 2687 #define cfgPSWUSCFG0_0_LINK_CNTL_16GT 0xfffe00000418 2688 #define cfgPSWUSCFG0_0_LINK_STATUS_16GT 0xfffe0000041c 2689 #define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe00000420 2690 #define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe00000424 2691 #define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe00000428 2692 #define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe00000430 2693 #define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe00000431 2694 #define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe00000432 2695 #define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe00000433 2696 #define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe00000434 2697 #define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe00000435 2698 #define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe00000436 2699 #define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe00000437 2700 #define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe00000438 2701 #define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe00000439 2702 #define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe0000043a 2703 #define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe0000043b 2704 #define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe0000043c 2705 #define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe0000043d 2706 #define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe0000043e 2707 #define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe0000043f 2708 #define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe00000440 2709 #define cfgPSWUSCFG0_0_MARGINING_PORT_CAP 0xfffe00000444 2710 #define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS 0xfffe00000446 2711 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL 0xfffe00000448 2712 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS 0xfffe0000044a 2713 #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL 0xfffe0000044c 2714 #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS 0xfffe0000044e 2715 #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL 0xfffe00000450 2716 #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS 0xfffe00000452 2717 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL 0xfffe00000454 2718 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS 0xfffe00000456 2719 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL 0xfffe00000458 2720 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS 0xfffe0000045a 2721 #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL 0xfffe0000045c 2722 #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS 0xfffe0000045e 2723 #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL 0xfffe00000460 2724 #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS 0xfffe00000462 2725 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL 0xfffe00000464 2726 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS 0xfffe00000466 2727 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL 0xfffe00000468 2728 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS 0xfffe0000046a 2729 #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL 0xfffe0000046c 2730 #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS 0xfffe0000046e 2731 #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL 0xfffe00000470 2732 #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS 0xfffe00000472 2733 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL 0xfffe00000474 2734 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS 0xfffe00000476 2735 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL 0xfffe00000478 2736 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS 0xfffe0000047a 2737 #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL 0xfffe0000047c 2738 #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS 0xfffe0000047e 2739 #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL 0xfffe00000480 2740 #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS 0xfffe00000482 2741 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL 0xfffe00000484 2742 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS 0xfffe00000486 2743 #define cfgPSWUSCFG0_0_LINK_CAP_32GT 0xfffe00000504 2744 #define cfgPSWUSCFG0_0_LINK_CNTL_32GT 0xfffe00000508 2745 #define cfgPSWUSCFG0_0_LINK_STATUS_32GT 0xfffe0000050c 2746 2747 2748 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp 2749 // base address: 0xfffe10100000 2750 #define cfgBIF_CFG_DEV0_RC0_VENDOR_ID 0xfffe10100000 2751 #define cfgBIF_CFG_DEV0_RC0_DEVICE_ID 0xfffe10100002 2752 #define cfgBIF_CFG_DEV0_RC0_COMMAND 0xfffe10100004 2753 #define cfgBIF_CFG_DEV0_RC0_STATUS 0xfffe10100006 2754 #define cfgBIF_CFG_DEV0_RC0_REVISION_ID 0xfffe10100008 2755 #define cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE 0xfffe10100009 2756 #define cfgBIF_CFG_DEV0_RC0_SUB_CLASS 0xfffe1010000a 2757 #define cfgBIF_CFG_DEV0_RC0_BASE_CLASS 0xfffe1010000b 2758 #define cfgBIF_CFG_DEV0_RC0_CACHE_LINE 0xfffe1010000c 2759 #define cfgBIF_CFG_DEV0_RC0_LATENCY 0xfffe1010000d 2760 #define cfgBIF_CFG_DEV0_RC0_HEADER 0xfffe1010000e 2761 #define cfgBIF_CFG_DEV0_RC0_BIST 0xfffe1010000f 2762 #define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1 0xfffe10100010 2763 #define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_2 0xfffe10100014 2764 #define cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0xfffe10100018 2765 #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0xfffe1010001c 2766 #define cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0xfffe1010001e 2767 #define cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0xfffe10100020 2768 #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0xfffe10100024 2769 #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0xfffe10100028 2770 #define cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0xfffe1010002c 2771 #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0xfffe10100030 2772 #define cfgBIF_CFG_DEV0_RC0_CAP_PTR 0xfffe10100034 2773 #define cfgBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0xfffe10100038 2774 #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0xfffe1010003c 2775 #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0xfffe1010003d 2776 #define cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0xfffe10100050 2777 #define cfgBIF_CFG_DEV0_RC0_PMI_CAP 0xfffe10100052 2778 #define cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0xfffe10100054 2779 #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0xfffe10100058 2780 #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP 0xfffe1010005a 2781 #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP 0xfffe1010005c 2782 #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL 0xfffe10100060 2783 #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS 0xfffe10100062 2784 #define cfgBIF_CFG_DEV0_RC0_LINK_CAP 0xfffe10100064 2785 #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL 0xfffe10100068 2786 #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS 0xfffe1010006a 2787 #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP 0xfffe1010006c 2788 #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL 0xfffe10100070 2789 #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS 0xfffe10100072 2790 #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2 0xfffe1010007c 2791 #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0xfffe10100080 2792 #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0xfffe10100082 2793 #define cfgBIF_CFG_DEV0_RC0_LINK_CAP2 0xfffe10100084 2794 #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL2 0xfffe10100088 2795 #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS2 0xfffe1010008a 2796 #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP2 0xfffe1010008c 2797 #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2 0xfffe10100090 2798 #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2 0xfffe10100092 2799 #define cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0xfffe101000a0 2800 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0xfffe101000a2 2801 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0xfffe101000a4 2802 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0xfffe101000a8 2803 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0xfffe101000a8 2804 #define cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0xfffe101000aa 2805 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0xfffe101000ac 2806 #define cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0xfffe101000ae 2807 #define cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0xfffe101000c0 2808 #define cfgBIF_CFG_DEV0_RC0_SSID_CAP 0xfffe101000c4 2809 #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10100100 2810 #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10100104 2811 #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0xfffe10100108 2812 #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0xfffe1010010c 2813 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0xfffe10100110 2814 #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0xfffe10100114 2815 #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0xfffe10100118 2816 #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0xfffe1010011c 2817 #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0xfffe1010011e 2818 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0xfffe10100120 2819 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0xfffe10100124 2820 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0xfffe1010012a 2821 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0xfffe1010012c 2822 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0xfffe10100130 2823 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0xfffe10100136 2824 #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10100140 2825 #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10100144 2826 #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10100148 2827 #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10100150 2828 #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0xfffe10100154 2829 #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0xfffe10100158 2830 #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1010015c 2831 #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0xfffe10100160 2832 #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0xfffe10100164 2833 #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10100168 2834 #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0xfffe1010016c 2835 #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0xfffe10100170 2836 #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0xfffe10100174 2837 #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0xfffe10100178 2838 #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0xfffe10100188 2839 #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0xfffe1010018c 2840 #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0xfffe10100190 2841 #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0xfffe10100194 2842 #define cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10100270 2843 #define cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0xfffe10100274 2844 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0xfffe10100278 2845 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1010027c 2846 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1010027e 2847 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10100280 2848 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10100282 2849 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10100284 2850 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10100286 2851 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10100288 2852 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1010028a 2853 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1010028c 2854 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1010028e 2855 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10100290 2856 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10100292 2857 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10100294 2858 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10100296 2859 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10100298 2860 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1010029a 2861 #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0xfffe101002a0 2862 #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0xfffe101002a4 2863 #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0xfffe101002a6 2864 #define cfgBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0xfffe10100400 2865 #define cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0xfffe10100404 2866 #define cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0xfffe10100408 2867 #define cfgBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10100410 2868 #define cfgBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0xfffe10100414 2869 #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0xfffe10100418 2870 #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0xfffe1010041c 2871 #define cfgBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10100420 2872 #define cfgBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10100424 2873 #define cfgBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10100428 2874 #define cfgBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10100430 2875 #define cfgBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10100431 2876 #define cfgBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10100432 2877 #define cfgBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10100433 2878 #define cfgBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10100434 2879 #define cfgBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10100435 2880 #define cfgBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10100436 2881 #define cfgBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10100437 2882 #define cfgBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10100438 2883 #define cfgBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10100439 2884 #define cfgBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1010043a 2885 #define cfgBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1010043b 2886 #define cfgBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1010043c 2887 #define cfgBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1010043d 2888 #define cfgBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1010043e 2889 #define cfgBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1010043f 2890 #define cfgBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10100450 2891 #define cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0xfffe10100454 2892 #define cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0xfffe10100456 2893 #define cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0xfffe10100458 2894 #define cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0xfffe1010045a 2895 #define cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0xfffe1010045c 2896 #define cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0xfffe1010045e 2897 #define cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0xfffe10100460 2898 #define cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0xfffe10100462 2899 #define cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0xfffe10100464 2900 #define cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0xfffe10100466 2901 #define cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0xfffe10100468 2902 #define cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0xfffe1010046a 2903 #define cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0xfffe1010046c 2904 #define cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0xfffe1010046e 2905 #define cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0xfffe10100470 2906 #define cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0xfffe10100472 2907 #define cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0xfffe10100474 2908 #define cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0xfffe10100476 2909 #define cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0xfffe10100478 2910 #define cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0xfffe1010047a 2911 #define cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0xfffe1010047c 2912 #define cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0xfffe1010047e 2913 #define cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0xfffe10100480 2914 #define cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0xfffe10100482 2915 #define cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0xfffe10100484 2916 #define cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0xfffe10100486 2917 #define cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0xfffe10100488 2918 #define cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0xfffe1010048a 2919 #define cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0xfffe1010048c 2920 #define cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0xfffe1010048e 2921 #define cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0xfffe10100490 2922 #define cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0xfffe10100492 2923 #define cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0xfffe10100494 2924 #define cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0xfffe10100496 2925 #define cfgBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0xfffe10100504 2926 #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0xfffe10100508 2927 #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0xfffe1010050c 2928 2929 2930 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 2931 // base address: 0xfffe10200000 2932 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0xfffe10200000 2933 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0xfffe10200002 2934 #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0xfffe10200004 2935 #define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0xfffe10200006 2936 #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0xfffe10200008 2937 #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0xfffe10200009 2938 #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0xfffe1020000a 2939 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0xfffe1020000b 2940 #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0xfffe1020000c 2941 #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0xfffe1020000d 2942 #define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0xfffe1020000e 2943 #define cfgBIF_CFG_DEV0_EPF0_0_BIST 0xfffe1020000f 2944 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0xfffe10200010 2945 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0xfffe10200014 2946 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0xfffe10200018 2947 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0xfffe1020001c 2948 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0xfffe10200020 2949 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0xfffe10200024 2950 #define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0xfffe10200028 2951 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0xfffe1020002c 2952 #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0xfffe10200030 2953 #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0xfffe10200034 2954 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0xfffe1020003c 2955 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0xfffe1020003d 2956 #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0xfffe1020003e 2957 #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0xfffe1020003f 2958 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0xfffe10200048 2959 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0xfffe1020004c 2960 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0xfffe10200050 2961 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0xfffe10200052 2962 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0xfffe10200054 2963 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0xfffe10200064 2964 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0xfffe10200066 2965 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0xfffe10200068 2966 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0xfffe1020006c 2967 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0xfffe1020006e 2968 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0xfffe10200070 2969 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0xfffe10200074 2970 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0xfffe10200076 2971 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0xfffe10200088 2972 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0xfffe1020008c 2973 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0xfffe1020008e 2974 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0xfffe10200090 2975 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0xfffe10200094 2976 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0xfffe10200096 2977 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0xfffe102000a0 2978 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0xfffe102000a2 2979 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0xfffe102000a4 2980 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0xfffe102000a8 2981 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0xfffe102000a8 2982 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0xfffe102000aa 2983 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0xfffe102000ac 2984 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0xfffe102000ac 2985 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0xfffe102000ae 2986 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0xfffe102000b0 2987 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0xfffe102000b0 2988 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0xfffe102000b4 2989 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0xfffe102000c0 2990 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0xfffe102000c2 2991 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0xfffe102000c4 2992 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0xfffe102000c8 2993 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10200100 2994 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10200104 2995 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0xfffe10200108 2996 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020010c 2997 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0xfffe10200110 2998 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0xfffe10200114 2999 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0xfffe10200118 3000 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0xfffe1020011c 3001 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0xfffe1020011e 3002 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0xfffe10200120 3003 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0xfffe10200124 3004 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0xfffe1020012a 3005 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0xfffe1020012c 3006 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0xfffe10200130 3007 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0xfffe10200136 3008 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10200140 3009 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10200144 3010 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10200148 3011 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10200150 3012 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0xfffe10200154 3013 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0xfffe10200158 3014 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020015c 3015 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0xfffe10200160 3016 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0xfffe10200164 3017 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10200168 3018 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0xfffe1020016c 3019 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0xfffe10200170 3020 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0xfffe10200174 3021 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0xfffe10200178 3022 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0xfffe10200188 3023 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020018c 3024 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0xfffe10200190 3025 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0xfffe10200194 3026 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10200200 3027 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0xfffe10200204 3028 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0xfffe10200208 3029 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0xfffe1020020c 3030 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0xfffe10200210 3031 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0xfffe10200214 3032 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0xfffe10200218 3033 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0xfffe1020021c 3034 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0xfffe10200220 3035 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0xfffe10200224 3036 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0xfffe10200228 3037 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0xfffe1020022c 3038 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0xfffe10200230 3039 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10200240 3040 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10200244 3041 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0xfffe10200248 3042 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0xfffe1020024c 3043 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10200250 3044 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0xfffe10200254 3045 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10200258 3046 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0xfffe1020025c 3047 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0xfffe1020025e 3048 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10200260 3049 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10200261 3050 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10200262 3051 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10200263 3052 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10200264 3053 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10200265 3054 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10200266 3055 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10200267 3056 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10200270 3057 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0xfffe10200274 3058 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0xfffe10200278 3059 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020027c 3060 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020027e 3061 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10200280 3062 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10200282 3063 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10200284 3064 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10200286 3065 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10200288 3066 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020028a 3067 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020028c 3068 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020028e 3069 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10200290 3070 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10200292 3071 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10200294 3072 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10200296 3073 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10200298 3074 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020029a 3075 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102002a0 3076 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0xfffe102002a4 3077 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0xfffe102002a6 3078 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102002d0 3079 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0xfffe102002d4 3080 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0xfffe102002d6 3081 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0xfffe102002f0 3082 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0xfffe102002f4 3083 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0xfffe102002f6 3084 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0xfffe102002f8 3085 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0xfffe102002fc 3086 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0xfffe10200300 3087 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0xfffe10200304 3088 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0xfffe10200308 3089 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0xfffe1020030c 3090 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10200310 3091 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10200314 3092 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0xfffe10200320 3093 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0xfffe10200324 3094 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10200328 3095 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0xfffe1020032c 3096 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0xfffe1020032e 3097 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10200330 3098 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0xfffe10200334 3099 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0xfffe10200338 3100 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0xfffe1020033a 3101 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0xfffe1020033c 3102 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0xfffe1020033e 3103 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0xfffe10200340 3104 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10200342 3105 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10200344 3106 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0xfffe10200346 3107 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020034a 3108 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020034c 3109 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10200350 3110 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10200354 3111 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10200358 3112 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020035c 3113 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10200360 3114 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10200364 3115 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10200368 3116 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020036c 3117 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0xfffe10200400 3118 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0xfffe10200404 3119 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0xfffe10200408 3120 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10200410 3121 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0xfffe10200414 3122 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0xfffe10200418 3123 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0xfffe1020041c 3124 #define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10200420 3125 #define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10200424 3126 #define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10200428 3127 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10200430 3128 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10200431 3129 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10200432 3130 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10200433 3131 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10200434 3132 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10200435 3133 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10200436 3134 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10200437 3135 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10200438 3136 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10200439 3137 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020043a 3138 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020043b 3139 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020043c 3140 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020043d 3141 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020043e 3142 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020043f 3143 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10200450 3144 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0xfffe10200454 3145 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0xfffe10200456 3146 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0xfffe10200458 3147 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0xfffe1020045a 3148 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0xfffe1020045c 3149 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0xfffe1020045e 3150 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0xfffe10200460 3151 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0xfffe10200462 3152 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0xfffe10200464 3153 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0xfffe10200466 3154 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0xfffe10200468 3155 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0xfffe1020046a 3156 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0xfffe1020046c 3157 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0xfffe1020046e 3158 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0xfffe10200470 3159 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0xfffe10200472 3160 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0xfffe10200474 3161 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0xfffe10200476 3162 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0xfffe10200478 3163 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0xfffe1020047a 3164 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0xfffe1020047c 3165 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0xfffe1020047e 3166 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0xfffe10200480 3167 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0xfffe10200482 3168 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0xfffe10200484 3169 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0xfffe10200486 3170 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0xfffe10200488 3171 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0xfffe1020048a 3172 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0xfffe1020048c 3173 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0xfffe1020048e 3174 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0xfffe10200490 3175 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0xfffe10200492 3176 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0xfffe10200494 3177 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0xfffe10200496 3178 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102004c0 3179 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102004c4 3180 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102004c8 3181 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102004cc 3182 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102004d0 3183 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102004d4 3184 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102004d8 3185 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102004dc 3186 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102004e0 3187 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102004e4 3188 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102004e8 3189 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102004ec 3190 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102004f0 3191 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0xfffe10200504 3192 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0xfffe10200508 3193 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0xfffe1020050c 3194 3195 3196 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 3197 // base address: 0xfffe10201000 3198 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0xfffe10201000 3199 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0xfffe10201002 3200 #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0xfffe10201004 3201 #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0xfffe10201006 3202 #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0xfffe10201008 3203 #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0xfffe10201009 3204 #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0xfffe1020100a 3205 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0xfffe1020100b 3206 #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0xfffe1020100c 3207 #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0xfffe1020100d 3208 #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0xfffe1020100e 3209 #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0xfffe1020100f 3210 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0xfffe10201010 3211 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0xfffe10201014 3212 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0xfffe10201018 3213 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0xfffe1020101c 3214 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0xfffe10201020 3215 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0xfffe10201024 3216 #define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0xfffe10201028 3217 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0xfffe1020102c 3218 #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0xfffe10201030 3219 #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0xfffe10201034 3220 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0xfffe1020103c 3221 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0xfffe1020103d 3222 #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0xfffe1020103e 3223 #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0xfffe1020103f 3224 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0xfffe10201048 3225 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0xfffe1020104c 3226 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0xfffe10201050 3227 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0xfffe10201052 3228 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0xfffe10201054 3229 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0xfffe10201064 3230 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0xfffe10201066 3231 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0xfffe10201068 3232 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0xfffe1020106c 3233 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0xfffe1020106e 3234 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0xfffe10201070 3235 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0xfffe10201074 3236 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0xfffe10201076 3237 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0xfffe10201088 3238 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0xfffe1020108c 3239 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0xfffe1020108e 3240 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0xfffe10201090 3241 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0xfffe10201094 3242 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0xfffe10201096 3243 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0xfffe102010a0 3244 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0xfffe102010a2 3245 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0xfffe102010a4 3246 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0xfffe102010a8 3247 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0xfffe102010a8 3248 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0xfffe102010aa 3249 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0xfffe102010ac 3250 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0xfffe102010ac 3251 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0xfffe102010ae 3252 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0xfffe102010b0 3253 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0xfffe102010b0 3254 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0xfffe102010b4 3255 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0xfffe102010c0 3256 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0xfffe102010c2 3257 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0xfffe102010c4 3258 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0xfffe102010c8 3259 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10201100 3260 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10201104 3261 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0xfffe10201108 3262 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020110c 3263 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10201140 3264 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10201144 3265 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10201148 3266 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10201150 3267 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0xfffe10201154 3268 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0xfffe10201158 3269 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020115c 3270 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0xfffe10201160 3271 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0xfffe10201164 3272 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10201168 3273 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0xfffe1020116c 3274 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0xfffe10201170 3275 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0xfffe10201174 3276 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0xfffe10201178 3277 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0xfffe10201188 3278 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020118c 3279 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0xfffe10201190 3280 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0xfffe10201194 3281 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10201200 3282 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0xfffe10201204 3283 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0xfffe10201208 3284 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0xfffe1020120c 3285 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0xfffe10201210 3286 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0xfffe10201214 3287 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0xfffe10201218 3288 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0xfffe1020121c 3289 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0xfffe10201220 3290 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0xfffe10201224 3291 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0xfffe10201228 3292 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0xfffe1020122c 3293 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0xfffe10201230 3294 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10201240 3295 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10201244 3296 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0xfffe10201248 3297 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0xfffe1020124c 3298 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10201250 3299 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0xfffe10201254 3300 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10201258 3301 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0xfffe1020125c 3302 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0xfffe1020125e 3303 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10201260 3304 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10201261 3305 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10201262 3306 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10201263 3307 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10201264 3308 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10201265 3309 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10201266 3310 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10201267 3311 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10201270 3312 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0xfffe10201274 3313 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0xfffe10201278 3314 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020127c 3315 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020127e 3316 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10201280 3317 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10201282 3318 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10201284 3319 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10201286 3320 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10201288 3321 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020128a 3322 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020128c 3323 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020128e 3324 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10201290 3325 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10201292 3326 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10201294 3327 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10201296 3328 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10201298 3329 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020129a 3330 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102012a0 3331 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0xfffe102012a4 3332 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0xfffe102012a6 3333 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102012d0 3334 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0xfffe102012d4 3335 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0xfffe102012d6 3336 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0xfffe102012f0 3337 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0xfffe102012f4 3338 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0xfffe102012f6 3339 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0xfffe102012f8 3340 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0xfffe102012fc 3341 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0xfffe10201300 3342 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0xfffe10201304 3343 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0xfffe10201308 3344 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0xfffe1020130c 3345 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10201310 3346 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10201314 3347 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0xfffe10201320 3348 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0xfffe10201324 3349 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10201328 3350 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0xfffe1020132c 3351 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0xfffe1020132e 3352 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10201330 3353 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0xfffe10201334 3354 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0xfffe10201338 3355 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0xfffe1020133a 3356 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0xfffe1020133c 3357 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0xfffe1020133e 3358 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0xfffe10201340 3359 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10201342 3360 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10201344 3361 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0xfffe10201346 3362 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020134a 3363 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020134c 3364 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10201350 3365 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10201354 3366 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10201358 3367 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020135c 3368 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10201360 3369 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10201364 3370 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10201368 3371 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020136c 3372 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102014c0 3373 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102014c4 3374 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102014c8 3375 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102014cc 3376 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102014d0 3377 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102014d4 3378 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102014d8 3379 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102014dc 3380 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102014e0 3381 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102014e4 3382 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102014e8 3383 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102014ec 3384 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102014f0 3385 3386 3387 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp 3388 // base address: 0xfffe10202000 3389 #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0xfffe10202000 3390 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0xfffe10202002 3391 #define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0xfffe10202004 3392 #define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0xfffe10202006 3393 #define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0xfffe10202008 3394 #define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0xfffe10202009 3395 #define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0xfffe1020200a 3396 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0xfffe1020200b 3397 #define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0xfffe1020200c 3398 #define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0xfffe1020200d 3399 #define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0xfffe1020200e 3400 #define cfgBIF_CFG_DEV0_EPF2_0_BIST 0xfffe1020200f 3401 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0xfffe10202010 3402 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0xfffe10202014 3403 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0xfffe10202018 3404 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0xfffe1020201c 3405 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0xfffe10202020 3406 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0xfffe10202024 3407 #define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR 0xfffe10202028 3408 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0xfffe1020202c 3409 #define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0xfffe10202030 3410 #define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0xfffe10202034 3411 #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0xfffe1020203c 3412 #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0xfffe1020203d 3413 #define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0xfffe1020203e 3414 #define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0xfffe1020203f 3415 #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0xfffe10202048 3416 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0xfffe1020204c 3417 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0xfffe10202050 3418 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0xfffe10202052 3419 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0xfffe10202054 3420 #define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0xfffe10202060 3421 #define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0xfffe10202061 3422 #define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0xfffe10202062 3423 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0xfffe10202064 3424 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0xfffe10202066 3425 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0xfffe10202068 3426 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0xfffe1020206c 3427 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0xfffe1020206e 3428 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0xfffe10202070 3429 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0xfffe10202074 3430 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0xfffe10202076 3431 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0xfffe10202088 3432 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0xfffe1020208c 3433 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0xfffe1020208e 3434 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0xfffe10202090 3435 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0xfffe10202094 3436 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0xfffe10202096 3437 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0xfffe102020a0 3438 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0xfffe102020a2 3439 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0xfffe102020a4 3440 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0xfffe102020a8 3441 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0xfffe102020a8 3442 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA 0xfffe102020aa 3443 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0xfffe102020ac 3444 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0xfffe102020ac 3445 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64 0xfffe102020ae 3446 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0xfffe102020b0 3447 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0xfffe102020b0 3448 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0xfffe102020b4 3449 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0xfffe102020c0 3450 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0xfffe102020c2 3451 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0xfffe102020c4 3452 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0xfffe102020c8 3453 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10202100 3454 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10202104 3455 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0xfffe10202108 3456 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020210c 3457 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10202150 3458 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0xfffe10202154 3459 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0xfffe10202158 3460 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020215c 3461 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0xfffe10202160 3462 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0xfffe10202164 3463 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10202168 3464 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0xfffe1020216c 3465 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0xfffe10202170 3466 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0xfffe10202174 3467 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0xfffe10202178 3468 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0xfffe10202188 3469 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020218c 3470 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0xfffe10202190 3471 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0xfffe10202194 3472 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10202200 3473 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0xfffe10202204 3474 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0xfffe10202208 3475 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0xfffe1020220c 3476 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0xfffe10202210 3477 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0xfffe10202214 3478 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0xfffe10202218 3479 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0xfffe1020221c 3480 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0xfffe10202220 3481 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0xfffe10202224 3482 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0xfffe10202228 3483 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0xfffe1020222c 3484 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0xfffe10202230 3485 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10202240 3486 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10202244 3487 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0xfffe10202248 3488 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0xfffe1020224c 3489 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10202250 3490 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0xfffe10202254 3491 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10202258 3492 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0xfffe1020225c 3493 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0xfffe1020225e 3494 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10202260 3495 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10202261 3496 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10202262 3497 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10202263 3498 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10202264 3499 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10202265 3500 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10202266 3501 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10202267 3502 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102022a0 3503 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0xfffe102022a4 3504 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0xfffe102022a6 3505 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102022d0 3506 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP 0xfffe102022d4 3507 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL 0xfffe102022d6 3508 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10202328 3509 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0xfffe1020232c 3510 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0xfffe1020232e 3511 3512 3513 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp 3514 // base address: 0xfffe10203000 3515 #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0xfffe10203000 3516 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0xfffe10203002 3517 #define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0xfffe10203004 3518 #define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0xfffe10203006 3519 #define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0xfffe10203008 3520 #define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0xfffe10203009 3521 #define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0xfffe1020300a 3522 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0xfffe1020300b 3523 #define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0xfffe1020300c 3524 #define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0xfffe1020300d 3525 #define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0xfffe1020300e 3526 #define cfgBIF_CFG_DEV0_EPF3_0_BIST 0xfffe1020300f 3527 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0xfffe10203010 3528 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0xfffe10203014 3529 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0xfffe10203018 3530 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0xfffe1020301c 3531 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0xfffe10203020 3532 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0xfffe10203024 3533 #define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR 0xfffe10203028 3534 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0xfffe1020302c 3535 #define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0xfffe10203030 3536 #define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0xfffe10203034 3537 #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0xfffe1020303c 3538 #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0xfffe1020303d 3539 #define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0xfffe1020303e 3540 #define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0xfffe1020303f 3541 #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0xfffe10203048 3542 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0xfffe1020304c 3543 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0xfffe10203050 3544 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0xfffe10203052 3545 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0xfffe10203054 3546 #define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0xfffe10203060 3547 #define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0xfffe10203061 3548 #define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0xfffe10203062 3549 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0xfffe10203064 3550 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0xfffe10203066 3551 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0xfffe10203068 3552 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0xfffe1020306c 3553 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0xfffe1020306e 3554 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0xfffe10203070 3555 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0xfffe10203074 3556 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0xfffe10203076 3557 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0xfffe10203088 3558 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0xfffe1020308c 3559 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0xfffe1020308e 3560 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0xfffe10203090 3561 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0xfffe10203094 3562 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0xfffe10203096 3563 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0xfffe102030a0 3564 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0xfffe102030a2 3565 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0xfffe102030a4 3566 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0xfffe102030a8 3567 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0xfffe102030a8 3568 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA 0xfffe102030aa 3569 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0xfffe102030ac 3570 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0xfffe102030ac 3571 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64 0xfffe102030ae 3572 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0xfffe102030b0 3573 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0xfffe102030b0 3574 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0xfffe102030b4 3575 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0xfffe102030c0 3576 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0xfffe102030c2 3577 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0xfffe102030c4 3578 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0xfffe102030c8 3579 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10203100 3580 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10203104 3581 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0xfffe10203108 3582 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020310c 3583 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10203150 3584 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0xfffe10203154 3585 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0xfffe10203158 3586 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020315c 3587 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0xfffe10203160 3588 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0xfffe10203164 3589 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10203168 3590 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0xfffe1020316c 3591 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0xfffe10203170 3592 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0xfffe10203174 3593 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0xfffe10203178 3594 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0xfffe10203188 3595 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020318c 3596 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0xfffe10203190 3597 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0xfffe10203194 3598 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10203200 3599 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0xfffe10203204 3600 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0xfffe10203208 3601 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0xfffe1020320c 3602 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0xfffe10203210 3603 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0xfffe10203214 3604 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0xfffe10203218 3605 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0xfffe1020321c 3606 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0xfffe10203220 3607 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0xfffe10203224 3608 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0xfffe10203228 3609 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0xfffe1020322c 3610 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0xfffe10203230 3611 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10203240 3612 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10203244 3613 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0xfffe10203248 3614 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0xfffe1020324c 3615 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10203250 3616 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0xfffe10203254 3617 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10203258 3618 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0xfffe1020325c 3619 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0xfffe1020325e 3620 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10203260 3621 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10203261 3622 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10203262 3623 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10203263 3624 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10203264 3625 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10203265 3626 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10203266 3627 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10203267 3628 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102032a0 3629 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0xfffe102032a4 3630 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0xfffe102032a6 3631 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102032d0 3632 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP 0xfffe102032d4 3633 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL 0xfffe102032d6 3634 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10203328 3635 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0xfffe1020332c 3636 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0xfffe1020332e 3637 3638 3639 // addressBlock: nbio_nbif0_bif_bx_SYSDEC 3640 // base address: 0x30200000 3641 #define cfgPCIE_INDEX 0x30200030 3642 #define cfgPCIE_DATA 0x30200034 3643 #define cfgPCIE_INDEX2 0x30200038 3644 #define cfgPCIE_DATA2 0x3020003c 3645 #define cfgPCIE_INDEX_HI 0x30200040 3646 #define cfgPCIE_INDEX2_HI 0x30200044 3647 #define cfgSBIOS_SCRATCH_0 0x30200120 3648 #define cfgSBIOS_SCRATCH_1 0x30200124 3649 #define cfgSBIOS_SCRATCH_2 0x30200128 3650 #define cfgSBIOS_SCRATCH_3 0x3020012c 3651 #define cfgBIOS_SCRATCH_0 0x30200130 3652 #define cfgBIOS_SCRATCH_1 0x30200134 3653 #define cfgBIOS_SCRATCH_2 0x30200138 3654 #define cfgBIOS_SCRATCH_3 0x3020013c 3655 #define cfgBIOS_SCRATCH_4 0x30200140 3656 #define cfgBIOS_SCRATCH_5 0x30200144 3657 #define cfgBIOS_SCRATCH_6 0x30200148 3658 #define cfgBIOS_SCRATCH_7 0x3020014c 3659 #define cfgBIOS_SCRATCH_8 0x30200150 3660 #define cfgBIOS_SCRATCH_9 0x30200154 3661 #define cfgBIOS_SCRATCH_10 0x30200158 3662 #define cfgBIOS_SCRATCH_11 0x3020015c 3663 #define cfgBIOS_SCRATCH_12 0x30200160 3664 #define cfgBIOS_SCRATCH_13 0x30200164 3665 #define cfgBIOS_SCRATCH_14 0x30200168 3666 #define cfgBIOS_SCRATCH_15 0x3020016c 3667 #define cfgBIF_RLC_INTR_CNTL 0x30200180 3668 #define cfgBIF_VCE_INTR_CNTL 0x30200184 3669 #define cfgBIF_UVD_INTR_CNTL 0x30200188 3670 #define cfgGFX_MMIOREG_CAM_ADDR0 0x30200200 3671 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR0 0x30200204 3672 #define cfgGFX_MMIOREG_CAM_ADDR1 0x30200208 3673 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR1 0x3020020c 3674 #define cfgGFX_MMIOREG_CAM_ADDR2 0x30200210 3675 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR2 0x30200214 3676 #define cfgGFX_MMIOREG_CAM_ADDR3 0x30200218 3677 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR3 0x3020021c 3678 #define cfgGFX_MMIOREG_CAM_ADDR4 0x30200220 3679 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR4 0x30200224 3680 #define cfgGFX_MMIOREG_CAM_ADDR5 0x30200228 3681 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR5 0x3020022c 3682 #define cfgGFX_MMIOREG_CAM_ADDR6 0x30200230 3683 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR6 0x30200234 3684 #define cfgGFX_MMIOREG_CAM_ADDR7 0x30200238 3685 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR7 0x3020023c 3686 #define cfgGFX_MMIOREG_CAM_CNTL 0x30200240 3687 #define cfgGFX_MMIOREG_CAM_ZERO_CPL 0x30200244 3688 #define cfgGFX_MMIOREG_CAM_ONE_CPL 0x30200248 3689 #define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x3020024c 3690 #define cfgDRIVER_SCRATCH_0 0x30200250 3691 #define cfgDRIVER_SCRATCH_1 0x30200254 3692 #define cfgDRIVER_SCRATCH_2 0x30200258 3693 #define cfgDRIVER_SCRATCH_3 0x3020025c 3694 #define cfgDRIVER_SCRATCH_4 0x30200260 3695 #define cfgDRIVER_SCRATCH_5 0x30200264 3696 #define cfgDRIVER_SCRATCH_6 0x30200268 3697 #define cfgDRIVER_SCRATCH_7 0x3020026c 3698 #define cfgDRIVER_SCRATCH_8 0x30200270 3699 #define cfgDRIVER_SCRATCH_9 0x30200274 3700 #define cfgDRIVER_SCRATCH_10 0x30200278 3701 #define cfgDRIVER_SCRATCH_11 0x3020027c 3702 #define cfgDRIVER_SCRATCH_12 0x30200280 3703 #define cfgDRIVER_SCRATCH_13 0x30200284 3704 #define cfgDRIVER_SCRATCH_14 0x30200288 3705 #define cfgDRIVER_SCRATCH_15 0x3020028c 3706 #define cfgFW_SCRATCH_0 0x30200290 3707 #define cfgFW_SCRATCH_1 0x30200294 3708 #define cfgFW_SCRATCH_2 0x30200298 3709 #define cfgFW_SCRATCH_3 0x3020029c 3710 #define cfgFW_SCRATCH_4 0x302002a0 3711 #define cfgFW_SCRATCH_5 0x302002a4 3712 #define cfgFW_SCRATCH_6 0x302002a8 3713 #define cfgFW_SCRATCH_7 0x302002ac 3714 #define cfgFW_SCRATCH_8 0x302002b0 3715 #define cfgFW_SCRATCH_9 0x302002b4 3716 #define cfgFW_SCRATCH_10 0x302002b8 3717 #define cfgFW_SCRATCH_11 0x302002bc 3718 #define cfgFW_SCRATCH_12 0x302002c0 3719 #define cfgFW_SCRATCH_13 0x302002c4 3720 #define cfgFW_SCRATCH_14 0x302002c8 3721 #define cfgFW_SCRATCH_15 0x302002cc 3722 #define cfgSBIOS_SCRATCH_4 0x302002d0 3723 #define cfgSBIOS_SCRATCH_5 0x302002d4 3724 #define cfgSBIOS_SCRATCH_6 0x302002d8 3725 #define cfgSBIOS_SCRATCH_7 0x302002dc 3726 #define cfgSBIOS_SCRATCH_8 0x302002e0 3727 #define cfgSBIOS_SCRATCH_9 0x302002e4 3728 #define cfgSBIOS_SCRATCH_10 0x302002e8 3729 #define cfgSBIOS_SCRATCH_11 0x302002ec 3730 #define cfgSBIOS_SCRATCH_12 0x302002f0 3731 #define cfgSBIOS_SCRATCH_13 0x302002f4 3732 #define cfgSBIOS_SCRATCH_14 0x302002f8 3733 #define cfgSBIOS_SCRATCH_15 0x302002fc 3734 3735 3736 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 3737 // base address: 0x30200000 3738 #define cfgDN_PCIE_RESERVED 0x30203600 3739 #define cfgDN_PCIE_SCRATCH 0x30203604 3740 #define cfgDN_PCIE_CNTL 0x3020360c 3741 #define cfgDN_PCIE_CONFIG_CNTL 0x30203610 3742 #define cfgDN_PCIE_RX_CNTL2 0x30203614 3743 #define cfgDN_PCIE_BUS_CNTL 0x30203618 3744 #define cfgDN_PCIE_CFG_CNTL 0x3020361c 3745 #define cfgDN_PCIE_STRAP_F0 0x30203620 3746 #define cfgDN_PCIE_STRAP_MISC 0x30203624 3747 #define cfgDN_PCIE_STRAP_MISC2 0x30203628 3748 3749 3750 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 3751 // base address: 0x30200000 3752 #define cfgPCIE_ERR_CNTL 0x30203630 3753 #define cfgPCIE_RX_CNTL 0x30203634 3754 #define cfgPCIE_LC_SPEED_CNTL 0x30203638 3755 #define cfgPCIE_LC_CNTL2 0x3020363c 3756 #define cfgPCIEP_STRAP_MISC 0x30203640 3757 #define cfgLTR_MSG_INFO_FROM_EP 0x30203644 3758 3759 3760 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 3761 // base address: 0x30200000 3762 #define cfgEP_PCIE_SCRATCH 0x30203580 3763 #define cfgEP_PCIE_CNTL 0x30203588 3764 #define cfgEP_PCIE_INT_CNTL 0x3020358c 3765 #define cfgEP_PCIE_INT_STATUS 0x30203590 3766 #define cfgEP_PCIE_RX_CNTL2 0x30203594 3767 #define cfgEP_PCIE_BUS_CNTL 0x30203598 3768 #define cfgEP_PCIE_CFG_CNTL 0x3020359c 3769 #define cfgEP_PCIE_TX_LTR_CNTL 0x302035a4 3770 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x302035a8 3771 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x302035a9 3772 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x302035aa 3773 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x302035ab 3774 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x302035ac 3775 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x302035ad 3776 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x302035ae 3777 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x302035af 3778 #define cfgEP_PCIE_STRAP_MISC 0x302035b0 3779 #define cfgEP_PCIE_STRAP_MISC2 0x302035b4 3780 #define cfgEP_PCIE_F0_DPA_CAP 0x302035bc 3781 #define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x302035c0 3782 #define cfgEP_PCIE_F0_DPA_CNTL 0x302035c1 3783 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x302035c3 3784 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x302035c4 3785 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x302035c5 3786 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x302035c6 3787 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x302035c7 3788 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x302035c8 3789 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x302035c9 3790 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x302035ca 3791 #define cfgEP_PCIE_PME_CONTROL 0x302035cb 3792 #define cfgEP_PCIEP_RESERVED 0x302035cc 3793 #define cfgEP_PCIE_TX_CNTL 0x302035d4 3794 #define cfgEP_PCIE_TX_REQUESTER_ID 0x302035d8 3795 #define cfgEP_PCIE_ERR_CNTL 0x302035dc 3796 #define cfgEP_PCIE_RX_CNTL 0x302035e0 3797 #define cfgEP_PCIE_LC_SPEED_CNTL 0x302035e4 3798 3799 3800 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 3801 // base address: 0x30200000 3802 #define cfgBIF_BX_PF0_MM_INDEX 0x30200000 3803 #define cfgBIF_BX_PF0_MM_DATA 0x30200004 3804 #define cfgBIF_BX_PF0_MM_INDEX_HI 0x30200018 3805 3806 3807 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 3808 // base address: 0x30200000 3809 #define cfgCC_BIF_BX_STRAP0 0x30203808 3810 #define cfgCC_BIF_BX_PINSTRAP0 0x30203810 3811 #define cfgBIF_MM_INDACCESS_CNTL 0x30203818 3812 #define cfgBUS_CNTL 0x3020381c 3813 #define cfgBIF_SCRATCH0 0x30203820 3814 #define cfgBIF_SCRATCH1 0x30203824 3815 #define cfgBX_RESET_EN 0x30203834 3816 #define cfgMM_CFGREGS_CNTL 0x30203838 3817 #define cfgBX_RESET_CNTL 0x30203840 3818 #define cfgINTERRUPT_CNTL 0x30203844 3819 #define cfgINTERRUPT_CNTL2 0x30203848 3820 #define cfgCLKREQB_PAD_CNTL 0x30203860 3821 #define cfgBIF_FEATURES_CONTROL_MISC 0x3020386c 3822 #define cfgHDP_ATOMIC_CONTROL_MISC 0x30203870 3823 #define cfgBIF_DOORBELL_CNTL 0x30203874 3824 #define cfgBIF_DOORBELL_INT_CNTL 0x30203878 3825 #define cfgBIF_FB_EN 0x30203880 3826 #define cfgBIF_INTR_CNTL 0x30203884 3827 #define cfgBIF_MST_TRANS_PENDING_VF 0x302038a4 3828 #define cfgBIF_SLV_TRANS_PENDING_VF 0x302038a8 3829 #define cfgBACO_CNTL 0x302038ac 3830 #define cfgBIF_BACO_EXIT_TIME0 0x302038b0 3831 #define cfgBIF_BACO_EXIT_TIMER1 0x302038b4 3832 #define cfgBIF_BACO_EXIT_TIMER2 0x302038b8 3833 #define cfgBIF_BACO_EXIT_TIMER3 0x302038bc 3834 #define cfgBIF_BACO_EXIT_TIMER4 0x302038c0 3835 #define cfgMEM_TYPE_CNTL 0x302038c4 3836 #define cfgNBIF_GFX_ADDR_LUT_CNTL 0x302038cc 3837 #define cfgNBIF_GFX_ADDR_LUT_0 0x302038d0 3838 #define cfgNBIF_GFX_ADDR_LUT_1 0x302038d4 3839 #define cfgNBIF_GFX_ADDR_LUT_2 0x302038d8 3840 #define cfgNBIF_GFX_ADDR_LUT_3 0x302038dc 3841 #define cfgNBIF_GFX_ADDR_LUT_4 0x302038e0 3842 #define cfgNBIF_GFX_ADDR_LUT_5 0x302038e4 3843 #define cfgNBIF_GFX_ADDR_LUT_6 0x302038e8 3844 #define cfgNBIF_GFX_ADDR_LUT_7 0x302038ec 3845 #define cfgNBIF_GFX_ADDR_LUT_8 0x302038f0 3846 #define cfgNBIF_GFX_ADDR_LUT_9 0x302038f4 3847 #define cfgNBIF_GFX_ADDR_LUT_10 0x302038f8 3848 #define cfgNBIF_GFX_ADDR_LUT_11 0x302038fc 3849 #define cfgNBIF_GFX_ADDR_LUT_12 0x30203900 3850 #define cfgNBIF_GFX_ADDR_LUT_13 0x30203904 3851 #define cfgNBIF_GFX_ADDR_LUT_14 0x30203908 3852 #define cfgNBIF_GFX_ADDR_LUT_15 0x3020390c 3853 #define cfgREMAP_HDP_MEM_FLUSH_CNTL 0x30203934 3854 #define cfgREMAP_HDP_REG_FLUSH_CNTL 0x30203938 3855 #define cfgBIF_RB_CNTL 0x3020393c 3856 #define cfgBIF_RB_BASE 0x30203940 3857 #define cfgBIF_RB_RPTR 0x30203944 3858 #define cfgBIF_RB_WPTR 0x30203948 3859 #define cfgBIF_RB_WPTR_ADDR_HI 0x3020394c 3860 #define cfgBIF_RB_WPTR_ADDR_LO 0x30203950 3861 #define cfgMAILBOX_INDEX 0x30203954 3862 #define cfgBIF_MP1_INTR_CTRL 0x30203988 3863 #define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x30203994 3864 #define cfgBIF_PERSTB_PAD_CNTL 0x302039a0 3865 #define cfgBIF_PX_EN_PAD_CNTL 0x302039a4 3866 #define cfgBIF_REFPADKIN_PAD_CNTL 0x302039a8 3867 #define cfgBIF_CLKREQB_PAD_CNTL 0x302039ac 3868 #define cfgBIF_PWRBRK_PAD_CNTL 0x302039b0 3869 #define cfgBIF_WAKEB_PAD_CNTL 0x302039b4 3870 #define cfgBIF_VAUX_PRESENT_PAD_CNTL 0x302039b8 3871 3872 3873 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 3874 // base address: 0x30200000 3875 #define cfgRCC_ERR_INT_CNTL 0x30203698 3876 #define cfgRCC_BACO_CNTL_MISC 0x3020369c 3877 #define cfgRCC_RESET_EN 0x302036a0 3878 #define cfgRCC_VDM_SUPPORT 0x302036a4 3879 #define cfgRCC_MARGIN_PARAM_CNTL0 0x302036a8 3880 #define cfgRCC_MARGIN_PARAM_CNTL1 0x302036ac 3881 #define cfgRCC_GPUIOV_REGION 0x302036b0 3882 #define cfgRCC_PEER_REG_RANGE0 0x30203778 3883 #define cfgRCC_PEER_REG_RANGE1 0x3020377c 3884 #define cfgRCC_BUS_CNTL 0x30203784 3885 #define cfgRCC_CONFIG_CNTL 0x30203788 3886 #define cfgRCC_CONFIG_F0_BASE 0x30203798 3887 #define cfgRCC_CONFIG_APER_SIZE 0x3020379c 3888 #define cfgRCC_CONFIG_REG_APER_SIZE 0x302037a0 3889 #define cfgRCC_XDMA_LO 0x302037a4 3890 #define cfgRCC_XDMA_HI 0x302037a8 3891 #define cfgRCC_FEATURES_CONTROL_MISC 0x302037ac 3892 #define cfgRCC_BUSNUM_CNTL1 0x302037b0 3893 #define cfgRCC_BUSNUM_LIST0 0x302037b4 3894 #define cfgRCC_BUSNUM_LIST1 0x302037b8 3895 #define cfgRCC_BUSNUM_CNTL2 0x302037bc 3896 #define cfgRCC_CAPTURE_HOST_BUSNUM 0x302037c0 3897 #define cfgRCC_HOST_BUSNUM 0x302037c4 3898 #define cfgRCC_PEER0_FB_OFFSET_HI 0x302037c8 3899 #define cfgRCC_PEER0_FB_OFFSET_LO 0x302037cc 3900 #define cfgRCC_PEER1_FB_OFFSET_HI 0x302037d0 3901 #define cfgRCC_PEER1_FB_OFFSET_LO 0x302037d4 3902 #define cfgRCC_PEER2_FB_OFFSET_HI 0x302037d8 3903 #define cfgRCC_PEER2_FB_OFFSET_LO 0x302037dc 3904 #define cfgRCC_PEER3_FB_OFFSET_HI 0x302037e0 3905 #define cfgRCC_PEER3_FB_OFFSET_LO 0x302037e4 3906 #define cfgRCC_DEVFUNCNUM_LIST0 0x302037e8 3907 #define cfgRCC_DEVFUNCNUM_LIST1 0x302037ec 3908 #define cfgRCC_DEV0_LINK_CNTL 0x302037f4 3909 #define cfgRCC_CMN_LINK_CNTL 0x302037f8 3910 #define cfgRCC_EP_REQUESTERID_RESTORE 0x302037fc 3911 #define cfgRCC_LTR_LSWITCH_CNTL 0x30203800 3912 #define cfgRCC_MH_ARB_CNTL 0x30203804 3913 3914 3915 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 3916 // base address: 0x30200000 3917 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x30242000 3918 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x30242004 3919 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x30242008 3920 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x3024200c 3921 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x30242010 3922 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x30242014 3923 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x30242018 3924 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x3024201c 3925 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x30242020 3926 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x30242024 3927 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x30242028 3928 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x3024202c 3929 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x30242030 3930 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x30242034 3931 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x30242038 3932 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x3024203c 3933 #define cfgRCC_DEV0_EPF0_GFXMSIX_PBA 0x30243000 3934 3935 3936 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 3937 // base address: 0x30200000 3938 #define cfgRCC_BIF_STRAP0 0x30203480 3939 #define cfgRCC_BIF_STRAP1 0x30203484 3940 #define cfgRCC_BIF_STRAP2 0x30203488 3941 #define cfgRCC_BIF_STRAP3 0x3020348c 3942 #define cfgRCC_BIF_STRAP4 0x30203490 3943 #define cfgRCC_BIF_STRAP5 0x30203494 3944 #define cfgRCC_BIF_STRAP6 0x30203498 3945 #define cfgRCC_DEV0_PORT_STRAP0 0x3020349c 3946 #define cfgRCC_DEV0_PORT_STRAP1 0x302034a0 3947 #define cfgRCC_DEV0_PORT_STRAP10 0x302034a4 3948 #define cfgRCC_DEV0_PORT_STRAP11 0x302034a8 3949 #define cfgRCC_DEV0_PORT_STRAP12 0x302034ac 3950 #define cfgRCC_DEV0_PORT_STRAP13 0x302034b0 3951 #define cfgRCC_DEV0_PORT_STRAP14 0x302034b4 3952 #define cfgRCC_DEV0_PORT_STRAP2 0x302034b8 3953 #define cfgRCC_DEV0_PORT_STRAP3 0x302034bc 3954 #define cfgRCC_DEV0_PORT_STRAP4 0x302034c0 3955 #define cfgRCC_DEV0_PORT_STRAP5 0x302034c4 3956 #define cfgRCC_DEV0_PORT_STRAP6 0x302034c8 3957 #define cfgRCC_DEV0_PORT_STRAP7 0x302034cc 3958 #define cfgRCC_DEV0_PORT_STRAP8 0x302034d0 3959 #define cfgRCC_DEV0_PORT_STRAP9 0x302034d4 3960 #define cfgRCC_DEV0_EPF0_STRAP0 0x302034d8 3961 #define cfgRCC_DEV0_EPF0_STRAP1 0x302034dc 3962 #define cfgRCC_DEV0_EPF0_STRAP13 0x302034e0 3963 #define cfgRCC_DEV0_EPF0_STRAP14 0x302034e4 3964 #define cfgRCC_DEV0_EPF0_STRAP15 0x302034e8 3965 #define cfgRCC_DEV0_EPF0_STRAP16 0x302034ec 3966 #define cfgRCC_DEV0_EPF0_STRAP17 0x302034f0 3967 #define cfgRCC_DEV0_EPF0_STRAP18 0x302034f4 3968 #define cfgRCC_DEV0_EPF0_STRAP2 0x302034f8 3969 #define cfgRCC_DEV0_EPF0_STRAP26 0x302034fc 3970 #define cfgRCC_DEV0_EPF0_STRAP3 0x30203500 3971 #define cfgRCC_DEV0_EPF0_STRAP4 0x30203504 3972 #define cfgRCC_DEV0_EPF0_STRAP5 0x30203508 3973 #define cfgRCC_DEV0_EPF0_STRAP8 0x3020350c 3974 #define cfgRCC_DEV0_EPF0_STRAP9 0x30203510 3975 #define cfgRCC_DEV0_EPF1_STRAP0 0x30203514 3976 #define cfgRCC_DEV0_EPF1_STRAP2 0x30203544 3977 #define cfgRCC_DEV0_EPF1_STRAP20 0x30203548 3978 #define cfgRCC_DEV0_EPF1_STRAP21 0x3020354c 3979 #define cfgRCC_DEV0_EPF1_STRAP22 0x30203550 3980 #define cfgRCC_DEV0_EPF1_STRAP23 0x30203554 3981 #define cfgRCC_DEV0_EPF1_STRAP24 0x30203558 3982 #define cfgRCC_DEV0_EPF1_STRAP25 0x3020355c 3983 #define cfgRCC_DEV0_EPF1_STRAP3 0x30203560 3984 #define cfgRCC_DEV0_EPF1_STRAP4 0x30203564 3985 #define cfgRCC_DEV0_EPF1_STRAP5 0x30203568 3986 #define cfgRCC_DEV0_EPF1_STRAP6 0x3020356c 3987 #define cfgRCC_DEV0_EPF1_STRAP7 0x30203570 3988 3989 3990 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 3991 // base address: 0x30200000 3992 #define cfgBIF_BX_PF_BIF_BME_STATUS 0x3020382c 3993 #define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x30203830 3994 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x3020384c 3995 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x30203850 3996 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x30203854 3997 #define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x30203858 3998 #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x3020385c 3999 #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x30203864 4000 #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x30203868 4001 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x30203898 4002 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x3020389c 4003 #define cfgBIF_BX_PF_BIF_TRANS_PENDING 0x302038a0 4004 #define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x302038c8 4005 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x30203958 4006 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x3020395c 4007 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x30203960 4008 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x30203964 4009 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x30203968 4010 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x3020396c 4011 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x30203970 4012 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x30203974 4013 #define cfgBIF_BX_PF_MAILBOX_CONTROL 0x30203978 4014 #define cfgBIF_BX_PF_MAILBOX_INT_CNTL 0x3020397c 4015 #define cfgBIF_BX_PF_BIF_VMHV_MAILBOX 0x30203980 4016 4017 4018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] 4019 // base address: 0x30203480 4020 #define cfgRCC_DEV0_EPF0_RCC_ERR_LOG 0x30203694 4021 #define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x30203780 4022 #define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x3020378c 4023 #define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x30203790 4024 #define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x30203794 4025 4026 4027 // addressBlock: nbio_nbif0_gdc_GDCDEC 4028 // base address: 0x30200000 4029 #define cfgSHUB_REGS_IF_CTL 0x30203b8c 4030 #define cfgNGDC_MGCG_CTRL 0x30203ba8 4031 #define cfgNGDC_RESERVED_0 0x30203bac 4032 #define cfgNGDC_RESERVED_1 0x30203bb0 4033 #define cfgATDMA_MISC_CNTL 0x30203bf4 4034 #define cfgS2A_MISC_CNTL 0x30203bfc 4035 #define cfgNGDC_PG_MISC_CTRL 0x30203c60 4036 #define cfgNGDC_PGMST_CTRL 0x30203c64 4037 #define cfgNGDC_PGSLV_CTRL 0x30203c68 4038 4039 4040 // addressBlock: nbio_nbif0_bif_swus_SUMDEC 4041 // base address: 0x100000 4042 #define cfgSUM_INDEX 0x1000e0 4043 #define cfgSUM_DATA 0x1000e4 4044 #define cfgSUM_INDEX_HI 0x1000ec 4045 4046 4047 // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec 4048 // base address: 0xfffe30000000 4049 #define cfgSHADOW_COMMAND 0xfffe30000004 4050 #define cfgSHADOW_BASE_ADDR_1 0xfffe30000010 4051 #define cfgSHADOW_BASE_ADDR_2 0xfffe30000014 4052 #define cfgSHADOW_SUB_BUS_NUMBER_LATENCY 0xfffe30000018 4053 #define cfgSHADOW_IO_BASE_LIMIT 0xfffe3000001c 4054 #define cfgSHADOW_MEM_BASE_LIMIT 0xfffe30000020 4055 #define cfgSHADOW_PREF_BASE_LIMIT 0xfffe30000024 4056 #define cfgSHADOW_PREF_BASE_UPPER 0xfffe30000028 4057 #define cfgSHADOW_PREF_LIMIT_UPPER 0xfffe3000002c 4058 #define cfgSHADOW_IO_BASE_LIMIT_HI 0xfffe30000030 4059 #define cfgSUC_INDEX 0xfffe300000e0 4060 #define cfgSUC_DATA 0xfffe300000e4 4061 4062 4063 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 4064 // base address: 0x0 4065 #define cfgBIF_BX_PF1_MM_INDEX 0x0000 4066 #define cfgBIF_BX_PF1_MM_DATA 0x0004 4067 #define cfgBIF_BX_PF1_MM_INDEX_HI 0x0018 4068 4069 4070 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 4071 // base address: 0xfffe10300000 4072 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0xfffe10300000 4073 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0xfffe10300002 4074 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0xfffe10300004 4075 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0xfffe10300006 4076 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0xfffe10300008 4077 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0xfffe10300009 4078 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0xfffe1030000a 4079 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0xfffe1030000b 4080 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0xfffe1030000c 4081 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0xfffe1030000d 4082 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0xfffe1030000e 4083 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0xfffe1030000f 4084 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0xfffe10300010 4085 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0xfffe10300014 4086 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0xfffe10300018 4087 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0xfffe1030001c 4088 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0xfffe10300020 4089 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0xfffe10300024 4090 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR 0xfffe10300028 4091 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0xfffe1030002c 4092 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0xfffe10300030 4093 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0xfffe10300034 4094 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0xfffe1030003c 4095 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0xfffe1030003d 4096 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT 0xfffe1030003e 4097 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY 0xfffe1030003f 4098 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0xfffe10300064 4099 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0xfffe10300066 4100 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0xfffe10300068 4101 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0xfffe1030006c 4102 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0xfffe1030006e 4103 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0xfffe10300070 4104 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0xfffe10300074 4105 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0xfffe10300076 4106 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0xfffe10300088 4107 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0xfffe1030008c 4108 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0xfffe1030008e 4109 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0xfffe10300090 4110 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0xfffe10300094 4111 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0xfffe10300096 4112 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0xfffe103000a0 4113 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0xfffe103000a2 4114 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0xfffe103000a4 4115 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0xfffe103000a8 4116 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0xfffe103000a8 4117 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA 0xfffe103000aa 4118 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0xfffe103000ac 4119 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0xfffe103000ac 4120 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64 0xfffe103000ae 4121 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0xfffe103000b0 4122 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0xfffe103000b0 4123 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0xfffe103000b4 4124 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0xfffe103000c0 4125 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0xfffe103000c2 4126 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0xfffe103000c4 4127 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0xfffe103000c8 4128 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10300100 4129 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10300104 4130 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0xfffe10300108 4131 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030010c 4132 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10300150 4133 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0xfffe10300154 4134 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0xfffe10300158 4135 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030015c 4136 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0xfffe10300160 4137 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0xfffe10300164 4138 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10300168 4139 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0xfffe1030016c 4140 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0xfffe10300170 4141 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0xfffe10300174 4142 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0xfffe10300178 4143 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0xfffe10300188 4144 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030018c 4145 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0xfffe10300190 4146 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0xfffe10300194 4147 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10300328 4148 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0xfffe1030032c 4149 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0xfffe1030032e 4150 4151 4152 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 4153 // base address: 0xfffe10301000 4154 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0xfffe10301000 4155 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0xfffe10301002 4156 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0xfffe10301004 4157 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0xfffe10301006 4158 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0xfffe10301008 4159 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0xfffe10301009 4160 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0xfffe1030100a 4161 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0xfffe1030100b 4162 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0xfffe1030100c 4163 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0xfffe1030100d 4164 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0xfffe1030100e 4165 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0xfffe1030100f 4166 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0xfffe10301010 4167 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0xfffe10301014 4168 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0xfffe10301018 4169 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0xfffe1030101c 4170 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0xfffe10301020 4171 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0xfffe10301024 4172 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR 0xfffe10301028 4173 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0xfffe1030102c 4174 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0xfffe10301030 4175 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0xfffe10301034 4176 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0xfffe1030103c 4177 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0xfffe1030103d 4178 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT 0xfffe1030103e 4179 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY 0xfffe1030103f 4180 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0xfffe10301064 4181 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0xfffe10301066 4182 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0xfffe10301068 4183 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0xfffe1030106c 4184 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0xfffe1030106e 4185 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0xfffe10301070 4186 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0xfffe10301074 4187 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0xfffe10301076 4188 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0xfffe10301088 4189 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0xfffe1030108c 4190 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0xfffe1030108e 4191 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0xfffe10301090 4192 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0xfffe10301094 4193 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0xfffe10301096 4194 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0xfffe103010a0 4195 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0xfffe103010a2 4196 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0xfffe103010a4 4197 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0xfffe103010a8 4198 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0xfffe103010a8 4199 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA 0xfffe103010aa 4200 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0xfffe103010ac 4201 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0xfffe103010ac 4202 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64 0xfffe103010ae 4203 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0xfffe103010b0 4204 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0xfffe103010b0 4205 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0xfffe103010b4 4206 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0xfffe103010c0 4207 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0xfffe103010c2 4208 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0xfffe103010c4 4209 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0xfffe103010c8 4210 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10301100 4211 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10301104 4212 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0xfffe10301108 4213 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030110c 4214 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10301150 4215 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0xfffe10301154 4216 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0xfffe10301158 4217 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030115c 4218 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0xfffe10301160 4219 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0xfffe10301164 4220 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10301168 4221 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0xfffe1030116c 4222 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0xfffe10301170 4223 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0xfffe10301174 4224 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0xfffe10301178 4225 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0xfffe10301188 4226 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030118c 4227 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0xfffe10301190 4228 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0xfffe10301194 4229 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10301328 4230 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0xfffe1030132c 4231 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0xfffe1030132e 4232 4233 4234 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 4235 // base address: 0xfffe10302000 4236 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0xfffe10302000 4237 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0xfffe10302002 4238 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0xfffe10302004 4239 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0xfffe10302006 4240 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0xfffe10302008 4241 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0xfffe10302009 4242 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0xfffe1030200a 4243 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0xfffe1030200b 4244 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0xfffe1030200c 4245 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0xfffe1030200d 4246 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0xfffe1030200e 4247 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0xfffe1030200f 4248 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0xfffe10302010 4249 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0xfffe10302014 4250 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0xfffe10302018 4251 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0xfffe1030201c 4252 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0xfffe10302020 4253 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0xfffe10302024 4254 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR 0xfffe10302028 4255 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0xfffe1030202c 4256 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0xfffe10302030 4257 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0xfffe10302034 4258 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0xfffe1030203c 4259 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0xfffe1030203d 4260 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT 0xfffe1030203e 4261 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY 0xfffe1030203f 4262 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0xfffe10302064 4263 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0xfffe10302066 4264 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0xfffe10302068 4265 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0xfffe1030206c 4266 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0xfffe1030206e 4267 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0xfffe10302070 4268 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0xfffe10302074 4269 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0xfffe10302076 4270 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0xfffe10302088 4271 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0xfffe1030208c 4272 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0xfffe1030208e 4273 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0xfffe10302090 4274 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0xfffe10302094 4275 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0xfffe10302096 4276 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0xfffe103020a0 4277 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0xfffe103020a2 4278 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0xfffe103020a4 4279 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0xfffe103020a8 4280 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0xfffe103020a8 4281 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA 0xfffe103020aa 4282 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0xfffe103020ac 4283 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0xfffe103020ac 4284 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64 0xfffe103020ae 4285 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0xfffe103020b0 4286 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0xfffe103020b0 4287 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0xfffe103020b4 4288 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0xfffe103020c0 4289 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0xfffe103020c2 4290 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0xfffe103020c4 4291 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0xfffe103020c8 4292 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10302100 4293 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10302104 4294 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0xfffe10302108 4295 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030210c 4296 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10302150 4297 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0xfffe10302154 4298 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0xfffe10302158 4299 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030215c 4300 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0xfffe10302160 4301 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0xfffe10302164 4302 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10302168 4303 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0xfffe1030216c 4304 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0xfffe10302170 4305 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0xfffe10302174 4306 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0xfffe10302178 4307 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0xfffe10302188 4308 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030218c 4309 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0xfffe10302190 4310 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0xfffe10302194 4311 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10302328 4312 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0xfffe1030232c 4313 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0xfffe1030232e 4314 4315 4316 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 4317 // base address: 0xfffe10303000 4318 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0xfffe10303000 4319 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0xfffe10303002 4320 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0xfffe10303004 4321 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0xfffe10303006 4322 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0xfffe10303008 4323 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0xfffe10303009 4324 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0xfffe1030300a 4325 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0xfffe1030300b 4326 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0xfffe1030300c 4327 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0xfffe1030300d 4328 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0xfffe1030300e 4329 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0xfffe1030300f 4330 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0xfffe10303010 4331 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0xfffe10303014 4332 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0xfffe10303018 4333 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0xfffe1030301c 4334 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0xfffe10303020 4335 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0xfffe10303024 4336 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR 0xfffe10303028 4337 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0xfffe1030302c 4338 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0xfffe10303030 4339 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0xfffe10303034 4340 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0xfffe1030303c 4341 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0xfffe1030303d 4342 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT 0xfffe1030303e 4343 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY 0xfffe1030303f 4344 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0xfffe10303064 4345 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0xfffe10303066 4346 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0xfffe10303068 4347 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0xfffe1030306c 4348 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0xfffe1030306e 4349 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0xfffe10303070 4350 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0xfffe10303074 4351 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0xfffe10303076 4352 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0xfffe10303088 4353 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0xfffe1030308c 4354 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0xfffe1030308e 4355 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0xfffe10303090 4356 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0xfffe10303094 4357 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0xfffe10303096 4358 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0xfffe103030a0 4359 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0xfffe103030a2 4360 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0xfffe103030a4 4361 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0xfffe103030a8 4362 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0xfffe103030a8 4363 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA 0xfffe103030aa 4364 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0xfffe103030ac 4365 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0xfffe103030ac 4366 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64 0xfffe103030ae 4367 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0xfffe103030b0 4368 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0xfffe103030b0 4369 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0xfffe103030b4 4370 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0xfffe103030c0 4371 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0xfffe103030c2 4372 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0xfffe103030c4 4373 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0xfffe103030c8 4374 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10303100 4375 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10303104 4376 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0xfffe10303108 4377 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030310c 4378 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10303150 4379 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0xfffe10303154 4380 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0xfffe10303158 4381 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030315c 4382 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0xfffe10303160 4383 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0xfffe10303164 4384 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10303168 4385 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0xfffe1030316c 4386 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0xfffe10303170 4387 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0xfffe10303174 4388 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0xfffe10303178 4389 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0xfffe10303188 4390 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030318c 4391 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0xfffe10303190 4392 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0xfffe10303194 4393 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10303328 4394 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0xfffe1030332c 4395 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0xfffe1030332e 4396 4397 4398 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 4399 // base address: 0xfffe10304000 4400 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0xfffe10304000 4401 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0xfffe10304002 4402 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0xfffe10304004 4403 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0xfffe10304006 4404 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0xfffe10304008 4405 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0xfffe10304009 4406 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0xfffe1030400a 4407 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0xfffe1030400b 4408 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0xfffe1030400c 4409 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0xfffe1030400d 4410 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0xfffe1030400e 4411 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0xfffe1030400f 4412 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0xfffe10304010 4413 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0xfffe10304014 4414 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0xfffe10304018 4415 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0xfffe1030401c 4416 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0xfffe10304020 4417 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0xfffe10304024 4418 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR 0xfffe10304028 4419 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0xfffe1030402c 4420 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0xfffe10304030 4421 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0xfffe10304034 4422 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0xfffe1030403c 4423 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0xfffe1030403d 4424 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT 0xfffe1030403e 4425 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY 0xfffe1030403f 4426 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0xfffe10304064 4427 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0xfffe10304066 4428 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0xfffe10304068 4429 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0xfffe1030406c 4430 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0xfffe1030406e 4431 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0xfffe10304070 4432 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0xfffe10304074 4433 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0xfffe10304076 4434 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0xfffe10304088 4435 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0xfffe1030408c 4436 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0xfffe1030408e 4437 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0xfffe10304090 4438 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0xfffe10304094 4439 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0xfffe10304096 4440 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0xfffe103040a0 4441 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0xfffe103040a2 4442 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0xfffe103040a4 4443 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0xfffe103040a8 4444 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0xfffe103040a8 4445 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA 0xfffe103040aa 4446 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0xfffe103040ac 4447 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0xfffe103040ac 4448 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64 0xfffe103040ae 4449 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0xfffe103040b0 4450 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0xfffe103040b0 4451 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0xfffe103040b4 4452 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0xfffe103040c0 4453 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0xfffe103040c2 4454 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0xfffe103040c4 4455 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0xfffe103040c8 4456 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10304100 4457 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10304104 4458 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0xfffe10304108 4459 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030410c 4460 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10304150 4461 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0xfffe10304154 4462 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0xfffe10304158 4463 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030415c 4464 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0xfffe10304160 4465 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0xfffe10304164 4466 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10304168 4467 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0xfffe1030416c 4468 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0xfffe10304170 4469 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0xfffe10304174 4470 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0xfffe10304178 4471 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0xfffe10304188 4472 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030418c 4473 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0xfffe10304190 4474 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0xfffe10304194 4475 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10304328 4476 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0xfffe1030432c 4477 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0xfffe1030432e 4478 4479 4480 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 4481 // base address: 0xfffe10305000 4482 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0xfffe10305000 4483 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0xfffe10305002 4484 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0xfffe10305004 4485 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0xfffe10305006 4486 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0xfffe10305008 4487 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0xfffe10305009 4488 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0xfffe1030500a 4489 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0xfffe1030500b 4490 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0xfffe1030500c 4491 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0xfffe1030500d 4492 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0xfffe1030500e 4493 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0xfffe1030500f 4494 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0xfffe10305010 4495 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0xfffe10305014 4496 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0xfffe10305018 4497 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0xfffe1030501c 4498 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0xfffe10305020 4499 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0xfffe10305024 4500 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR 0xfffe10305028 4501 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0xfffe1030502c 4502 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0xfffe10305030 4503 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0xfffe10305034 4504 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0xfffe1030503c 4505 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0xfffe1030503d 4506 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT 0xfffe1030503e 4507 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY 0xfffe1030503f 4508 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0xfffe10305064 4509 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0xfffe10305066 4510 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0xfffe10305068 4511 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0xfffe1030506c 4512 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0xfffe1030506e 4513 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0xfffe10305070 4514 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0xfffe10305074 4515 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0xfffe10305076 4516 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0xfffe10305088 4517 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0xfffe1030508c 4518 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0xfffe1030508e 4519 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0xfffe10305090 4520 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0xfffe10305094 4521 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0xfffe10305096 4522 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0xfffe103050a0 4523 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0xfffe103050a2 4524 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0xfffe103050a4 4525 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0xfffe103050a8 4526 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0xfffe103050a8 4527 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA 0xfffe103050aa 4528 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0xfffe103050ac 4529 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0xfffe103050ac 4530 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64 0xfffe103050ae 4531 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0xfffe103050b0 4532 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0xfffe103050b0 4533 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0xfffe103050b4 4534 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0xfffe103050c0 4535 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0xfffe103050c2 4536 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0xfffe103050c4 4537 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0xfffe103050c8 4538 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10305100 4539 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10305104 4540 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0xfffe10305108 4541 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030510c 4542 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10305150 4543 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0xfffe10305154 4544 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0xfffe10305158 4545 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030515c 4546 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0xfffe10305160 4547 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0xfffe10305164 4548 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10305168 4549 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0xfffe1030516c 4550 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0xfffe10305170 4551 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0xfffe10305174 4552 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0xfffe10305178 4553 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0xfffe10305188 4554 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030518c 4555 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0xfffe10305190 4556 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0xfffe10305194 4557 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10305328 4558 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0xfffe1030532c 4559 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0xfffe1030532e 4560 4561 4562 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 4563 // base address: 0xfffe10306000 4564 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0xfffe10306000 4565 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0xfffe10306002 4566 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0xfffe10306004 4567 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0xfffe10306006 4568 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0xfffe10306008 4569 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0xfffe10306009 4570 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0xfffe1030600a 4571 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0xfffe1030600b 4572 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0xfffe1030600c 4573 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0xfffe1030600d 4574 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0xfffe1030600e 4575 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0xfffe1030600f 4576 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0xfffe10306010 4577 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0xfffe10306014 4578 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0xfffe10306018 4579 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0xfffe1030601c 4580 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0xfffe10306020 4581 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0xfffe10306024 4582 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR 0xfffe10306028 4583 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0xfffe1030602c 4584 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0xfffe10306030 4585 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0xfffe10306034 4586 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0xfffe1030603c 4587 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0xfffe1030603d 4588 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT 0xfffe1030603e 4589 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY 0xfffe1030603f 4590 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0xfffe10306064 4591 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0xfffe10306066 4592 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0xfffe10306068 4593 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0xfffe1030606c 4594 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0xfffe1030606e 4595 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0xfffe10306070 4596 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0xfffe10306074 4597 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0xfffe10306076 4598 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0xfffe10306088 4599 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0xfffe1030608c 4600 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0xfffe1030608e 4601 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0xfffe10306090 4602 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0xfffe10306094 4603 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0xfffe10306096 4604 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0xfffe103060a0 4605 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0xfffe103060a2 4606 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0xfffe103060a4 4607 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0xfffe103060a8 4608 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0xfffe103060a8 4609 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA 0xfffe103060aa 4610 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0xfffe103060ac 4611 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0xfffe103060ac 4612 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64 0xfffe103060ae 4613 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0xfffe103060b0 4614 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0xfffe103060b0 4615 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0xfffe103060b4 4616 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0xfffe103060c0 4617 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0xfffe103060c2 4618 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0xfffe103060c4 4619 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0xfffe103060c8 4620 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10306100 4621 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10306104 4622 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0xfffe10306108 4623 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030610c 4624 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10306150 4625 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0xfffe10306154 4626 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0xfffe10306158 4627 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030615c 4628 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0xfffe10306160 4629 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0xfffe10306164 4630 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10306168 4631 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0xfffe1030616c 4632 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0xfffe10306170 4633 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0xfffe10306174 4634 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0xfffe10306178 4635 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0xfffe10306188 4636 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030618c 4637 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0xfffe10306190 4638 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0xfffe10306194 4639 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10306328 4640 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0xfffe1030632c 4641 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0xfffe1030632e 4642 4643 4644 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 4645 // base address: 0xfffe10307000 4646 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0xfffe10307000 4647 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0xfffe10307002 4648 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0xfffe10307004 4649 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0xfffe10307006 4650 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0xfffe10307008 4651 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0xfffe10307009 4652 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0xfffe1030700a 4653 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0xfffe1030700b 4654 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0xfffe1030700c 4655 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0xfffe1030700d 4656 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0xfffe1030700e 4657 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0xfffe1030700f 4658 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0xfffe10307010 4659 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0xfffe10307014 4660 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0xfffe10307018 4661 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0xfffe1030701c 4662 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0xfffe10307020 4663 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0xfffe10307024 4664 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR 0xfffe10307028 4665 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0xfffe1030702c 4666 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0xfffe10307030 4667 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0xfffe10307034 4668 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0xfffe1030703c 4669 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0xfffe1030703d 4670 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT 0xfffe1030703e 4671 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY 0xfffe1030703f 4672 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0xfffe10307064 4673 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0xfffe10307066 4674 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0xfffe10307068 4675 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0xfffe1030706c 4676 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0xfffe1030706e 4677 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0xfffe10307070 4678 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0xfffe10307074 4679 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0xfffe10307076 4680 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0xfffe10307088 4681 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0xfffe1030708c 4682 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0xfffe1030708e 4683 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0xfffe10307090 4684 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0xfffe10307094 4685 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0xfffe10307096 4686 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0xfffe103070a0 4687 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0xfffe103070a2 4688 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0xfffe103070a4 4689 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0xfffe103070a8 4690 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0xfffe103070a8 4691 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA 0xfffe103070aa 4692 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0xfffe103070ac 4693 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0xfffe103070ac 4694 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64 0xfffe103070ae 4695 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0xfffe103070b0 4696 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0xfffe103070b0 4697 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0xfffe103070b4 4698 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0xfffe103070c0 4699 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0xfffe103070c2 4700 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0xfffe103070c4 4701 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0xfffe103070c8 4702 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10307100 4703 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10307104 4704 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0xfffe10307108 4705 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030710c 4706 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10307150 4707 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0xfffe10307154 4708 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0xfffe10307158 4709 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030715c 4710 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0xfffe10307160 4711 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0xfffe10307164 4712 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10307168 4713 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0xfffe1030716c 4714 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0xfffe10307170 4715 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0xfffe10307174 4716 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0xfffe10307178 4717 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0xfffe10307188 4718 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030718c 4719 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0xfffe10307190 4720 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0xfffe10307194 4721 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10307328 4722 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0xfffe1030732c 4723 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0xfffe1030732e 4724 4725 4726 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 4727 // base address: 0xfffe10308000 4728 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0xfffe10308000 4729 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0xfffe10308002 4730 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0xfffe10308004 4731 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0xfffe10308006 4732 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0xfffe10308008 4733 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0xfffe10308009 4734 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0xfffe1030800a 4735 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0xfffe1030800b 4736 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0xfffe1030800c 4737 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0xfffe1030800d 4738 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0xfffe1030800e 4739 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0xfffe1030800f 4740 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0xfffe10308010 4741 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0xfffe10308014 4742 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0xfffe10308018 4743 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0xfffe1030801c 4744 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0xfffe10308020 4745 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0xfffe10308024 4746 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR 0xfffe10308028 4747 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0xfffe1030802c 4748 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0xfffe10308030 4749 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0xfffe10308034 4750 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0xfffe1030803c 4751 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0xfffe1030803d 4752 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT 0xfffe1030803e 4753 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY 0xfffe1030803f 4754 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0xfffe10308064 4755 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0xfffe10308066 4756 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0xfffe10308068 4757 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0xfffe1030806c 4758 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0xfffe1030806e 4759 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0xfffe10308070 4760 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0xfffe10308074 4761 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0xfffe10308076 4762 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0xfffe10308088 4763 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0xfffe1030808c 4764 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0xfffe1030808e 4765 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0xfffe10308090 4766 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0xfffe10308094 4767 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0xfffe10308096 4768 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0xfffe103080a0 4769 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0xfffe103080a2 4770 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0xfffe103080a4 4771 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0xfffe103080a8 4772 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0xfffe103080a8 4773 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA 0xfffe103080aa 4774 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0xfffe103080ac 4775 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0xfffe103080ac 4776 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64 0xfffe103080ae 4777 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0xfffe103080b0 4778 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0xfffe103080b0 4779 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0xfffe103080b4 4780 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0xfffe103080c0 4781 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0xfffe103080c2 4782 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0xfffe103080c4 4783 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0xfffe103080c8 4784 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10308100 4785 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10308104 4786 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0xfffe10308108 4787 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030810c 4788 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10308150 4789 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0xfffe10308154 4790 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0xfffe10308158 4791 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030815c 4792 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0xfffe10308160 4793 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0xfffe10308164 4794 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10308168 4795 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0xfffe1030816c 4796 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0xfffe10308170 4797 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0xfffe10308174 4798 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0xfffe10308178 4799 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0xfffe10308188 4800 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030818c 4801 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0xfffe10308190 4802 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0xfffe10308194 4803 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10308328 4804 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0xfffe1030832c 4805 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0xfffe1030832e 4806 4807 4808 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 4809 // base address: 0xfffe10309000 4810 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0xfffe10309000 4811 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0xfffe10309002 4812 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0xfffe10309004 4813 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0xfffe10309006 4814 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0xfffe10309008 4815 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0xfffe10309009 4816 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0xfffe1030900a 4817 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0xfffe1030900b 4818 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0xfffe1030900c 4819 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0xfffe1030900d 4820 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0xfffe1030900e 4821 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0xfffe1030900f 4822 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0xfffe10309010 4823 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0xfffe10309014 4824 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0xfffe10309018 4825 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0xfffe1030901c 4826 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0xfffe10309020 4827 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0xfffe10309024 4828 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR 0xfffe10309028 4829 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0xfffe1030902c 4830 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0xfffe10309030 4831 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0xfffe10309034 4832 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0xfffe1030903c 4833 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0xfffe1030903d 4834 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT 0xfffe1030903e 4835 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY 0xfffe1030903f 4836 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0xfffe10309064 4837 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0xfffe10309066 4838 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0xfffe10309068 4839 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0xfffe1030906c 4840 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0xfffe1030906e 4841 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0xfffe10309070 4842 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0xfffe10309074 4843 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0xfffe10309076 4844 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0xfffe10309088 4845 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0xfffe1030908c 4846 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0xfffe1030908e 4847 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0xfffe10309090 4848 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0xfffe10309094 4849 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0xfffe10309096 4850 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0xfffe103090a0 4851 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0xfffe103090a2 4852 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0xfffe103090a4 4853 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0xfffe103090a8 4854 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0xfffe103090a8 4855 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA 0xfffe103090aa 4856 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0xfffe103090ac 4857 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0xfffe103090ac 4858 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64 0xfffe103090ae 4859 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0xfffe103090b0 4860 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0xfffe103090b0 4861 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0xfffe103090b4 4862 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0xfffe103090c0 4863 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0xfffe103090c2 4864 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0xfffe103090c4 4865 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0xfffe103090c8 4866 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10309100 4867 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10309104 4868 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0xfffe10309108 4869 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030910c 4870 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10309150 4871 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0xfffe10309154 4872 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0xfffe10309158 4873 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030915c 4874 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0xfffe10309160 4875 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0xfffe10309164 4876 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10309168 4877 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0xfffe1030916c 4878 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0xfffe10309170 4879 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0xfffe10309174 4880 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0xfffe10309178 4881 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0xfffe10309188 4882 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030918c 4883 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0xfffe10309190 4884 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0xfffe10309194 4885 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10309328 4886 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0xfffe1030932c 4887 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0xfffe1030932e 4888 4889 4890 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 4891 // base address: 0xfffe1030a000 4892 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0xfffe1030a000 4893 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0xfffe1030a002 4894 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0xfffe1030a004 4895 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0xfffe1030a006 4896 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0xfffe1030a008 4897 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0xfffe1030a009 4898 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0xfffe1030a00a 4899 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0xfffe1030a00b 4900 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0xfffe1030a00c 4901 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0xfffe1030a00d 4902 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0xfffe1030a00e 4903 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0xfffe1030a00f 4904 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0xfffe1030a010 4905 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0xfffe1030a014 4906 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0xfffe1030a018 4907 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0xfffe1030a01c 4908 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0xfffe1030a020 4909 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0xfffe1030a024 4910 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR 0xfffe1030a028 4911 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0xfffe1030a02c 4912 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0xfffe1030a030 4913 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0xfffe1030a034 4914 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0xfffe1030a03c 4915 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0xfffe1030a03d 4916 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT 0xfffe1030a03e 4917 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY 0xfffe1030a03f 4918 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0xfffe1030a064 4919 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0xfffe1030a066 4920 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0xfffe1030a068 4921 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0xfffe1030a06c 4922 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0xfffe1030a06e 4923 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0xfffe1030a070 4924 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0xfffe1030a074 4925 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0xfffe1030a076 4926 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0xfffe1030a088 4927 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0xfffe1030a08c 4928 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0xfffe1030a08e 4929 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0xfffe1030a090 4930 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0xfffe1030a094 4931 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0xfffe1030a096 4932 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0xfffe1030a0a0 4933 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0xfffe1030a0a2 4934 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0xfffe1030a0a4 4935 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0xfffe1030a0a8 4936 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0xfffe1030a0a8 4937 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA 0xfffe1030a0aa 4938 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0xfffe1030a0ac 4939 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0xfffe1030a0ac 4940 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64 0xfffe1030a0ae 4941 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0xfffe1030a0b0 4942 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0xfffe1030a0b0 4943 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0xfffe1030a0b4 4944 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0xfffe1030a0c0 4945 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0xfffe1030a0c2 4946 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0xfffe1030a0c4 4947 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0xfffe1030a0c8 4948 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030a100 4949 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030a104 4950 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030a108 4951 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030a10c 4952 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030a150 4953 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030a154 4954 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0xfffe1030a158 4955 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030a15c 4956 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0xfffe1030a160 4957 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0xfffe1030a164 4958 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030a168 4959 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0xfffe1030a16c 4960 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0xfffe1030a170 4961 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0xfffe1030a174 4962 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0xfffe1030a178 4963 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030a188 4964 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030a18c 4965 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030a190 4966 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030a194 4967 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030a328 4968 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0xfffe1030a32c 4969 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0xfffe1030a32e 4970 4971 4972 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 4973 // base address: 0xfffe1030b000 4974 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0xfffe1030b000 4975 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0xfffe1030b002 4976 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0xfffe1030b004 4977 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0xfffe1030b006 4978 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0xfffe1030b008 4979 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0xfffe1030b009 4980 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0xfffe1030b00a 4981 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0xfffe1030b00b 4982 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0xfffe1030b00c 4983 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0xfffe1030b00d 4984 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0xfffe1030b00e 4985 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0xfffe1030b00f 4986 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0xfffe1030b010 4987 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0xfffe1030b014 4988 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0xfffe1030b018 4989 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0xfffe1030b01c 4990 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0xfffe1030b020 4991 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0xfffe1030b024 4992 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR 0xfffe1030b028 4993 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0xfffe1030b02c 4994 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0xfffe1030b030 4995 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0xfffe1030b034 4996 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0xfffe1030b03c 4997 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0xfffe1030b03d 4998 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT 0xfffe1030b03e 4999 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY 0xfffe1030b03f 5000 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0xfffe1030b064 5001 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0xfffe1030b066 5002 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0xfffe1030b068 5003 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0xfffe1030b06c 5004 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0xfffe1030b06e 5005 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0xfffe1030b070 5006 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0xfffe1030b074 5007 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0xfffe1030b076 5008 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0xfffe1030b088 5009 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0xfffe1030b08c 5010 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0xfffe1030b08e 5011 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0xfffe1030b090 5012 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0xfffe1030b094 5013 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0xfffe1030b096 5014 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0xfffe1030b0a0 5015 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0xfffe1030b0a2 5016 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0xfffe1030b0a4 5017 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0xfffe1030b0a8 5018 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0xfffe1030b0a8 5019 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA 0xfffe1030b0aa 5020 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0xfffe1030b0ac 5021 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0xfffe1030b0ac 5022 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64 0xfffe1030b0ae 5023 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0xfffe1030b0b0 5024 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0xfffe1030b0b0 5025 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0xfffe1030b0b4 5026 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0xfffe1030b0c0 5027 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0xfffe1030b0c2 5028 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0xfffe1030b0c4 5029 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0xfffe1030b0c8 5030 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030b100 5031 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030b104 5032 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030b108 5033 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030b10c 5034 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030b150 5035 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030b154 5036 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0xfffe1030b158 5037 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030b15c 5038 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0xfffe1030b160 5039 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0xfffe1030b164 5040 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030b168 5041 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0xfffe1030b16c 5042 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0xfffe1030b170 5043 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0xfffe1030b174 5044 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0xfffe1030b178 5045 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030b188 5046 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030b18c 5047 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030b190 5048 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030b194 5049 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030b328 5050 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0xfffe1030b32c 5051 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0xfffe1030b32e 5052 5053 5054 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 5055 // base address: 0xfffe1030c000 5056 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0xfffe1030c000 5057 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0xfffe1030c002 5058 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0xfffe1030c004 5059 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0xfffe1030c006 5060 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0xfffe1030c008 5061 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0xfffe1030c009 5062 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0xfffe1030c00a 5063 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0xfffe1030c00b 5064 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0xfffe1030c00c 5065 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0xfffe1030c00d 5066 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0xfffe1030c00e 5067 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0xfffe1030c00f 5068 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0xfffe1030c010 5069 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0xfffe1030c014 5070 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0xfffe1030c018 5071 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0xfffe1030c01c 5072 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0xfffe1030c020 5073 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0xfffe1030c024 5074 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR 0xfffe1030c028 5075 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0xfffe1030c02c 5076 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0xfffe1030c030 5077 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0xfffe1030c034 5078 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0xfffe1030c03c 5079 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0xfffe1030c03d 5080 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT 0xfffe1030c03e 5081 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY 0xfffe1030c03f 5082 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0xfffe1030c064 5083 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0xfffe1030c066 5084 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0xfffe1030c068 5085 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0xfffe1030c06c 5086 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0xfffe1030c06e 5087 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0xfffe1030c070 5088 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0xfffe1030c074 5089 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0xfffe1030c076 5090 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0xfffe1030c088 5091 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0xfffe1030c08c 5092 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0xfffe1030c08e 5093 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0xfffe1030c090 5094 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0xfffe1030c094 5095 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0xfffe1030c096 5096 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0xfffe1030c0a0 5097 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0xfffe1030c0a2 5098 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0xfffe1030c0a4 5099 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0xfffe1030c0a8 5100 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0xfffe1030c0a8 5101 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA 0xfffe1030c0aa 5102 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0xfffe1030c0ac 5103 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0xfffe1030c0ac 5104 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64 0xfffe1030c0ae 5105 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0xfffe1030c0b0 5106 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0xfffe1030c0b0 5107 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0xfffe1030c0b4 5108 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0xfffe1030c0c0 5109 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0xfffe1030c0c2 5110 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0xfffe1030c0c4 5111 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0xfffe1030c0c8 5112 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030c100 5113 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030c104 5114 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030c108 5115 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030c10c 5116 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030c150 5117 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030c154 5118 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0xfffe1030c158 5119 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030c15c 5120 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0xfffe1030c160 5121 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0xfffe1030c164 5122 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030c168 5123 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0xfffe1030c16c 5124 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0xfffe1030c170 5125 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0xfffe1030c174 5126 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0xfffe1030c178 5127 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030c188 5128 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030c18c 5129 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030c190 5130 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030c194 5131 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030c328 5132 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0xfffe1030c32c 5133 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0xfffe1030c32e 5134 5135 5136 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 5137 // base address: 0xfffe1030d000 5138 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0xfffe1030d000 5139 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0xfffe1030d002 5140 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0xfffe1030d004 5141 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0xfffe1030d006 5142 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0xfffe1030d008 5143 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0xfffe1030d009 5144 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0xfffe1030d00a 5145 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0xfffe1030d00b 5146 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0xfffe1030d00c 5147 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0xfffe1030d00d 5148 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0xfffe1030d00e 5149 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0xfffe1030d00f 5150 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0xfffe1030d010 5151 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0xfffe1030d014 5152 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0xfffe1030d018 5153 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0xfffe1030d01c 5154 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0xfffe1030d020 5155 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0xfffe1030d024 5156 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR 0xfffe1030d028 5157 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0xfffe1030d02c 5158 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0xfffe1030d030 5159 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0xfffe1030d034 5160 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0xfffe1030d03c 5161 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0xfffe1030d03d 5162 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT 0xfffe1030d03e 5163 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY 0xfffe1030d03f 5164 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0xfffe1030d064 5165 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0xfffe1030d066 5166 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0xfffe1030d068 5167 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0xfffe1030d06c 5168 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0xfffe1030d06e 5169 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0xfffe1030d070 5170 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0xfffe1030d074 5171 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0xfffe1030d076 5172 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0xfffe1030d088 5173 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0xfffe1030d08c 5174 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0xfffe1030d08e 5175 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0xfffe1030d090 5176 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0xfffe1030d094 5177 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0xfffe1030d096 5178 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0xfffe1030d0a0 5179 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0xfffe1030d0a2 5180 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0xfffe1030d0a4 5181 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0xfffe1030d0a8 5182 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0xfffe1030d0a8 5183 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA 0xfffe1030d0aa 5184 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0xfffe1030d0ac 5185 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0xfffe1030d0ac 5186 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64 0xfffe1030d0ae 5187 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0xfffe1030d0b0 5188 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0xfffe1030d0b0 5189 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0xfffe1030d0b4 5190 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0xfffe1030d0c0 5191 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0xfffe1030d0c2 5192 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0xfffe1030d0c4 5193 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0xfffe1030d0c8 5194 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030d100 5195 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030d104 5196 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030d108 5197 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030d10c 5198 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030d150 5199 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030d154 5200 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0xfffe1030d158 5201 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030d15c 5202 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0xfffe1030d160 5203 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0xfffe1030d164 5204 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030d168 5205 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0xfffe1030d16c 5206 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0xfffe1030d170 5207 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0xfffe1030d174 5208 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0xfffe1030d178 5209 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030d188 5210 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030d18c 5211 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030d190 5212 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030d194 5213 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030d328 5214 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0xfffe1030d32c 5215 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0xfffe1030d32e 5216 5217 5218 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 5219 // base address: 0xfffe1030e000 5220 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0xfffe1030e000 5221 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0xfffe1030e002 5222 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0xfffe1030e004 5223 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0xfffe1030e006 5224 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0xfffe1030e008 5225 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0xfffe1030e009 5226 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0xfffe1030e00a 5227 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0xfffe1030e00b 5228 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0xfffe1030e00c 5229 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0xfffe1030e00d 5230 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0xfffe1030e00e 5231 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0xfffe1030e00f 5232 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0xfffe1030e010 5233 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0xfffe1030e014 5234 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0xfffe1030e018 5235 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0xfffe1030e01c 5236 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0xfffe1030e020 5237 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0xfffe1030e024 5238 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR 0xfffe1030e028 5239 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0xfffe1030e02c 5240 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0xfffe1030e030 5241 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0xfffe1030e034 5242 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0xfffe1030e03c 5243 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0xfffe1030e03d 5244 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT 0xfffe1030e03e 5245 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY 0xfffe1030e03f 5246 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0xfffe1030e064 5247 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0xfffe1030e066 5248 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0xfffe1030e068 5249 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0xfffe1030e06c 5250 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0xfffe1030e06e 5251 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0xfffe1030e070 5252 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0xfffe1030e074 5253 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0xfffe1030e076 5254 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0xfffe1030e088 5255 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0xfffe1030e08c 5256 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0xfffe1030e08e 5257 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0xfffe1030e090 5258 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0xfffe1030e094 5259 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0xfffe1030e096 5260 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0xfffe1030e0a0 5261 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0xfffe1030e0a2 5262 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0xfffe1030e0a4 5263 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0xfffe1030e0a8 5264 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0xfffe1030e0a8 5265 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA 0xfffe1030e0aa 5266 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0xfffe1030e0ac 5267 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0xfffe1030e0ac 5268 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64 0xfffe1030e0ae 5269 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0xfffe1030e0b0 5270 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0xfffe1030e0b0 5271 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0xfffe1030e0b4 5272 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0xfffe1030e0c0 5273 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0xfffe1030e0c2 5274 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0xfffe1030e0c4 5275 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0xfffe1030e0c8 5276 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030e100 5277 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030e104 5278 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030e108 5279 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030e10c 5280 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030e150 5281 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030e154 5282 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0xfffe1030e158 5283 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030e15c 5284 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0xfffe1030e160 5285 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0xfffe1030e164 5286 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030e168 5287 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0xfffe1030e16c 5288 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0xfffe1030e170 5289 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0xfffe1030e174 5290 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0xfffe1030e178 5291 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030e188 5292 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030e18c 5293 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030e190 5294 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030e194 5295 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030e328 5296 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0xfffe1030e32c 5297 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0xfffe1030e32e 5298 5299 5300 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 5301 // base address: 0xfffe1030f000 5302 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0xfffe1030f000 5303 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0xfffe1030f002 5304 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0xfffe1030f004 5305 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0xfffe1030f006 5306 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0xfffe1030f008 5307 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0xfffe1030f009 5308 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0xfffe1030f00a 5309 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0xfffe1030f00b 5310 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0xfffe1030f00c 5311 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0xfffe1030f00d 5312 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0xfffe1030f00e 5313 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0xfffe1030f00f 5314 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0xfffe1030f010 5315 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0xfffe1030f014 5316 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0xfffe1030f018 5317 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0xfffe1030f01c 5318 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0xfffe1030f020 5319 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0xfffe1030f024 5320 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR 0xfffe1030f028 5321 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0xfffe1030f02c 5322 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0xfffe1030f030 5323 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0xfffe1030f034 5324 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0xfffe1030f03c 5325 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0xfffe1030f03d 5326 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT 0xfffe1030f03e 5327 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY 0xfffe1030f03f 5328 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0xfffe1030f064 5329 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0xfffe1030f066 5330 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0xfffe1030f068 5331 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0xfffe1030f06c 5332 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0xfffe1030f06e 5333 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0xfffe1030f070 5334 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0xfffe1030f074 5335 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0xfffe1030f076 5336 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0xfffe1030f088 5337 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0xfffe1030f08c 5338 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0xfffe1030f08e 5339 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0xfffe1030f090 5340 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0xfffe1030f094 5341 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0xfffe1030f096 5342 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0xfffe1030f0a0 5343 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0xfffe1030f0a2 5344 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0xfffe1030f0a4 5345 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0xfffe1030f0a8 5346 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0xfffe1030f0a8 5347 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA 0xfffe1030f0aa 5348 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0xfffe1030f0ac 5349 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0xfffe1030f0ac 5350 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64 0xfffe1030f0ae 5351 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0xfffe1030f0b0 5352 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0xfffe1030f0b0 5353 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0xfffe1030f0b4 5354 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0xfffe1030f0c0 5355 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0xfffe1030f0c2 5356 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0xfffe1030f0c4 5357 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0xfffe1030f0c8 5358 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030f100 5359 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030f104 5360 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030f108 5361 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030f10c 5362 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030f150 5363 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030f154 5364 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0xfffe1030f158 5365 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030f15c 5366 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0xfffe1030f160 5367 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0xfffe1030f164 5368 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030f168 5369 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0xfffe1030f16c 5370 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0xfffe1030f170 5371 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0xfffe1030f174 5372 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0xfffe1030f178 5373 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030f188 5374 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030f18c 5375 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030f190 5376 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030f194 5377 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030f328 5378 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0xfffe1030f32c 5379 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0xfffe1030f32e 5380 5381 5382 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 5383 // base address: 0xd0000000 5384 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0xd000382c 5385 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0xd0003830 5386 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd000384c 5387 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0003850 5388 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0003854 5389 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0003858 5390 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd000385c 5391 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0003864 5392 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0003868 5393 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0xd0003898 5394 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0xd000389c 5395 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0xd00038a0 5396 #define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0xd00038c8 5397 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0xd0003958 5398 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0xd000395c 5399 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0xd0003960 5400 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0xd0003964 5401 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0xd0003968 5402 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0xd000396c 5403 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0xd0003970 5404 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0xd0003974 5405 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0xd0003978 5406 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0xd000397c 5407 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0xd0003980 5408 5409 5410 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 5411 // base address: 0xd0000000 5412 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0xd0000000 5413 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA 0xd0000004 5414 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0xd0000018 5415 5416 5417 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 5418 // base address: 0xd0000000 5419 #define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0xd0003694 5420 #define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0xd0003780 5421 #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0xd000378c 5422 #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0xd0003790 5423 #define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0xd0003794 5424 5425 5426 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 5427 // base address: 0xd0000000 5428 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0xd0042000 5429 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0xd0042004 5430 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0xd0042008 5431 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0xd004200c 5432 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0xd0042010 5433 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0xd0042014 5434 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0xd0042018 5435 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0xd004201c 5436 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0xd0042020 5437 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0xd0042024 5438 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0xd0042028 5439 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0xd004202c 5440 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0xd0042030 5441 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0xd0042034 5442 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0xd0042038 5443 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0xd004203c 5444 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0xd0043000 5445 5446 5447 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 5448 // base address: 0xd0080000 5449 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0xd008382c 5450 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0xd0083830 5451 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd008384c 5452 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0083850 5453 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0083854 5454 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0083858 5455 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd008385c 5456 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0083864 5457 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0083868 5458 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0xd0083898 5459 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0xd008389c 5460 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0xd00838a0 5461 #define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0xd00838c8 5462 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0xd0083958 5463 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0xd008395c 5464 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0xd0083960 5465 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0xd0083964 5466 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0xd0083968 5467 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0xd008396c 5468 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0xd0083970 5469 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0xd0083974 5470 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0xd0083978 5471 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0xd008397c 5472 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0xd0083980 5473 5474 5475 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 5476 // base address: 0xd0080000 5477 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0xd0080000 5478 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA 0xd0080004 5479 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0xd0080018 5480 5481 5482 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 5483 // base address: 0xd0080000 5484 #define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0xd0083694 5485 #define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0xd0083780 5486 #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0xd008378c 5487 #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0xd0083790 5488 #define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0xd0083794 5489 5490 5491 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 5492 // base address: 0xd0080000 5493 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0xd00c2000 5494 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0xd00c2004 5495 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0xd00c2008 5496 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0xd00c200c 5497 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0xd00c2010 5498 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0xd00c2014 5499 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0xd00c2018 5500 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0xd00c201c 5501 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0xd00c2020 5502 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0xd00c2024 5503 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0xd00c2028 5504 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0xd00c202c 5505 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0xd00c2030 5506 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0xd00c2034 5507 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0xd00c2038 5508 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0xd00c203c 5509 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0xd00c3000 5510 5511 5512 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 5513 // base address: 0xd0100000 5514 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0xd010382c 5515 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0xd0103830 5516 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd010384c 5517 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0103850 5518 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0103854 5519 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0103858 5520 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd010385c 5521 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0103864 5522 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0103868 5523 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0xd0103898 5524 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0xd010389c 5525 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0xd01038a0 5526 #define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0xd01038c8 5527 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0xd0103958 5528 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0xd010395c 5529 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0xd0103960 5530 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0xd0103964 5531 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0xd0103968 5532 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0xd010396c 5533 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0xd0103970 5534 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0xd0103974 5535 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0xd0103978 5536 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0xd010397c 5537 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0xd0103980 5538 5539 5540 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 5541 // base address: 0xd0100000 5542 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0xd0100000 5543 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA 0xd0100004 5544 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0xd0100018 5545 5546 5547 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 5548 // base address: 0xd0100000 5549 #define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0xd0103694 5550 #define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0xd0103780 5551 #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0xd010378c 5552 #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0xd0103790 5553 #define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0xd0103794 5554 5555 5556 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 5557 // base address: 0xd0100000 5558 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0xd0142000 5559 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0xd0142004 5560 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0xd0142008 5561 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0xd014200c 5562 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0xd0142010 5563 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0xd0142014 5564 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0xd0142018 5565 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0xd014201c 5566 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0xd0142020 5567 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0xd0142024 5568 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0xd0142028 5569 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0xd014202c 5570 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0xd0142030 5571 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0xd0142034 5572 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0xd0142038 5573 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0xd014203c 5574 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0xd0143000 5575 5576 5577 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 5578 // base address: 0xd0180000 5579 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0xd018382c 5580 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0xd0183830 5581 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd018384c 5582 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0183850 5583 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0183854 5584 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0183858 5585 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd018385c 5586 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0183864 5587 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0183868 5588 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0xd0183898 5589 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0xd018389c 5590 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0xd01838a0 5591 #define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0xd01838c8 5592 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0xd0183958 5593 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0xd018395c 5594 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0xd0183960 5595 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0xd0183964 5596 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0xd0183968 5597 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0xd018396c 5598 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0xd0183970 5599 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0xd0183974 5600 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0xd0183978 5601 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0xd018397c 5602 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0xd0183980 5603 5604 5605 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 5606 // base address: 0xd0180000 5607 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0xd0180000 5608 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA 0xd0180004 5609 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0xd0180018 5610 5611 5612 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 5613 // base address: 0xd0180000 5614 #define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0xd0183694 5615 #define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0xd0183780 5616 #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0xd018378c 5617 #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0xd0183790 5618 #define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0xd0183794 5619 5620 5621 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 5622 // base address: 0xd0180000 5623 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0xd01c2000 5624 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0xd01c2004 5625 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0xd01c2008 5626 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0xd01c200c 5627 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0xd01c2010 5628 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0xd01c2014 5629 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0xd01c2018 5630 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0xd01c201c 5631 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0xd01c2020 5632 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0xd01c2024 5633 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0xd01c2028 5634 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0xd01c202c 5635 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0xd01c2030 5636 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0xd01c2034 5637 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0xd01c2038 5638 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0xd01c203c 5639 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0xd01c3000 5640 5641 5642 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 5643 // base address: 0xd0200000 5644 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0xd020382c 5645 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0xd0203830 5646 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd020384c 5647 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0203850 5648 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0203854 5649 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0203858 5650 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd020385c 5651 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0203864 5652 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0203868 5653 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0xd0203898 5654 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0xd020389c 5655 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0xd02038a0 5656 #define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0xd02038c8 5657 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0xd0203958 5658 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0xd020395c 5659 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0xd0203960 5660 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0xd0203964 5661 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0xd0203968 5662 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0xd020396c 5663 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0xd0203970 5664 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0xd0203974 5665 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0xd0203978 5666 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0xd020397c 5667 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0xd0203980 5668 5669 5670 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 5671 // base address: 0xd0200000 5672 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0xd0200000 5673 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA 0xd0200004 5674 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0xd0200018 5675 5676 5677 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 5678 // base address: 0xd0200000 5679 #define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0xd0203694 5680 #define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0xd0203780 5681 #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0xd020378c 5682 #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0xd0203790 5683 #define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0xd0203794 5684 5685 5686 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 5687 // base address: 0xd0200000 5688 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0xd0242000 5689 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0xd0242004 5690 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0xd0242008 5691 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0xd024200c 5692 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0xd0242010 5693 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0xd0242014 5694 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0xd0242018 5695 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0xd024201c 5696 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0xd0242020 5697 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0xd0242024 5698 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0xd0242028 5699 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0xd024202c 5700 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0xd0242030 5701 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0xd0242034 5702 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0xd0242038 5703 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0xd024203c 5704 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0xd0243000 5705 5706 5707 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 5708 // base address: 0xd0280000 5709 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0xd028382c 5710 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0xd0283830 5711 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd028384c 5712 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0283850 5713 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0283854 5714 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0283858 5715 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd028385c 5716 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0283864 5717 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0283868 5718 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0xd0283898 5719 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0xd028389c 5720 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0xd02838a0 5721 #define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0xd02838c8 5722 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0xd0283958 5723 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0xd028395c 5724 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0xd0283960 5725 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0xd0283964 5726 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0xd0283968 5727 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0xd028396c 5728 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0xd0283970 5729 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0xd0283974 5730 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0xd0283978 5731 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0xd028397c 5732 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0xd0283980 5733 5734 5735 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 5736 // base address: 0xd0280000 5737 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0xd0280000 5738 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA 0xd0280004 5739 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0xd0280018 5740 5741 5742 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 5743 // base address: 0xd0280000 5744 #define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0xd0283694 5745 #define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0xd0283780 5746 #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0xd028378c 5747 #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0xd0283790 5748 #define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0xd0283794 5749 5750 5751 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 5752 // base address: 0xd0280000 5753 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0xd02c2000 5754 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0xd02c2004 5755 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0xd02c2008 5756 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0xd02c200c 5757 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0xd02c2010 5758 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0xd02c2014 5759 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0xd02c2018 5760 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0xd02c201c 5761 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0xd02c2020 5762 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0xd02c2024 5763 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0xd02c2028 5764 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0xd02c202c 5765 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0xd02c2030 5766 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0xd02c2034 5767 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0xd02c2038 5768 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0xd02c203c 5769 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0xd02c3000 5770 5771 5772 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 5773 // base address: 0xd0300000 5774 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0xd030382c 5775 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0xd0303830 5776 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd030384c 5777 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0303850 5778 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0303854 5779 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0303858 5780 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd030385c 5781 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0303864 5782 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0303868 5783 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0xd0303898 5784 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0xd030389c 5785 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0xd03038a0 5786 #define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0xd03038c8 5787 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0xd0303958 5788 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0xd030395c 5789 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0xd0303960 5790 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0xd0303964 5791 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0xd0303968 5792 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0xd030396c 5793 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0xd0303970 5794 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0xd0303974 5795 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0xd0303978 5796 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0xd030397c 5797 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0xd0303980 5798 5799 5800 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 5801 // base address: 0xd0300000 5802 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0xd0300000 5803 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA 0xd0300004 5804 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0xd0300018 5805 5806 5807 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 5808 // base address: 0xd0300000 5809 #define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0xd0303694 5810 #define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0xd0303780 5811 #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0xd030378c 5812 #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0xd0303790 5813 #define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0xd0303794 5814 5815 5816 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 5817 // base address: 0xd0300000 5818 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0xd0342000 5819 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0xd0342004 5820 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0xd0342008 5821 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0xd034200c 5822 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0xd0342010 5823 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0xd0342014 5824 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0xd0342018 5825 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0xd034201c 5826 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0xd0342020 5827 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0xd0342024 5828 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0xd0342028 5829 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0xd034202c 5830 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0xd0342030 5831 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0xd0342034 5832 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0xd0342038 5833 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0xd034203c 5834 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0xd0343000 5835 5836 5837 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 5838 // base address: 0xd0380000 5839 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0xd038382c 5840 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0xd0383830 5841 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd038384c 5842 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0383850 5843 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0383854 5844 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0383858 5845 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd038385c 5846 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0383864 5847 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0383868 5848 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0xd0383898 5849 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0xd038389c 5850 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0xd03838a0 5851 #define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0xd03838c8 5852 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0xd0383958 5853 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0xd038395c 5854 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0xd0383960 5855 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0xd0383964 5856 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0xd0383968 5857 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0xd038396c 5858 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0xd0383970 5859 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0xd0383974 5860 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0xd0383978 5861 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0xd038397c 5862 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0xd0383980 5863 5864 5865 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 5866 // base address: 0xd0380000 5867 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0xd0380000 5868 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA 0xd0380004 5869 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0xd0380018 5870 5871 5872 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 5873 // base address: 0xd0380000 5874 #define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0xd0383694 5875 #define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0xd0383780 5876 #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0xd038378c 5877 #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0xd0383790 5878 #define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0xd0383794 5879 5880 5881 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 5882 // base address: 0xd0380000 5883 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0xd03c2000 5884 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0xd03c2004 5885 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0xd03c2008 5886 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0xd03c200c 5887 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0xd03c2010 5888 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0xd03c2014 5889 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0xd03c2018 5890 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0xd03c201c 5891 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0xd03c2020 5892 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0xd03c2024 5893 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0xd03c2028 5894 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0xd03c202c 5895 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0xd03c2030 5896 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0xd03c2034 5897 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0xd03c2038 5898 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0xd03c203c 5899 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0xd03c3000 5900 5901 5902 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 5903 // base address: 0xd0400000 5904 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0xd040382c 5905 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0xd0403830 5906 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd040384c 5907 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0403850 5908 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0403854 5909 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0403858 5910 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd040385c 5911 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0403864 5912 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0403868 5913 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0xd0403898 5914 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0xd040389c 5915 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0xd04038a0 5916 #define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0xd04038c8 5917 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0xd0403958 5918 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0xd040395c 5919 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0xd0403960 5920 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0xd0403964 5921 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0xd0403968 5922 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0xd040396c 5923 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0xd0403970 5924 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0xd0403974 5925 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0xd0403978 5926 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0xd040397c 5927 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0xd0403980 5928 5929 5930 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 5931 // base address: 0xd0400000 5932 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0xd0400000 5933 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA 0xd0400004 5934 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0xd0400018 5935 5936 5937 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 5938 // base address: 0xd0400000 5939 #define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0xd0403694 5940 #define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0xd0403780 5941 #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0xd040378c 5942 #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0xd0403790 5943 #define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0xd0403794 5944 5945 5946 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 5947 // base address: 0xd0400000 5948 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0xd0442000 5949 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0xd0442004 5950 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0xd0442008 5951 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0xd044200c 5952 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0xd0442010 5953 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0xd0442014 5954 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0xd0442018 5955 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0xd044201c 5956 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0xd0442020 5957 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0xd0442024 5958 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0xd0442028 5959 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0xd044202c 5960 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0xd0442030 5961 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0xd0442034 5962 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0xd0442038 5963 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0xd044203c 5964 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0xd0443000 5965 5966 5967 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 5968 // base address: 0xd0480000 5969 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0xd048382c 5970 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0xd0483830 5971 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd048384c 5972 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0483850 5973 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0483854 5974 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0483858 5975 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd048385c 5976 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0483864 5977 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0483868 5978 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0xd0483898 5979 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0xd048389c 5980 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0xd04838a0 5981 #define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0xd04838c8 5982 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0xd0483958 5983 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0xd048395c 5984 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0xd0483960 5985 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0xd0483964 5986 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0xd0483968 5987 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0xd048396c 5988 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0xd0483970 5989 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0xd0483974 5990 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0xd0483978 5991 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0xd048397c 5992 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0xd0483980 5993 5994 5995 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 5996 // base address: 0xd0480000 5997 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0xd0480000 5998 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA 0xd0480004 5999 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0xd0480018 6000 6001 6002 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 6003 // base address: 0xd0480000 6004 #define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0xd0483694 6005 #define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0xd0483780 6006 #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0xd048378c 6007 #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0xd0483790 6008 #define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0xd0483794 6009 6010 6011 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 6012 // base address: 0xd0480000 6013 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0xd04c2000 6014 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0xd04c2004 6015 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0xd04c2008 6016 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0xd04c200c 6017 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0xd04c2010 6018 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0xd04c2014 6019 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0xd04c2018 6020 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0xd04c201c 6021 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0xd04c2020 6022 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0xd04c2024 6023 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0xd04c2028 6024 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0xd04c202c 6025 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0xd04c2030 6026 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0xd04c2034 6027 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0xd04c2038 6028 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0xd04c203c 6029 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0xd04c3000 6030 6031 6032 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 6033 // base address: 0xd0500000 6034 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0xd050382c 6035 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0xd0503830 6036 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd050384c 6037 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0503850 6038 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0503854 6039 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0503858 6040 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd050385c 6041 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0503864 6042 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0503868 6043 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0xd0503898 6044 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0xd050389c 6045 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0xd05038a0 6046 #define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0xd05038c8 6047 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0xd0503958 6048 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0xd050395c 6049 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0xd0503960 6050 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0xd0503964 6051 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0xd0503968 6052 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0xd050396c 6053 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0xd0503970 6054 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0xd0503974 6055 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0xd0503978 6056 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0xd050397c 6057 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0xd0503980 6058 6059 6060 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 6061 // base address: 0xd0500000 6062 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0xd0500000 6063 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA 0xd0500004 6064 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0xd0500018 6065 6066 6067 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 6068 // base address: 0xd0500000 6069 #define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0xd0503694 6070 #define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0xd0503780 6071 #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0xd050378c 6072 #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0xd0503790 6073 #define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0xd0503794 6074 6075 6076 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 6077 // base address: 0xd0500000 6078 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0xd0542000 6079 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0xd0542004 6080 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0xd0542008 6081 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0xd054200c 6082 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0xd0542010 6083 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0xd0542014 6084 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0xd0542018 6085 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0xd054201c 6086 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0xd0542020 6087 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0xd0542024 6088 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0xd0542028 6089 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0xd054202c 6090 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0xd0542030 6091 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0xd0542034 6092 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0xd0542038 6093 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0xd054203c 6094 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0xd0543000 6095 6096 6097 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 6098 // base address: 0xd0580000 6099 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0xd058382c 6100 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0xd0583830 6101 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd058384c 6102 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0583850 6103 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0583854 6104 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0583858 6105 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd058385c 6106 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0583864 6107 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0583868 6108 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0xd0583898 6109 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0xd058389c 6110 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0xd05838a0 6111 #define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0xd05838c8 6112 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0xd0583958 6113 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0xd058395c 6114 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0xd0583960 6115 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0xd0583964 6116 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0xd0583968 6117 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0xd058396c 6118 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0xd0583970 6119 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0xd0583974 6120 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0xd0583978 6121 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0xd058397c 6122 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0xd0583980 6123 6124 6125 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 6126 // base address: 0xd0580000 6127 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0xd0580000 6128 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA 0xd0580004 6129 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0xd0580018 6130 6131 6132 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 6133 // base address: 0xd0580000 6134 #define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0xd0583694 6135 #define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0xd0583780 6136 #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0xd058378c 6137 #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0xd0583790 6138 #define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0xd0583794 6139 6140 6141 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 6142 // base address: 0xd0580000 6143 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0xd05c2000 6144 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0xd05c2004 6145 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0xd05c2008 6146 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0xd05c200c 6147 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0xd05c2010 6148 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0xd05c2014 6149 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0xd05c2018 6150 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0xd05c201c 6151 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0xd05c2020 6152 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0xd05c2024 6153 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0xd05c2028 6154 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0xd05c202c 6155 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0xd05c2030 6156 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0xd05c2034 6157 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0xd05c2038 6158 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0xd05c203c 6159 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0xd05c3000 6160 6161 6162 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 6163 // base address: 0xd0600000 6164 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0xd060382c 6165 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0xd0603830 6166 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd060384c 6167 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0603850 6168 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0603854 6169 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0603858 6170 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd060385c 6171 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0603864 6172 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0603868 6173 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0xd0603898 6174 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0xd060389c 6175 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0xd06038a0 6176 #define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0xd06038c8 6177 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0xd0603958 6178 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0xd060395c 6179 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0xd0603960 6180 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0xd0603964 6181 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0xd0603968 6182 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0xd060396c 6183 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0xd0603970 6184 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0xd0603974 6185 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0xd0603978 6186 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0xd060397c 6187 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0xd0603980 6188 6189 6190 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 6191 // base address: 0xd0600000 6192 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0xd0600000 6193 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA 0xd0600004 6194 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0xd0600018 6195 6196 6197 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 6198 // base address: 0xd0600000 6199 #define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0xd0603694 6200 #define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0xd0603780 6201 #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0xd060378c 6202 #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0xd0603790 6203 #define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0xd0603794 6204 6205 6206 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 6207 // base address: 0xd0600000 6208 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0xd0642000 6209 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0xd0642004 6210 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0xd0642008 6211 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0xd064200c 6212 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0xd0642010 6213 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0xd0642014 6214 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0xd0642018 6215 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0xd064201c 6216 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0xd0642020 6217 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0xd0642024 6218 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0xd0642028 6219 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0xd064202c 6220 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0xd0642030 6221 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0xd0642034 6222 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0xd0642038 6223 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0xd064203c 6224 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0xd0643000 6225 6226 6227 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 6228 // base address: 0xd0680000 6229 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0xd068382c 6230 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0xd0683830 6231 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd068384c 6232 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0683850 6233 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0683854 6234 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0683858 6235 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd068385c 6236 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0683864 6237 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0683868 6238 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0xd0683898 6239 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0xd068389c 6240 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0xd06838a0 6241 #define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0xd06838c8 6242 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0xd0683958 6243 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0xd068395c 6244 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0xd0683960 6245 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0xd0683964 6246 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0xd0683968 6247 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0xd068396c 6248 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0xd0683970 6249 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0xd0683974 6250 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0xd0683978 6251 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0xd068397c 6252 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0xd0683980 6253 6254 6255 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 6256 // base address: 0xd0680000 6257 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0xd0680000 6258 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA 0xd0680004 6259 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0xd0680018 6260 6261 6262 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 6263 // base address: 0xd0680000 6264 #define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0xd0683694 6265 #define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0xd0683780 6266 #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0xd068378c 6267 #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0xd0683790 6268 #define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0xd0683794 6269 6270 6271 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 6272 // base address: 0xd0680000 6273 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0xd06c2000 6274 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0xd06c2004 6275 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0xd06c2008 6276 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0xd06c200c 6277 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0xd06c2010 6278 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0xd06c2014 6279 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0xd06c2018 6280 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0xd06c201c 6281 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0xd06c2020 6282 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0xd06c2024 6283 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0xd06c2028 6284 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0xd06c202c 6285 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0xd06c2030 6286 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0xd06c2034 6287 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0xd06c2038 6288 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0xd06c203c 6289 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0xd06c3000 6290 6291 6292 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 6293 // base address: 0xd0700000 6294 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0xd070382c 6295 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0xd0703830 6296 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd070384c 6297 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0703850 6298 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0703854 6299 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0703858 6300 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd070385c 6301 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0703864 6302 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0703868 6303 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0xd0703898 6304 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0xd070389c 6305 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0xd07038a0 6306 #define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0xd07038c8 6307 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0xd0703958 6308 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0xd070395c 6309 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0xd0703960 6310 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0xd0703964 6311 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0xd0703968 6312 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0xd070396c 6313 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0xd0703970 6314 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0xd0703974 6315 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0xd0703978 6316 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0xd070397c 6317 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0xd0703980 6318 6319 6320 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 6321 // base address: 0xd0700000 6322 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0xd0700000 6323 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA 0xd0700004 6324 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0xd0700018 6325 6326 6327 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 6328 // base address: 0xd0700000 6329 #define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0xd0703694 6330 #define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0xd0703780 6331 #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0xd070378c 6332 #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0xd0703790 6333 #define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0xd0703794 6334 6335 6336 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 6337 // base address: 0xd0700000 6338 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0xd0742000 6339 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0xd0742004 6340 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0xd0742008 6341 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0xd074200c 6342 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0xd0742010 6343 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0xd0742014 6344 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0xd0742018 6345 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0xd074201c 6346 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0xd0742020 6347 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0xd0742024 6348 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0xd0742028 6349 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0xd074202c 6350 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0xd0742030 6351 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0xd0742034 6352 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0xd0742038 6353 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0xd074203c 6354 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0xd0743000 6355 6356 6357 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 6358 // base address: 0xd0780000 6359 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0xd078382c 6360 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0xd0783830 6361 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd078384c 6362 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0783850 6363 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0783854 6364 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0783858 6365 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd078385c 6366 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0783864 6367 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0783868 6368 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0xd0783898 6369 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0xd078389c 6370 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0xd07838a0 6371 #define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0xd07838c8 6372 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0xd0783958 6373 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0xd078395c 6374 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0xd0783960 6375 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0xd0783964 6376 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0xd0783968 6377 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0xd078396c 6378 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0xd0783970 6379 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0xd0783974 6380 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0xd0783978 6381 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0xd078397c 6382 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0xd0783980 6383 6384 6385 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 6386 // base address: 0xd0780000 6387 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0xd0780000 6388 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA 0xd0780004 6389 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0xd0780018 6390 6391 6392 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 6393 // base address: 0xd0780000 6394 #define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0xd0783694 6395 #define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0xd0783780 6396 #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0xd078378c 6397 #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0xd0783790 6398 #define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0xd0783794 6399 6400 6401 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 6402 // base address: 0xd0780000 6403 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0xd07c2000 6404 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0xd07c2004 6405 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0xd07c2008 6406 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0xd07c200c 6407 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0xd07c2010 6408 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0xd07c2014 6409 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0xd07c2018 6410 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0xd07c201c 6411 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0xd07c2020 6412 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0xd07c2024 6413 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0xd07c2028 6414 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0xd07c202c 6415 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0xd07c2030 6416 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0xd07c2034 6417 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0xd07c2038 6418 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0xd07c203c 6419 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0xd07c3000 6420 6421 6422 // addressBlock: nbio_pcie0_pswusp0_pciedir_p 6423 // base address: 0x1a340000 6424 #define regPCIEP_RESERVED 0x2890000 6425 #define regPCIEP_RESERVED_BASE_IDX 5 6426 #define regPCIEP_SCRATCH 0x2890001 6427 #define regPCIEP_SCRATCH_BASE_IDX 5 6428 #define regPCIEP_PORT_CNTL 0x2890010 6429 #define regPCIEP_PORT_CNTL_BASE_IDX 5 6430 #define regPCIE_TX_REQUESTER_ID 0x2890021 6431 #define regPCIE_TX_REQUESTER_ID_BASE_IDX 5 6432 #define regPCIE_P_PORT_LANE_STATUS 0x2890050 6433 #define regPCIE_P_PORT_LANE_STATUS_BASE_IDX 5 6434 #define regPSWUSP0_PCIE_ERR_CNTL 0x289006a 6435 #define regPSWUSP0_PCIE_ERR_CNTL_BASE_IDX 5 6436 #define regPSWUSP0_PCIE_RX_CNTL 0x2890070 6437 #define regPSWUSP0_PCIE_RX_CNTL_BASE_IDX 5 6438 #define regPCIE_RX_EXPECTED_SEQNUM 0x2890071 6439 #define regPCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 6440 #define regPCIE_RX_VENDOR_SPECIFIC 0x2890072 6441 #define regPCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 6442 #define regPCIE_RX_CNTL3 0x2890074 6443 #define regPCIE_RX_CNTL3_BASE_IDX 5 6444 #define regPCIE_RX_CREDITS_ALLOCATED_P 0x2890080 6445 #define regPCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 6446 #define regPCIE_RX_CREDITS_ALLOCATED_NP 0x2890081 6447 #define regPCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 6448 #define regPCIE_RX_CREDITS_ALLOCATED_CPL 0x2890082 6449 #define regPCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 6450 #define regPCIEP_ERROR_INJECT_PHYSICAL 0x2890083 6451 #define regPCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 6452 #define regPCIEP_ERROR_INJECT_TRANSACTION 0x2890084 6453 #define regPCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 6454 #define regPCIEP_NAK_COUNTER 0x2890086 6455 #define regPCIEP_NAK_COUNTER_BASE_IDX 5 6456 #define regPCIE_LC_CNTL 0x28900a0 6457 #define regPCIE_LC_CNTL_BASE_IDX 5 6458 #define regPCIE_LC_TRAINING_CNTL 0x28900a1 6459 #define regPCIE_LC_TRAINING_CNTL_BASE_IDX 5 6460 #define regPCIE_LC_LINK_WIDTH_CNTL 0x28900a2 6461 #define regPCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 6462 #define regPCIE_LC_N_FTS_CNTL 0x28900a3 6463 #define regPCIE_LC_N_FTS_CNTL_BASE_IDX 5 6464 #define regPSWUSP0_PCIE_LC_SPEED_CNTL 0x28900a4 6465 #define regPSWUSP0_PCIE_LC_SPEED_CNTL_BASE_IDX 5 6466 #define regPCIE_LC_STATE0 0x28900a5 6467 #define regPCIE_LC_STATE0_BASE_IDX 5 6468 #define regPCIE_LC_STATE1 0x28900a6 6469 #define regPCIE_LC_STATE1_BASE_IDX 5 6470 #define regPCIE_LC_STATE2 0x28900a7 6471 #define regPCIE_LC_STATE2_BASE_IDX 5 6472 #define regPCIE_LC_STATE3 0x28900a8 6473 #define regPCIE_LC_STATE3_BASE_IDX 5 6474 #define regPCIE_LC_STATE4 0x28900a9 6475 #define regPCIE_LC_STATE4_BASE_IDX 5 6476 #define regPCIE_LC_STATE5 0x28900aa 6477 #define regPCIE_LC_STATE5_BASE_IDX 5 6478 #define regPSWUSP0_PCIE_LC_CNTL2 0x28900b1 6479 #define regPSWUSP0_PCIE_LC_CNTL2_BASE_IDX 5 6480 #define regPCIE_LC_BW_CHANGE_CNTL 0x28900b2 6481 #define regPCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 6482 #define regPCIE_LC_CDR_CNTL 0x28900b3 6483 #define regPCIE_LC_CDR_CNTL_BASE_IDX 5 6484 #define regPCIE_LC_LANE_CNTL 0x28900b4 6485 #define regPCIE_LC_LANE_CNTL_BASE_IDX 5 6486 #define regPCIE_LC_CNTL3 0x28900b5 6487 #define regPCIE_LC_CNTL3_BASE_IDX 5 6488 #define regPCIE_LC_CNTL4 0x28900b6 6489 #define regPCIE_LC_CNTL4_BASE_IDX 5 6490 #define regPCIE_LC_CNTL5 0x28900b7 6491 #define regPCIE_LC_CNTL5_BASE_IDX 5 6492 #define regPCIE_LC_FORCE_COEFF 0x28900b8 6493 #define regPCIE_LC_FORCE_COEFF_BASE_IDX 5 6494 #define regPCIE_LC_BEST_EQ_SETTINGS 0x28900b9 6495 #define regPCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 6496 #define regPCIE_LC_FORCE_EQ_REQ_COEFF 0x28900ba 6497 #define regPCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 6498 #define regPCIE_LC_CNTL6 0x28900bb 6499 #define regPCIE_LC_CNTL6_BASE_IDX 5 6500 #define regPCIE_LC_CNTL7 0x28900bc 6501 #define regPCIE_LC_CNTL7_BASE_IDX 5 6502 #define regPCIEP_STRAP_LC 0x28900c0 6503 #define regPCIEP_STRAP_LC_BASE_IDX 5 6504 #define regPSWUSP0_PCIEP_STRAP_MISC 0x28900c1 6505 #define regPSWUSP0_PCIEP_STRAP_MISC_BASE_IDX 5 6506 #define regPCIEP_STRAP_LC2 0x28900c2 6507 #define regPCIEP_STRAP_LC2_BASE_IDX 5 6508 #define regPCIE_LC_L1_PM_SUBSTATE 0x28900c6 6509 #define regPCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 6510 #define regPCIE_LC_L1_PM_SUBSTATE2 0x28900c7 6511 #define regPCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 6512 #define regPCIE_LC_L1_PM_SUBSTATE3 0x28900c8 6513 #define regPCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 6514 #define regPCIE_LC_L1_PM_SUBSTATE4 0x28900c9 6515 #define regPCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 6516 #define regPCIE_LC_L1_PM_SUBSTATE5 0x28900ca 6517 #define regPCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 6518 #define regPCIEP_BCH_ECC_CNTL 0x28900d0 6519 #define regPCIEP_BCH_ECC_CNTL_BASE_IDX 5 6520 #define regPCIE_LC_CNTL8 0x28900dd 6521 #define regPCIE_LC_CNTL8_BASE_IDX 5 6522 #define regPCIE_LC_CNTL9 0x28900de 6523 #define regPCIE_LC_CNTL9_BASE_IDX 5 6524 #define regPCIE_LC_FORCE_COEFF2 0x28900df 6525 #define regPCIE_LC_FORCE_COEFF2_BASE_IDX 5 6526 #define regPCIE_LC_FORCE_EQ_REQ_COEFF2 0x28900e0 6527 #define regPCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 6528 #define regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x28900e2 6529 #define regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 6530 #define regPCIE_LC_CNTL10 0x28900e3 6531 #define regPCIE_LC_CNTL10_BASE_IDX 5 6532 #define regPCIE_LC_SAVE_RESTORE_1 0x28900e6 6533 #define regPCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 6534 #define regPCIE_LC_SAVE_RESTORE_2 0x28900e7 6535 #define regPCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 6536 #define regPCIE_LC_CNTL11 0x2890103 6537 #define regPCIE_LC_CNTL11_BASE_IDX 5 6538 #define regPCIE_LC_CNTL12 0x2890104 6539 #define regPCIE_LC_CNTL12_BASE_IDX 5 6540 #define regPCIE_LC_SPEED_CNTL2 0x2890105 6541 #define regPCIE_LC_SPEED_CNTL2_BASE_IDX 5 6542 #define regPCIE_LC_FORCE_COEFF3 0x2890106 6543 #define regPCIE_LC_FORCE_COEFF3_BASE_IDX 5 6544 #define regPCIE_LC_FORCE_EQ_REQ_COEFF3 0x2890107 6545 #define regPCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 6546 #define regPCIE_TX_SEQ 0x2890188 6547 #define regPCIE_TX_SEQ_BASE_IDX 5 6548 #define regPCIE_TX_REPLAY 0x2890189 6549 #define regPCIE_TX_REPLAY_BASE_IDX 5 6550 #define regPCIE_TX_ACK_LATENCY_LIMIT 0x289018c 6551 #define regPCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 6552 #define regPCIE_TX_CREDITS_FCU_THRESHOLD 0x2890190 6553 #define regPCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 6554 #define regPCIE_TX_VENDOR_SPECIFIC 0x2890194 6555 #define regPCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 6556 #define regPCIE_TX_NOP_DLLP 0x2890195 6557 #define regPCIE_TX_NOP_DLLP_BASE_IDX 5 6558 #define regPCIE_TX_REQUEST_NUM_CNTL 0x2890198 6559 #define regPCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 6560 #define regPCIE_TX_CREDITS_ADVT_P 0x28901a0 6561 #define regPCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 6562 #define regPCIE_TX_CREDITS_ADVT_NP 0x28901a1 6563 #define regPCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 6564 #define regPCIE_TX_CREDITS_ADVT_CPL 0x28901a2 6565 #define regPCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 6566 #define regPCIE_TX_CREDITS_INIT_P 0x28901a3 6567 #define regPCIE_TX_CREDITS_INIT_P_BASE_IDX 5 6568 #define regPCIE_TX_CREDITS_INIT_NP 0x28901a4 6569 #define regPCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 6570 #define regPCIE_TX_CREDITS_INIT_CPL 0x28901a5 6571 #define regPCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 6572 #define regPCIE_TX_CREDITS_STATUS 0x28901a6 6573 #define regPCIE_TX_CREDITS_STATUS_BASE_IDX 5 6574 #define regPCIE_FC_P 0x28901a8 6575 #define regPCIE_FC_P_BASE_IDX 5 6576 #define regPCIE_FC_NP 0x28901a9 6577 #define regPCIE_FC_NP_BASE_IDX 5 6578 #define regPCIE_FC_CPL 0x28901aa 6579 #define regPCIE_FC_CPL_BASE_IDX 5 6580 #define regPCIE_FC_P_VC1 0x28901ab 6581 #define regPCIE_FC_P_VC1_BASE_IDX 5 6582 #define regPCIE_FC_NP_VC1 0x28901ac 6583 #define regPCIE_FC_NP_VC1_BASE_IDX 5 6584 #define regPCIE_FC_CPL_VC1 0x28901ad 6585 #define regPCIE_FC_CPL_VC1_BASE_IDX 5 6586 6587 6588 // addressBlock: nbio_pcie0_pciedir 6589 // base address: 0x1a380000 6590 #define regPCIE_RESERVED 0x28a0000 6591 #define regPCIE_RESERVED_BASE_IDX 5 6592 #define regPCIE_SCRATCH 0x28a0001 6593 #define regPCIE_SCRATCH_BASE_IDX 5 6594 #define regPCIE_RX_NUM_NAK 0x28a000e 6595 #define regPCIE_RX_NUM_NAK_BASE_IDX 5 6596 #define regPCIE_RX_NUM_NAK_GENERATED 0x28a000f 6597 #define regPCIE_RX_NUM_NAK_GENERATED_BASE_IDX 5 6598 #define regPCIE_CNTL 0x28a0010 6599 #define regPCIE_CNTL_BASE_IDX 5 6600 #define regPCIE_CONFIG_CNTL 0x28a0011 6601 #define regPCIE_CONFIG_CNTL_BASE_IDX 5 6602 #define regPCIE_RX_CNTL5 0x28a0018 6603 #define regPCIE_RX_CNTL5_BASE_IDX 5 6604 #define regPCIE_RX_CNTL4 0x28a0019 6605 #define regPCIE_RX_CNTL4_BASE_IDX 5 6606 #define regPCIE_COMMON_AER_MASK 0x28a001a 6607 #define regPCIE_COMMON_AER_MASK_BASE_IDX 5 6608 #define regPCIE_CNTL2 0x28a001c 6609 #define regPCIE_CNTL2_BASE_IDX 5 6610 #define regPCIE_RX_CNTL2 0x28a001d 6611 #define regPCIE_RX_CNTL2_BASE_IDX 5 6612 #define regPCIE_CI_CNTL 0x28a0020 6613 #define regPCIE_CI_CNTL_BASE_IDX 5 6614 #define regPCIE_BUS_CNTL 0x28a0021 6615 #define regPCIE_BUS_CNTL_BASE_IDX 5 6616 #define regPCIE_LC_STATE6 0x28a0022 6617 #define regPCIE_LC_STATE6_BASE_IDX 5 6618 #define regPCIE_LC_STATE7 0x28a0023 6619 #define regPCIE_LC_STATE7_BASE_IDX 5 6620 #define regPCIE_LC_STATE8 0x28a0024 6621 #define regPCIE_LC_STATE8_BASE_IDX 5 6622 #define regPCIE_LC_STATE9 0x28a0025 6623 #define regPCIE_LC_STATE9_BASE_IDX 5 6624 #define regPCIE_LC_STATE10 0x28a0026 6625 #define regPCIE_LC_STATE10_BASE_IDX 5 6626 #define regPCIE_LC_STATE11 0x28a0027 6627 #define regPCIE_LC_STATE11_BASE_IDX 5 6628 #define regPCIE_LC_STATUS1 0x28a0028 6629 #define regPCIE_LC_STATUS1_BASE_IDX 5 6630 #define regPCIE_LC_STATUS2 0x28a0029 6631 #define regPCIE_LC_STATUS2_BASE_IDX 5 6632 #define regPCIE_WPR_CNTL 0x28a0030 6633 #define regPCIE_WPR_CNTL_BASE_IDX 5 6634 #define regPCIE_RX_LAST_TLP0 0x28a0031 6635 #define regPCIE_RX_LAST_TLP0_BASE_IDX 5 6636 #define regPCIE_RX_LAST_TLP1 0x28a0032 6637 #define regPCIE_RX_LAST_TLP1_BASE_IDX 5 6638 #define regPCIE_RX_LAST_TLP2 0x28a0033 6639 #define regPCIE_RX_LAST_TLP2_BASE_IDX 5 6640 #define regPCIE_RX_LAST_TLP3 0x28a0034 6641 #define regPCIE_RX_LAST_TLP3_BASE_IDX 5 6642 #define regPCIE_I2C_REG_ADDR_EXPAND 0x28a003a 6643 #define regPCIE_I2C_REG_ADDR_EXPAND_BASE_IDX 5 6644 #define regPCIE_I2C_REG_DATA 0x28a003b 6645 #define regPCIE_I2C_REG_DATA_BASE_IDX 5 6646 #define regPCIE_CFG_CNTL 0x28a003c 6647 #define regPCIE_CFG_CNTL_BASE_IDX 5 6648 #define regPCIE_LC_PM_CNTL 0x28a003d 6649 #define regPCIE_LC_PM_CNTL_BASE_IDX 5 6650 #define regPCIE_LC_PM_CNTL2 0x28a003e 6651 #define regPCIE_LC_PM_CNTL2_BASE_IDX 5 6652 #define regPCIE_P_CNTL 0x28a0040 6653 #define regPCIE_P_CNTL_BASE_IDX 5 6654 #define regPCIE_P_BUF_STATUS 0x28a0041 6655 #define regPCIE_P_BUF_STATUS_BASE_IDX 5 6656 #define regPCIE_P_DECODER_STATUS 0x28a0042 6657 #define regPCIE_P_DECODER_STATUS_BASE_IDX 5 6658 #define regPCIE_P_MISC_STATUS 0x28a0043 6659 #define regPCIE_P_MISC_STATUS_BASE_IDX 5 6660 #define regPCIE_P_RCV_L0S_FTS_DET 0x28a0050 6661 #define regPCIE_P_RCV_L0S_FTS_DET_BASE_IDX 5 6662 #define regPCIE_RX_AD 0x28a0062 6663 #define regPCIE_RX_AD_BASE_IDX 5 6664 #define regPCIE_SDP_CTRL 0x28a0063 6665 #define regPCIE_SDP_CTRL_BASE_IDX 5 6666 #define regPCIE_SDP_SWUS_SLV_ATTR_CTRL 0x28a0065 6667 #define regPCIE_SDP_SWUS_SLV_ATTR_CTRL_BASE_IDX 5 6668 #define regPCIE_SDP_CTRL2 0x28a0068 6669 #define regPCIE_SDP_CTRL2_BASE_IDX 5 6670 #define regPCIE_PERF_COUNT_CNTL 0x28a0080 6671 #define regPCIE_PERF_COUNT_CNTL_BASE_IDX 5 6672 #define regPCIE_PERF_CNTL_TXCLK1 0x28a0081 6673 #define regPCIE_PERF_CNTL_TXCLK1_BASE_IDX 5 6674 #define regPCIE_PERF_COUNT0_TXCLK1 0x28a0082 6675 #define regPCIE_PERF_COUNT0_TXCLK1_BASE_IDX 5 6676 #define regPCIE_PERF_COUNT1_TXCLK1 0x28a0083 6677 #define regPCIE_PERF_COUNT1_TXCLK1_BASE_IDX 5 6678 #define regPCIE_PERF_CNTL_TXCLK2 0x28a0084 6679 #define regPCIE_PERF_CNTL_TXCLK2_BASE_IDX 5 6680 #define regPCIE_PERF_COUNT0_TXCLK2 0x28a0085 6681 #define regPCIE_PERF_COUNT0_TXCLK2_BASE_IDX 5 6682 #define regPCIE_PERF_COUNT1_TXCLK2 0x28a0086 6683 #define regPCIE_PERF_COUNT1_TXCLK2_BASE_IDX 5 6684 #define regPCIE_PERF_CNTL_TXCLK3 0x28a0087 6685 #define regPCIE_PERF_CNTL_TXCLK3_BASE_IDX 5 6686 #define regPCIE_PERF_COUNT0_TXCLK3 0x28a0088 6687 #define regPCIE_PERF_COUNT0_TXCLK3_BASE_IDX 5 6688 #define regPCIE_PERF_COUNT1_TXCLK3 0x28a0089 6689 #define regPCIE_PERF_COUNT1_TXCLK3_BASE_IDX 5 6690 #define regPCIE_PERF_CNTL_TXCLK4 0x28a008a 6691 #define regPCIE_PERF_CNTL_TXCLK4_BASE_IDX 5 6692 #define regPCIE_PERF_COUNT0_TXCLK4 0x28a008b 6693 #define regPCIE_PERF_COUNT0_TXCLK4_BASE_IDX 5 6694 #define regPCIE_PERF_COUNT1_TXCLK4 0x28a008c 6695 #define regPCIE_PERF_COUNT1_TXCLK4_BASE_IDX 5 6696 #define regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x28a0093 6697 #define regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL_BASE_IDX 5 6698 #define regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x28a0094 6699 #define regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL_BASE_IDX 5 6700 #define regPCIE_PERF_CNTL_TXCLK5 0x28a0096 6701 #define regPCIE_PERF_CNTL_TXCLK5_BASE_IDX 5 6702 #define regPCIE_PERF_COUNT0_TXCLK5 0x28a0097 6703 #define regPCIE_PERF_COUNT0_TXCLK5_BASE_IDX 5 6704 #define regPCIE_PERF_COUNT1_TXCLK5 0x28a0098 6705 #define regPCIE_PERF_COUNT1_TXCLK5_BASE_IDX 5 6706 #define regPCIE_PERF_CNTL_TXCLK6 0x28a0099 6707 #define regPCIE_PERF_CNTL_TXCLK6_BASE_IDX 5 6708 #define regPCIE_PERF_COUNT0_TXCLK6 0x28a009a 6709 #define regPCIE_PERF_COUNT0_TXCLK6_BASE_IDX 5 6710 #define regPCIE_PERF_COUNT1_TXCLK6 0x28a009b 6711 #define regPCIE_PERF_COUNT1_TXCLK6_BASE_IDX 5 6712 #define regPCIE_STRAP_F0 0x28a00b0 6713 #define regPCIE_STRAP_F0_BASE_IDX 5 6714 #define regPCIE_STRAP_MISC 0x28a00c0 6715 #define regPCIE_STRAP_MISC_BASE_IDX 5 6716 #define regPCIE_STRAP_MISC2 0x28a00c1 6717 #define regPCIE_STRAP_MISC2_BASE_IDX 5 6718 #define regPCIE_STRAP_PI 0x28a00c2 6719 #define regPCIE_STRAP_PI_BASE_IDX 5 6720 #define regPCIE_STRAP_I2C_BD 0x28a00c4 6721 #define regPCIE_STRAP_I2C_BD_BASE_IDX 5 6722 #define regPCIE_PRBS_CLR 0x28a00c8 6723 #define regPCIE_PRBS_CLR_BASE_IDX 5 6724 #define regPCIE_PRBS_STATUS1 0x28a00c9 6725 #define regPCIE_PRBS_STATUS1_BASE_IDX 5 6726 #define regPCIE_PRBS_STATUS2 0x28a00ca 6727 #define regPCIE_PRBS_STATUS2_BASE_IDX 5 6728 #define regPCIE_PRBS_FREERUN 0x28a00cb 6729 #define regPCIE_PRBS_FREERUN_BASE_IDX 5 6730 #define regPCIE_PRBS_MISC 0x28a00cc 6731 #define regPCIE_PRBS_MISC_BASE_IDX 5 6732 #define regPCIE_PRBS_USER_PATTERN 0x28a00cd 6733 #define regPCIE_PRBS_USER_PATTERN_BASE_IDX 5 6734 #define regPCIE_PRBS_LO_BITCNT 0x28a00ce 6735 #define regPCIE_PRBS_LO_BITCNT_BASE_IDX 5 6736 #define regPCIE_PRBS_HI_BITCNT 0x28a00cf 6737 #define regPCIE_PRBS_HI_BITCNT_BASE_IDX 5 6738 #define regPCIE_PRBS_ERRCNT_0 0x28a00d0 6739 #define regPCIE_PRBS_ERRCNT_0_BASE_IDX 5 6740 #define regPCIE_PRBS_ERRCNT_1 0x28a00d1 6741 #define regPCIE_PRBS_ERRCNT_1_BASE_IDX 5 6742 #define regPCIE_PRBS_ERRCNT_2 0x28a00d2 6743 #define regPCIE_PRBS_ERRCNT_2_BASE_IDX 5 6744 #define regPCIE_PRBS_ERRCNT_3 0x28a00d3 6745 #define regPCIE_PRBS_ERRCNT_3_BASE_IDX 5 6746 #define regPCIE_PRBS_ERRCNT_4 0x28a00d4 6747 #define regPCIE_PRBS_ERRCNT_4_BASE_IDX 5 6748 #define regPCIE_PRBS_ERRCNT_5 0x28a00d5 6749 #define regPCIE_PRBS_ERRCNT_5_BASE_IDX 5 6750 #define regPCIE_PRBS_ERRCNT_6 0x28a00d6 6751 #define regPCIE_PRBS_ERRCNT_6_BASE_IDX 5 6752 #define regPCIE_PRBS_ERRCNT_7 0x28a00d7 6753 #define regPCIE_PRBS_ERRCNT_7_BASE_IDX 5 6754 #define regPCIE_PRBS_ERRCNT_8 0x28a00d8 6755 #define regPCIE_PRBS_ERRCNT_8_BASE_IDX 5 6756 #define regPCIE_PRBS_ERRCNT_9 0x28a00d9 6757 #define regPCIE_PRBS_ERRCNT_9_BASE_IDX 5 6758 #define regPCIE_PRBS_ERRCNT_10 0x28a00da 6759 #define regPCIE_PRBS_ERRCNT_10_BASE_IDX 5 6760 #define regPCIE_PRBS_ERRCNT_11 0x28a00db 6761 #define regPCIE_PRBS_ERRCNT_11_BASE_IDX 5 6762 #define regPCIE_PRBS_ERRCNT_12 0x28a00dc 6763 #define regPCIE_PRBS_ERRCNT_12_BASE_IDX 5 6764 #define regPCIE_PRBS_ERRCNT_13 0x28a00dd 6765 #define regPCIE_PRBS_ERRCNT_13_BASE_IDX 5 6766 #define regPCIE_PRBS_ERRCNT_14 0x28a00de 6767 #define regPCIE_PRBS_ERRCNT_14_BASE_IDX 5 6768 #define regPCIE_PRBS_ERRCNT_15 0x28a00df 6769 #define regPCIE_PRBS_ERRCNT_15_BASE_IDX 5 6770 #define regSWRST_COMMAND_STATUS 0x28a0100 6771 #define regSWRST_COMMAND_STATUS_BASE_IDX 5 6772 #define regSWRST_GENERAL_CONTROL 0x28a0101 6773 #define regSWRST_GENERAL_CONTROL_BASE_IDX 5 6774 #define regSWRST_COMMAND_0 0x28a0102 6775 #define regSWRST_COMMAND_0_BASE_IDX 5 6776 #define regSWRST_COMMAND_1 0x28a0103 6777 #define regSWRST_COMMAND_1_BASE_IDX 5 6778 #define regSWRST_CONTROL_0 0x28a0104 6779 #define regSWRST_CONTROL_0_BASE_IDX 5 6780 #define regSWRST_CONTROL_1 0x28a0105 6781 #define regSWRST_CONTROL_1_BASE_IDX 5 6782 #define regSWRST_CONTROL_2 0x28a0106 6783 #define regSWRST_CONTROL_2_BASE_IDX 5 6784 #define regSWRST_CONTROL_3 0x28a0107 6785 #define regSWRST_CONTROL_3_BASE_IDX 5 6786 #define regSWRST_CONTROL_4 0x28a0108 6787 #define regSWRST_CONTROL_4_BASE_IDX 5 6788 #define regSWRST_CONTROL_5 0x28a0109 6789 #define regSWRST_CONTROL_5_BASE_IDX 5 6790 #define regSWRST_CONTROL_6 0x28a010a 6791 #define regSWRST_CONTROL_6_BASE_IDX 5 6792 #define regSWRST_EP_COMMAND_0 0x28a010b 6793 #define regSWRST_EP_COMMAND_0_BASE_IDX 5 6794 #define regSWRST_EP_CONTROL_0 0x28a010c 6795 #define regSWRST_EP_CONTROL_0_BASE_IDX 5 6796 #define regCPM_CONTROL 0x28a0118 6797 #define regCPM_CONTROL_BASE_IDX 5 6798 #define regCPM_SPLIT_CONTROL 0x28a0119 6799 #define regCPM_SPLIT_CONTROL_BASE_IDX 5 6800 #define regCPM_CONTROL_EXT 0x28a011a 6801 #define regCPM_CONTROL_EXT_BASE_IDX 5 6802 #define regSMN_APERTURE_ID_A 0x28a011d 6803 #define regSMN_APERTURE_ID_A_BASE_IDX 5 6804 #define regSMN_APERTURE_ID_B 0x28a011e 6805 #define regSMN_APERTURE_ID_B_BASE_IDX 5 6806 #define regLNCNT_CONTROL 0x28a0125 6807 #define regLNCNT_CONTROL_BASE_IDX 5 6808 #define regSMU_INT_PIN_SHARING_PORT_INDICATOR 0x28a012f 6809 #define regSMU_INT_PIN_SHARING_PORT_INDICATOR_BASE_IDX 5 6810 #define regPCIE_PGMST_CNTL 0x28a0130 6811 #define regPCIE_PGMST_CNTL_BASE_IDX 5 6812 #define regPCIE_PGSLV_CNTL 0x28a0131 6813 #define regPCIE_PGSLV_CNTL_BASE_IDX 5 6814 #define regLC_CPM_CONTROL_0 0x28a0133 6815 #define regLC_CPM_CONTROL_0_BASE_IDX 5 6816 #define regLC_CPM_CONTROL_1 0x28a0134 6817 #define regLC_CPM_CONTROL_1_BASE_IDX 5 6818 #define regPCIE_RXMARGIN_CONTROL_CAPABILITIES 0x28a0135 6819 #define regPCIE_RXMARGIN_CONTROL_CAPABILITIES_BASE_IDX 5 6820 #define regPCIE_RXMARGIN_1_SETTINGS 0x28a0136 6821 #define regPCIE_RXMARGIN_1_SETTINGS_BASE_IDX 5 6822 #define regPCIE_RXMARGIN_2_SETTINGS 0x28a0137 6823 #define regPCIE_RXMARGIN_2_SETTINGS_BASE_IDX 5 6824 #define regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO 0x28a013a 6825 #define regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO_BASE_IDX 5 6826 #define regPCIE_TX_LAST_TLP0 0x28a0180 6827 #define regPCIE_TX_LAST_TLP0_BASE_IDX 5 6828 #define regPCIE_TX_LAST_TLP1 0x28a0181 6829 #define regPCIE_TX_LAST_TLP1_BASE_IDX 5 6830 #define regPCIE_TX_LAST_TLP2 0x28a0182 6831 #define regPCIE_TX_LAST_TLP2_BASE_IDX 5 6832 #define regPCIE_TX_LAST_TLP3 0x28a0183 6833 #define regPCIE_TX_LAST_TLP3_BASE_IDX 5 6834 #define regPCIE_TX_TRACKING_ADDR_LO 0x28a0184 6835 #define regPCIE_TX_TRACKING_ADDR_LO_BASE_IDX 5 6836 #define regPCIE_TX_TRACKING_ADDR_HI 0x28a0185 6837 #define regPCIE_TX_TRACKING_ADDR_HI_BASE_IDX 5 6838 #define regPCIE_TX_TRACKING_CTRL_STATUS 0x28a0186 6839 #define regPCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX 5 6840 #define regPCIE_TX_CTRL_4 0x28a018b 6841 #define regPCIE_TX_CTRL_4_BASE_IDX 5 6842 #define regPCIE_TX_STATUS 0x28a0194 6843 #define regPCIE_TX_STATUS_BASE_IDX 5 6844 #define regPCIE_TX_F0_ATTR_CNTL 0x28a019c 6845 #define regPCIE_TX_F0_ATTR_CNTL_BASE_IDX 5 6846 #define regPCIE_TX_SWUS_ATTR_CNTL 0x28a019d 6847 #define regPCIE_TX_SWUS_ATTR_CNTL_BASE_IDX 5 6848 #define regPCIE_MST_CTRL_1 0x28a01c4 6849 #define regPCIE_MST_CTRL_1_BASE_IDX 5 6850 #define regPCIE_HIP_REG0 0x28a01e0 6851 #define regPCIE_HIP_REG0_BASE_IDX 5 6852 #define regPCIE_HIP_REG1 0x28a01e1 6853 #define regPCIE_HIP_REG1_BASE_IDX 5 6854 #define regPCIE_HIP_REG2 0x28a01e2 6855 #define regPCIE_HIP_REG2_BASE_IDX 5 6856 #define regPCIE_HIP_REG3 0x28a01e3 6857 #define regPCIE_HIP_REG3_BASE_IDX 5 6858 #define regPCIE_HIP_REG4 0x28a01e4 6859 #define regPCIE_HIP_REG4_BASE_IDX 5 6860 #define regPCIE_HIP_REG5 0x28a01e5 6861 #define regPCIE_HIP_REG5_BASE_IDX 5 6862 #define regPCIE_HIP_REG6 0x28a01e6 6863 #define regPCIE_HIP_REG6_BASE_IDX 5 6864 #define regPCIE_HIP_REG7 0x28a01e7 6865 #define regPCIE_HIP_REG7_BASE_IDX 5 6866 #define regPCIE_HIP_REG8 0x28a01e8 6867 #define regPCIE_HIP_REG8_BASE_IDX 5 6868 #define regSMU_PCIE_FENCED1_REG 0x28a0200 6869 #define regSMU_PCIE_FENCED1_REG_BASE_IDX 5 6870 #define regSMU_PCIE_FENCED2_REG 0x28a0201 6871 #define regSMU_PCIE_FENCED2_REG_BASE_IDX 5 6872 #define regPCIE_PERF_CNTL_TXCLK7 0x28a0222 6873 #define regPCIE_PERF_CNTL_TXCLK7_BASE_IDX 5 6874 #define regPCIE_PERF_COUNT0_TXCLK7 0x28a0223 6875 #define regPCIE_PERF_COUNT0_TXCLK7_BASE_IDX 5 6876 #define regPCIE_PERF_COUNT1_TXCLK7 0x28a0224 6877 #define regPCIE_PERF_COUNT1_TXCLK7_BASE_IDX 5 6878 #define regPCIE_PERF_CNTL_TXCLK8 0x28a0225 6879 #define regPCIE_PERF_CNTL_TXCLK8_BASE_IDX 5 6880 #define regPCIE_PERF_COUNT0_TXCLK8 0x28a0226 6881 #define regPCIE_PERF_COUNT0_TXCLK8_BASE_IDX 5 6882 #define regPCIE_PERF_COUNT1_TXCLK8 0x28a0227 6883 #define regPCIE_PERF_COUNT1_TXCLK8_BASE_IDX 5 6884 #define regPCIE_PERF_CNTL_TXCLK9 0x28a0228 6885 #define regPCIE_PERF_CNTL_TXCLK9_BASE_IDX 5 6886 #define regPCIE_PERF_COUNT0_TXCLK9 0x28a0229 6887 #define regPCIE_PERF_COUNT0_TXCLK9_BASE_IDX 5 6888 #define regPCIE_PERF_COUNT1_TXCLK9 0x28a022a 6889 #define regPCIE_PERF_COUNT1_TXCLK9_BASE_IDX 5 6890 #define regPCIE_PERF_CNTL_TXCLK10 0x28a022b 6891 #define regPCIE_PERF_CNTL_TXCLK10_BASE_IDX 5 6892 #define regPCIE_PERF_COUNT0_TXCLK10 0x28a022c 6893 #define regPCIE_PERF_COUNT0_TXCLK10_BASE_IDX 5 6894 #define regPCIE_PERF_COUNT1_TXCLK10 0x28a022d 6895 #define regPCIE_PERF_COUNT1_TXCLK10_BASE_IDX 5 6896 6897 6898 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp 6899 // base address: 0x1a300000 6900 #define regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x2880006 6901 #define regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 6902 #define regPSWUSCFG0_IO_BASE_LIMIT 0x2880007 6903 #define regPSWUSCFG0_IO_BASE_LIMIT_BASE_IDX 5 6904 #define regPSWUSCFG0_SECONDARY_STATUS 0x2880007 6905 #define regPSWUSCFG0_SECONDARY_STATUS_BASE_IDX 5 6906 #define regPSWUSCFG0_MEM_BASE_LIMIT 0x2880008 6907 #define regPSWUSCFG0_MEM_BASE_LIMIT_BASE_IDX 5 6908 #define regPSWUSCFG0_PREF_BASE_LIMIT 0x2880009 6909 #define regPSWUSCFG0_PREF_BASE_LIMIT_BASE_IDX 5 6910 #define regPSWUSCFG0_PREF_BASE_UPPER 0x288000a 6911 #define regPSWUSCFG0_PREF_BASE_UPPER_BASE_IDX 5 6912 #define regPSWUSCFG0_PREF_LIMIT_UPPER 0x288000b 6913 #define regPSWUSCFG0_PREF_LIMIT_UPPER_BASE_IDX 5 6914 #define regPSWUSCFG0_IO_BASE_LIMIT_HI 0x288000c 6915 #define regPSWUSCFG0_IO_BASE_LIMIT_HI_BASE_IDX 5 6916 #define regPSWUSCFG0_SSID_CAP_LIST 0x2880030 6917 #define regPSWUSCFG0_SSID_CAP_LIST_BASE_IDX 5 6918 #define regPSWUSCFG0_SSID_CAP 0x2880031 6919 #define regPSWUSCFG0_SSID_CAP_BASE_IDX 5 6920 6921 #define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL 0x2890102 6922 #define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX 5 6923 6924 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp 6925 // base address: 0x10100000 6926 #define regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 0x0006 6927 #define regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 6928 #define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT 0x0007 6929 #define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_BASE_IDX 5 6930 #define regBIF_CFG_DEV0_RC_SECONDARY_STATUS 0x0007 6931 #define regBIF_CFG_DEV0_RC_SECONDARY_STATUS_BASE_IDX 5 6932 #define regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 0x0008 6933 #define regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT_BASE_IDX 5 6934 #define regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 0x0009 6935 #define regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT_BASE_IDX 5 6936 #define regBIF_CFG_DEV0_RC_PREF_BASE_UPPER 0x000a 6937 #define regBIF_CFG_DEV0_RC_PREF_BASE_UPPER_BASE_IDX 5 6938 #define regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 0x000b 6939 #define regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER_BASE_IDX 5 6940 #define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 0x000c 6941 #define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI_BASE_IDX 5 6942 #define regSLOT_CAP 0x001b 6943 #define regSLOT_CAP_BASE_IDX 5 6944 #define regSLOT_CNTL 0x001c 6945 #define regSLOT_CNTL_BASE_IDX 5 6946 #define regSLOT_STATUS 0x001c 6947 #define regSLOT_STATUS_BASE_IDX 5 6948 #define regSLOT_CAP2 0x0023 6949 #define regSLOT_CAP2_BASE_IDX 5 6950 #define regSLOT_CNTL2 0x0024 6951 #define regSLOT_CNTL2_BASE_IDX 5 6952 #define regSLOT_STATUS2 0x0024 6953 #define regSLOT_STATUS2_BASE_IDX 5 6954 #define regBIF_CFG_DEV0_RC_SSID_CAP_LIST 0x0030 6955 #define regBIF_CFG_DEV0_RC_SSID_CAP_LIST_BASE_IDX 5 6956 #define regBIF_CFG_DEV0_RC_SSID_CAP 0x0031 6957 #define regBIF_CFG_DEV0_RC_SSID_CAP_BASE_IDX 5 6958 6959 6960 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 6961 // base address: 0x10140000 6962 #define regBIF_CFG_DEV0_EPF0_VENDOR_ID 0x10000 6963 #define regBIF_CFG_DEV0_EPF0_VENDOR_ID_BASE_IDX 5 6964 #define regBIF_CFG_DEV0_EPF0_DEVICE_ID 0x10000 6965 #define regBIF_CFG_DEV0_EPF0_DEVICE_ID_BASE_IDX 5 6966 #define regBIF_CFG_DEV0_EPF0_COMMAND 0x10001 6967 #define regBIF_CFG_DEV0_EPF0_COMMAND_BASE_IDX 5 6968 #define regBIF_CFG_DEV0_EPF0_STATUS 0x10001 6969 #define regBIF_CFG_DEV0_EPF0_STATUS_BASE_IDX 5 6970 #define regBIF_CFG_DEV0_EPF0_REVISION_ID 0x10002 6971 #define regBIF_CFG_DEV0_EPF0_REVISION_ID_BASE_IDX 5 6972 #define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x10002 6973 #define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE_BASE_IDX 5 6974 #define regBIF_CFG_DEV0_EPF0_SUB_CLASS 0x10002 6975 #define regBIF_CFG_DEV0_EPF0_SUB_CLASS_BASE_IDX 5 6976 #define regBIF_CFG_DEV0_EPF0_BASE_CLASS 0x10002 6977 #define regBIF_CFG_DEV0_EPF0_BASE_CLASS_BASE_IDX 5 6978 #define regBIF_CFG_DEV0_EPF0_CACHE_LINE 0x10003 6979 #define regBIF_CFG_DEV0_EPF0_CACHE_LINE_BASE_IDX 5 6980 #define regBIF_CFG_DEV0_EPF0_LATENCY 0x10003 6981 #define regBIF_CFG_DEV0_EPF0_LATENCY_BASE_IDX 5 6982 #define regBIF_CFG_DEV0_EPF0_HEADER 0x10003 6983 #define regBIF_CFG_DEV0_EPF0_HEADER_BASE_IDX 5 6984 #define regBIF_CFG_DEV0_EPF0_BIST 0x10003 6985 #define regBIF_CFG_DEV0_EPF0_BIST_BASE_IDX 5 6986 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x10004 6987 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1_BASE_IDX 5 6988 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x10005 6989 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2_BASE_IDX 5 6990 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x10006 6991 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3_BASE_IDX 5 6992 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x10007 6993 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4_BASE_IDX 5 6994 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x10008 6995 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5_BASE_IDX 5 6996 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x10009 6997 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6_BASE_IDX 5 6998 #define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x1000a 6999 #define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_BASE_IDX 5 7000 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x1000b 7001 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_BASE_IDX 5 7002 #define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x1000c 7003 #define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_BASE_IDX 5 7004 #define regBIF_CFG_DEV0_EPF0_CAP_PTR 0x1000d 7005 #define regBIF_CFG_DEV0_EPF0_CAP_PTR_BASE_IDX 5 7006 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x1000f 7007 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_BASE_IDX 5 7008 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x1000f 7009 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_BASE_IDX 5 7010 #define regBIF_CFG_DEV0_EPF0_MIN_GRANT 0x1000f 7011 #define regBIF_CFG_DEV0_EPF0_MIN_GRANT_BASE_IDX 5 7012 #define regBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x1000f 7013 #define regBIF_CFG_DEV0_EPF0_MAX_LATENCY_BASE_IDX 5 7014 #define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x10012 7015 #define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_BASE_IDX 5 7016 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x10013 7017 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_BASE_IDX 5 7018 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x10014 7019 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_BASE_IDX 5 7020 #define regBIF_CFG_DEV0_EPF0_PMI_CAP 0x10014 7021 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_BASE_IDX 5 7022 #define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x10015 7023 #define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_BASE_IDX 5 7024 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x10019 7025 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_BASE_IDX 5 7026 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP 0x10019 7027 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_BASE_IDX 5 7028 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x1001a 7029 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP_BASE_IDX 5 7030 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x1001b 7031 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL_BASE_IDX 5 7032 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x1001b 7033 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS_BASE_IDX 5 7034 #define regBIF_CFG_DEV0_EPF0_LINK_CAP 0x1001c 7035 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_BASE_IDX 5 7036 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL 0x1001d 7037 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_BASE_IDX 5 7038 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS 0x1001d 7039 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_BASE_IDX 5 7040 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x10022 7041 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2_BASE_IDX 5 7042 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x10023 7043 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_BASE_IDX 5 7044 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x10023 7045 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_BASE_IDX 5 7046 #define regBIF_CFG_DEV0_EPF0_LINK_CAP2 0x10024 7047 #define regBIF_CFG_DEV0_EPF0_LINK_CAP2_BASE_IDX 5 7048 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x10025 7049 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL2_BASE_IDX 5 7050 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x10025 7051 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS2_BASE_IDX 5 7052 #define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x10028 7053 #define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_BASE_IDX 5 7054 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x10028 7055 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_BASE_IDX 5 7056 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x10029 7057 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_BASE_IDX 5 7058 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x1002a 7059 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_BASE_IDX 5 7060 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x1002a 7061 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_BASE_IDX 5 7062 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x1002a 7063 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_BASE_IDX 5 7064 #define regBIF_CFG_DEV0_EPF0_MSI_MASK 0x1002b 7065 #define regBIF_CFG_DEV0_EPF0_MSI_MASK_BASE_IDX 5 7066 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x1002b 7067 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_BASE_IDX 5 7068 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x1002b 7069 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 7070 #define regBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x1002c 7071 #define regBIF_CFG_DEV0_EPF0_MSI_MASK_64_BASE_IDX 5 7072 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING 0x1002c 7073 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_BASE_IDX 5 7074 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x1002d 7075 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64_BASE_IDX 5 7076 #define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x10030 7077 #define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_BASE_IDX 5 7078 #define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x10030 7079 #define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_BASE_IDX 5 7080 #define regBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x10031 7081 #define regBIF_CFG_DEV0_EPF0_MSIX_TABLE_BASE_IDX 5 7082 #define regBIF_CFG_DEV0_EPF0_MSIX_PBA 0x10032 7083 #define regBIF_CFG_DEV0_EPF0_MSIX_PBA_BASE_IDX 5 7084 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 7085 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 7086 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 7087 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 7088 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x10042 7089 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 7090 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x10043 7091 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 7092 #define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x10044 7093 #define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 7094 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x10045 7095 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 7096 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x10046 7097 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 7098 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x10047 7099 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_BASE_IDX 5 7100 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x10047 7101 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_BASE_IDX 5 7102 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x10048 7103 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 7104 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x10049 7105 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 7106 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x1004a 7107 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 7108 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x1004b 7109 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 7110 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x1004c 7111 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 7112 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x1004d 7113 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 7114 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 7115 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 7116 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 7117 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 7118 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 7119 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 7120 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 7121 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 7122 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x10055 7123 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 7124 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x10056 7125 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 7126 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x10057 7127 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 7128 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x10058 7129 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 7130 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x10059 7131 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 7132 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x1005a 7133 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 7134 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x1005b 7135 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_BASE_IDX 5 7136 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x1005c 7137 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_BASE_IDX 5 7138 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x1005d 7139 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_BASE_IDX 5 7140 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x1005e 7141 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_BASE_IDX 5 7142 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x10062 7143 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 7144 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x10063 7145 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 7146 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x10064 7147 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 7148 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x10065 7149 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 7150 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x10080 7151 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 7152 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x10081 7153 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_BASE_IDX 5 7154 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x10082 7155 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_BASE_IDX 5 7156 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x10083 7157 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_BASE_IDX 5 7158 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x10084 7159 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_BASE_IDX 5 7160 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x10085 7161 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_BASE_IDX 5 7162 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x10086 7163 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_BASE_IDX 5 7164 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x10087 7165 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_BASE_IDX 5 7166 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x10088 7167 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_BASE_IDX 5 7168 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x10089 7169 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_BASE_IDX 5 7170 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x1008a 7171 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_BASE_IDX 5 7172 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x1008b 7173 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_BASE_IDX 5 7174 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x1008c 7175 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_BASE_IDX 5 7176 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 7177 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 7178 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 7179 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 7180 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x10092 7181 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 7182 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x10093 7183 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 7184 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x10094 7185 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 7186 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x10095 7187 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_BASE_IDX 5 7188 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x10096 7189 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 7190 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x10097 7191 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_BASE_IDX 5 7192 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x10097 7193 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_BASE_IDX 5 7194 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 7195 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 7196 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 7197 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 7198 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 7199 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 7200 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 7201 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 7202 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 7203 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 7204 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 7205 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 7206 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 7207 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 7208 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 7209 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 7210 #define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c 7211 #define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 7212 #define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x1009d 7213 #define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_BASE_IDX 5 7214 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x1009e 7215 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 7216 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f 7217 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 7218 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f 7219 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 7220 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 7221 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 7222 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 7223 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 7224 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 7225 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 7226 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 7227 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 7228 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 7229 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 7230 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 7231 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 7232 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 7233 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 7234 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 7235 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 7236 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 7237 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 7238 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 7239 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 7240 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 7241 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 7242 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 7243 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 7244 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 7245 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 7246 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 7247 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 7248 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x100a8 7249 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 7250 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x100a9 7251 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_BASE_IDX 5 7252 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x100a9 7253 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_BASE_IDX 5 7254 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x100b4 7255 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 7256 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x100b5 7257 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_BASE_IDX 5 7258 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x100b5 7259 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_BASE_IDX 5 7260 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x100bc 7261 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 7262 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x100bd 7263 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP_BASE_IDX 5 7264 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x100bd 7265 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL_BASE_IDX 5 7266 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x100be 7267 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0_BASE_IDX 5 7268 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x100bf 7269 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1_BASE_IDX 5 7270 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x100c0 7271 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0_BASE_IDX 5 7272 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x100c1 7273 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1_BASE_IDX 5 7274 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x100c2 7275 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 7276 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x100c3 7277 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 7278 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x100c4 7279 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 7280 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x100c5 7281 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 7282 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x100c8 7283 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 7284 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x100c9 7285 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_BASE_IDX 5 7286 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x100ca 7287 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 7288 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x100cb 7289 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_BASE_IDX 5 7290 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x100cb 7291 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_BASE_IDX 5 7292 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc 7293 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 7294 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x100cd 7295 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_BASE_IDX 5 7296 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x100ce 7297 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_BASE_IDX 5 7298 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x100ce 7299 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_BASE_IDX 5 7300 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x100cf 7301 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 7302 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x100cf 7303 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 7304 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x100d0 7305 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 7306 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 7307 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 7308 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 7309 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 7310 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x100d1 7311 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 7312 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 7313 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 7314 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 7315 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 7316 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 7317 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 7318 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 7319 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 7320 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 7321 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 7322 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 7323 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 7324 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 7325 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 7326 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 7327 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 7328 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da 7329 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 7330 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db 7331 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 7332 #define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x10100 7333 #define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 7334 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x10101 7335 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 7336 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x10102 7337 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 7338 #define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 7339 #define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 7340 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x10105 7341 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_BASE_IDX 5 7342 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x10106 7343 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_BASE_IDX 5 7344 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x10107 7345 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_BASE_IDX 5 7346 #define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 7347 #define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 7348 #define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 7349 #define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 7350 #define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a 7351 #define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 7352 #define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c 7353 #define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7354 #define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c 7355 #define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7356 #define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c 7357 #define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7358 #define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c 7359 #define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7360 #define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d 7361 #define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7362 #define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d 7363 #define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7364 #define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d 7365 #define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7366 #define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d 7367 #define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7368 #define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e 7369 #define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7370 #define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e 7371 #define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7372 #define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e 7373 #define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7374 #define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e 7375 #define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7376 #define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f 7377 #define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7378 #define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f 7379 #define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7380 #define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f 7381 #define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7382 #define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f 7383 #define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 7384 #define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 7385 #define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 7386 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x10115 7387 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_BASE_IDX 5 7388 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x10115 7389 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_BASE_IDX 5 7390 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x10116 7391 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 7392 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x10116 7393 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 7394 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x10117 7395 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 7396 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x10117 7397 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 7398 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x10118 7399 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 7400 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x10118 7401 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 7402 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x10119 7403 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 7404 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x10119 7405 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 7406 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x1011a 7407 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 7408 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x1011a 7409 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 7410 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x1011b 7411 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 7412 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x1011b 7413 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 7414 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x1011c 7415 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 7416 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x1011c 7417 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 7418 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x1011d 7419 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 7420 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x1011d 7421 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 7422 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x1011e 7423 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 7424 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x1011e 7425 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 7426 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x1011f 7427 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 7428 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x1011f 7429 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 7430 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x10120 7431 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 7432 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x10120 7433 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 7434 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x10121 7435 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 7436 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x10121 7437 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 7438 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x10122 7439 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 7440 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x10122 7441 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 7442 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x10123 7443 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 7444 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x10123 7445 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 7446 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x10124 7447 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 7448 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x10124 7449 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 7450 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x10125 7451 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 7452 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x10125 7453 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 7454 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10130 7455 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 7456 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 0x10131 7457 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 7458 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 0x10132 7459 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 7460 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 0x10133 7461 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 7462 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 0x10134 7463 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 7464 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 0x10135 7465 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 7466 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 0x10136 7467 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 7468 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 0x10137 7469 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 7470 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 0x10138 7471 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 7472 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 0x10139 7473 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 7474 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 0x1013a 7475 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 7476 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 0x1013b 7477 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 7478 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 0x1013c 7479 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 7480 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x10141 7481 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT_BASE_IDX 5 7482 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x10142 7483 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT_BASE_IDX 5 7484 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x10143 7485 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT_BASE_IDX 5 7486 7487 7488 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 7489 // base address: 0x10160000 7490 #define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x18000 7491 #define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX 5 7492 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x18000 7493 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX 5 7494 #define regBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x18001 7495 #define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX 5 7496 #define regBIF_CFG_DEV0_EPF0_VF0_STATUS 0x18001 7497 #define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX 5 7498 #define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x18002 7499 #define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX 5 7500 #define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x18002 7501 #define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX 5 7502 #define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x18002 7503 #define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX 5 7504 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x18002 7505 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX 5 7506 #define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x18003 7507 #define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX 5 7508 #define regBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x18003 7509 #define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX 5 7510 #define regBIF_CFG_DEV0_EPF0_VF0_HEADER 0x18003 7511 #define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX 5 7512 #define regBIF_CFG_DEV0_EPF0_VF0_BIST 0x18003 7513 #define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX 5 7514 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x18004 7515 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX 5 7516 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x18005 7517 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX 5 7518 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x18006 7519 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX 5 7520 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x18007 7521 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX 5 7522 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x18008 7523 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX 5 7524 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x18009 7525 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX 5 7526 #define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x1800a 7527 #define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX 5 7528 #define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x1800b 7529 #define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX 5 7530 #define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x1800c 7531 #define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX 5 7532 #define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x1800d 7533 #define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX 5 7534 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x1800f 7535 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX 5 7536 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x1800f 7537 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX 5 7538 #define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x1800f 7539 #define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX 5 7540 #define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x1800f 7541 #define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX 5 7542 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x18019 7543 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX 5 7544 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x18019 7545 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX 5 7546 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x1801a 7547 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX 5 7548 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x1801b 7549 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX 5 7550 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x1801b 7551 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX 5 7552 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x1801c 7553 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX 5 7554 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x1801d 7555 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX 5 7556 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x1801d 7557 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX 5 7558 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x18022 7559 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX 5 7560 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x18023 7561 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX 5 7562 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x18023 7563 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX 5 7564 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x18024 7565 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX 5 7566 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x18025 7567 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX 5 7568 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x18025 7569 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX 5 7570 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x18028 7571 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX 5 7572 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x18028 7573 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX 5 7574 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x18029 7575 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5 7576 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x1802a 7577 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5 7578 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x1802a 7579 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX 5 7580 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x1802a 7581 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5 7582 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x1802b 7583 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX 5 7584 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x1802b 7585 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX 5 7586 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x1802b 7587 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 7588 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x1802c 7589 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX 5 7590 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x1802c 7591 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX 5 7592 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x1802d 7593 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX 5 7594 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x18030 7595 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX 5 7596 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x18030 7597 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX 5 7598 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x18031 7599 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX 5 7600 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x18032 7601 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX 5 7602 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18040 7603 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 7604 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x18041 7605 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 7606 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x18042 7607 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 7608 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x18043 7609 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 7610 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18054 7611 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 7612 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x18055 7613 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 7614 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x18056 7615 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 7616 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x18057 7617 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 7618 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x18058 7619 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 7620 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x18059 7621 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 7622 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x1805a 7623 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 7624 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x1805b 7625 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX 5 7626 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x1805c 7627 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX 5 7628 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x1805d 7629 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX 5 7630 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x1805e 7631 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX 5 7632 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x18062 7633 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 7634 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x18063 7635 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 7636 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x18064 7637 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 7638 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x18065 7639 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 7640 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x180ca 7641 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 7642 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x180cb 7643 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX 5 7644 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x180cb 7645 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX 5 7646 7647 7648 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 7649 // base address: 0x10161000 7650 #define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x18400 7651 #define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX 5 7652 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x18400 7653 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX 5 7654 #define regBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x18401 7655 #define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX 5 7656 #define regBIF_CFG_DEV0_EPF0_VF1_STATUS 0x18401 7657 #define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX 5 7658 #define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x18402 7659 #define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX 5 7660 #define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x18402 7661 #define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX 5 7662 #define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x18402 7663 #define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX 5 7664 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x18402 7665 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX 5 7666 #define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x18403 7667 #define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX 5 7668 #define regBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x18403 7669 #define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX 5 7670 #define regBIF_CFG_DEV0_EPF0_VF1_HEADER 0x18403 7671 #define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX 5 7672 #define regBIF_CFG_DEV0_EPF0_VF1_BIST 0x18403 7673 #define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX 5 7674 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x18404 7675 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX 5 7676 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x18405 7677 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX 5 7678 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x18406 7679 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX 5 7680 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x18407 7681 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX 5 7682 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x18408 7683 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX 5 7684 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x18409 7685 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX 5 7686 #define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x1840a 7687 #define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX 5 7688 #define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x1840b 7689 #define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX 5 7690 #define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x1840c 7691 #define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX 5 7692 #define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x1840d 7693 #define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX 5 7694 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x1840f 7695 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX 5 7696 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x1840f 7697 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX 5 7698 #define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x1840f 7699 #define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX 5 7700 #define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x1840f 7701 #define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX 5 7702 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x18419 7703 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX 5 7704 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x18419 7705 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX 5 7706 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x1841a 7707 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX 5 7708 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x1841b 7709 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX 5 7710 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x1841b 7711 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX 5 7712 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x1841c 7713 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX 5 7714 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x1841d 7715 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX 5 7716 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x1841d 7717 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX 5 7718 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x18422 7719 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX 5 7720 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x18423 7721 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX 5 7722 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x18423 7723 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX 5 7724 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x18424 7725 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX 5 7726 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x18425 7727 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX 5 7728 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x18425 7729 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX 5 7730 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x18428 7731 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX 5 7732 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x18428 7733 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX 5 7734 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x18429 7735 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX 5 7736 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x1842a 7737 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX 5 7738 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x1842a 7739 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX 5 7740 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x1842a 7741 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX 5 7742 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x1842b 7743 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX 5 7744 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x1842b 7745 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX 5 7746 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x1842b 7747 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 7748 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x1842c 7749 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX 5 7750 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x1842c 7751 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX 5 7752 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x1842d 7753 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX 5 7754 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x18430 7755 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX 5 7756 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x18430 7757 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX 5 7758 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x18431 7759 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX 5 7760 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x18432 7761 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX 5 7762 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18440 7763 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 7764 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x18441 7765 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 7766 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x18442 7767 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 7768 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x18443 7769 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 7770 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18454 7771 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 7772 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x18455 7773 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 7774 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x18456 7775 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 7776 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x18457 7777 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 7778 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x18458 7779 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 7780 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x18459 7781 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 7782 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x1845a 7783 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 7784 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x1845b 7785 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX 5 7786 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x1845c 7787 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX 5 7788 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x1845d 7789 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX 5 7790 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x1845e 7791 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX 5 7792 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x18462 7793 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 7794 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x18463 7795 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 7796 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x18464 7797 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 7798 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x18465 7799 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 7800 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x184ca 7801 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 7802 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x184cb 7803 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX 5 7804 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x184cb 7805 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX 5 7806 7807 7808 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 7809 // base address: 0x10162000 7810 #define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x18800 7811 #define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX 5 7812 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x18800 7813 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX 5 7814 #define regBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x18801 7815 #define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX 5 7816 #define regBIF_CFG_DEV0_EPF0_VF2_STATUS 0x18801 7817 #define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX 5 7818 #define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x18802 7819 #define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX 5 7820 #define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x18802 7821 #define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX 5 7822 #define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x18802 7823 #define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX 5 7824 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x18802 7825 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX 5 7826 #define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x18803 7827 #define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX 5 7828 #define regBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x18803 7829 #define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX 5 7830 #define regBIF_CFG_DEV0_EPF0_VF2_HEADER 0x18803 7831 #define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX 5 7832 #define regBIF_CFG_DEV0_EPF0_VF2_BIST 0x18803 7833 #define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX 5 7834 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x18804 7835 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX 5 7836 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x18805 7837 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX 5 7838 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x18806 7839 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX 5 7840 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x18807 7841 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX 5 7842 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x18808 7843 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX 5 7844 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x18809 7845 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX 5 7846 #define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x1880a 7847 #define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX 5 7848 #define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x1880b 7849 #define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX 5 7850 #define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x1880c 7851 #define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX 5 7852 #define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x1880d 7853 #define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX 5 7854 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x1880f 7855 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX 5 7856 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x1880f 7857 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX 5 7858 #define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x1880f 7859 #define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX 5 7860 #define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x1880f 7861 #define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX 5 7862 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x18819 7863 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX 5 7864 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x18819 7865 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX 5 7866 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x1881a 7867 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX 5 7868 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x1881b 7869 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX 5 7870 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x1881b 7871 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX 5 7872 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x1881c 7873 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX 5 7874 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x1881d 7875 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX 5 7876 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x1881d 7877 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX 5 7878 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x18822 7879 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX 5 7880 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x18823 7881 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX 5 7882 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x18823 7883 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX 5 7884 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x18824 7885 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX 5 7886 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x18825 7887 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX 5 7888 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x18825 7889 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX 5 7890 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x18828 7891 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX 5 7892 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x18828 7893 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX 5 7894 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x18829 7895 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX 5 7896 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x1882a 7897 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX 5 7898 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x1882a 7899 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX 5 7900 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x1882a 7901 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX 5 7902 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x1882b 7903 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX 5 7904 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x1882b 7905 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX 5 7906 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x1882b 7907 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 7908 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x1882c 7909 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX 5 7910 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x1882c 7911 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX 5 7912 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x1882d 7913 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX 5 7914 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x18830 7915 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX 5 7916 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x18830 7917 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX 5 7918 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x18831 7919 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX 5 7920 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x18832 7921 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX 5 7922 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18840 7923 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 7924 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x18841 7925 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 7926 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x18842 7927 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 7928 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x18843 7929 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 7930 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18854 7931 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 7932 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x18855 7933 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 7934 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x18856 7935 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 7936 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x18857 7937 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 7938 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x18858 7939 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 7940 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x18859 7941 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 7942 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x1885a 7943 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 7944 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x1885b 7945 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX 5 7946 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x1885c 7947 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX 5 7948 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x1885d 7949 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX 5 7950 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x1885e 7951 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX 5 7952 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x18862 7953 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 7954 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x18863 7955 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 7956 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x18864 7957 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 7958 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x18865 7959 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 7960 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x188ca 7961 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 7962 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x188cb 7963 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX 5 7964 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x188cb 7965 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX 5 7966 7967 7968 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 7969 // base address: 0x10163000 7970 #define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x18c00 7971 #define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX 5 7972 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x18c00 7973 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX 5 7974 #define regBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x18c01 7975 #define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX 5 7976 #define regBIF_CFG_DEV0_EPF0_VF3_STATUS 0x18c01 7977 #define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX 5 7978 #define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x18c02 7979 #define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX 5 7980 #define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x18c02 7981 #define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX 5 7982 #define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x18c02 7983 #define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX 5 7984 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x18c02 7985 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX 5 7986 #define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x18c03 7987 #define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX 5 7988 #define regBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x18c03 7989 #define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX 5 7990 #define regBIF_CFG_DEV0_EPF0_VF3_HEADER 0x18c03 7991 #define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX 5 7992 #define regBIF_CFG_DEV0_EPF0_VF3_BIST 0x18c03 7993 #define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX 5 7994 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x18c04 7995 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX 5 7996 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x18c05 7997 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX 5 7998 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x18c06 7999 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX 5 8000 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x18c07 8001 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX 5 8002 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x18c08 8003 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX 5 8004 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x18c09 8005 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX 5 8006 #define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x18c0a 8007 #define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX 5 8008 #define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x18c0b 8009 #define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX 5 8010 #define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x18c0c 8011 #define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX 5 8012 #define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x18c0d 8013 #define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX 5 8014 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x18c0f 8015 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX 5 8016 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x18c0f 8017 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX 5 8018 #define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x18c0f 8019 #define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX 5 8020 #define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x18c0f 8021 #define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX 5 8022 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x18c19 8023 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX 5 8024 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x18c19 8025 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX 5 8026 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x18c1a 8027 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX 5 8028 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x18c1b 8029 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX 5 8030 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x18c1b 8031 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX 5 8032 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x18c1c 8033 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX 5 8034 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x18c1d 8035 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX 5 8036 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x18c1d 8037 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX 5 8038 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x18c22 8039 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX 5 8040 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x18c23 8041 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX 5 8042 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x18c23 8043 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX 5 8044 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x18c24 8045 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX 5 8046 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x18c25 8047 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX 5 8048 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x18c25 8049 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX 5 8050 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x18c28 8051 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX 5 8052 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x18c28 8053 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX 5 8054 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x18c29 8055 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX 5 8056 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x18c2a 8057 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX 5 8058 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x18c2a 8059 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX 5 8060 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x18c2a 8061 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX 5 8062 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x18c2b 8063 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX 5 8064 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x18c2b 8065 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX 5 8066 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x18c2b 8067 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 8068 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x18c2c 8069 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX 5 8070 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x18c2c 8071 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX 5 8072 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x18c2d 8073 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX 5 8074 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x18c30 8075 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX 5 8076 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x18c30 8077 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX 5 8078 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x18c31 8079 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX 5 8080 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x18c32 8081 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX 5 8082 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18c40 8083 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 8084 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x18c41 8085 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 8086 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x18c42 8087 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 8088 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x18c43 8089 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 8090 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18c54 8091 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 8092 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x18c55 8093 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 8094 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x18c56 8095 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 8096 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x18c57 8097 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 8098 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x18c58 8099 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 8100 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x18c59 8101 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 8102 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x18c5a 8103 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 8104 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x18c5b 8105 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX 5 8106 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x18c5c 8107 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX 5 8108 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x18c5d 8109 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX 5 8110 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x18c5e 8111 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX 5 8112 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x18c62 8113 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 8114 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x18c63 8115 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 8116 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x18c64 8117 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 8118 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x18c65 8119 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 8120 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x18cca 8121 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 8122 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x18ccb 8123 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX 5 8124 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x18ccb 8125 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX 5 8126 8127 8128 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 8129 // base address: 0x10164000 8130 #define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x19000 8131 #define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX 5 8132 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x19000 8133 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX 5 8134 #define regBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x19001 8135 #define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX 5 8136 #define regBIF_CFG_DEV0_EPF0_VF4_STATUS 0x19001 8137 #define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX 5 8138 #define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x19002 8139 #define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX 5 8140 #define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x19002 8141 #define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX 5 8142 #define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x19002 8143 #define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX 5 8144 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x19002 8145 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX 5 8146 #define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x19003 8147 #define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX 5 8148 #define regBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x19003 8149 #define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX 5 8150 #define regBIF_CFG_DEV0_EPF0_VF4_HEADER 0x19003 8151 #define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX 5 8152 #define regBIF_CFG_DEV0_EPF0_VF4_BIST 0x19003 8153 #define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX 5 8154 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x19004 8155 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX 5 8156 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x19005 8157 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX 5 8158 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x19006 8159 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX 5 8160 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x19007 8161 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX 5 8162 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x19008 8163 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX 5 8164 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x19009 8165 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX 5 8166 #define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x1900a 8167 #define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX 5 8168 #define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x1900b 8169 #define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX 5 8170 #define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x1900c 8171 #define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX 5 8172 #define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x1900d 8173 #define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX 5 8174 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x1900f 8175 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX 5 8176 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x1900f 8177 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX 5 8178 #define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x1900f 8179 #define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX 5 8180 #define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x1900f 8181 #define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX 5 8182 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x19019 8183 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX 5 8184 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x19019 8185 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX 5 8186 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x1901a 8187 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX 5 8188 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x1901b 8189 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX 5 8190 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x1901b 8191 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX 5 8192 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x1901c 8193 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX 5 8194 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x1901d 8195 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX 5 8196 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x1901d 8197 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX 5 8198 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x19022 8199 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX 5 8200 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x19023 8201 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX 5 8202 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x19023 8203 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX 5 8204 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x19024 8205 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX 5 8206 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x19025 8207 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX 5 8208 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x19025 8209 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX 5 8210 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x19028 8211 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX 5 8212 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x19028 8213 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX 5 8214 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x19029 8215 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX 5 8216 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x1902a 8217 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX 5 8218 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x1902a 8219 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX 5 8220 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x1902a 8221 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX 5 8222 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x1902b 8223 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX 5 8224 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x1902b 8225 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX 5 8226 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x1902b 8227 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX 5 8228 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x1902c 8229 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX 5 8230 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x1902c 8231 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX 5 8232 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x1902d 8233 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX 5 8234 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x19030 8235 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX 5 8236 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x19030 8237 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX 5 8238 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x19031 8239 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX 5 8240 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x19032 8241 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX 5 8242 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19040 8243 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 8244 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x19041 8245 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 8246 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x19042 8247 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 8248 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x19043 8249 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 8250 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19054 8251 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 8252 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x19055 8253 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 8254 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x19056 8255 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 8256 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x19057 8257 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 8258 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x19058 8259 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX 5 8260 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x19059 8261 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX 5 8262 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x1905a 8263 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 8264 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x1905b 8265 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX 5 8266 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x1905c 8267 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX 5 8268 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x1905d 8269 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX 5 8270 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x1905e 8271 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX 5 8272 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x19062 8273 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 8274 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x19063 8275 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 8276 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x19064 8277 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 8278 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x19065 8279 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 8280 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x190ca 8281 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 8282 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x190cb 8283 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX 5 8284 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x190cb 8285 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX 5 8286 8287 8288 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 8289 // base address: 0x10165000 8290 #define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x19400 8291 #define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX 5 8292 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x19400 8293 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX 5 8294 #define regBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x19401 8295 #define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX 5 8296 #define regBIF_CFG_DEV0_EPF0_VF5_STATUS 0x19401 8297 #define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX 5 8298 #define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x19402 8299 #define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX 5 8300 #define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x19402 8301 #define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX 5 8302 #define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x19402 8303 #define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX 5 8304 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x19402 8305 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX 5 8306 #define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x19403 8307 #define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX 5 8308 #define regBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x19403 8309 #define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX 5 8310 #define regBIF_CFG_DEV0_EPF0_VF5_HEADER 0x19403 8311 #define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX 5 8312 #define regBIF_CFG_DEV0_EPF0_VF5_BIST 0x19403 8313 #define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX 5 8314 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x19404 8315 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX 5 8316 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x19405 8317 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX 5 8318 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x19406 8319 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX 5 8320 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x19407 8321 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX 5 8322 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x19408 8323 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX 5 8324 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x19409 8325 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX 5 8326 #define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x1940a 8327 #define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX 5 8328 #define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x1940b 8329 #define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX 5 8330 #define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x1940c 8331 #define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX 5 8332 #define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x1940d 8333 #define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX 5 8334 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x1940f 8335 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX 5 8336 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x1940f 8337 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX 5 8338 #define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x1940f 8339 #define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX 5 8340 #define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x1940f 8341 #define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX 5 8342 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x19419 8343 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX 5 8344 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x19419 8345 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX 5 8346 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x1941a 8347 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX 5 8348 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x1941b 8349 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX 5 8350 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x1941b 8351 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX 5 8352 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x1941c 8353 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX 5 8354 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x1941d 8355 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX 5 8356 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x1941d 8357 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX 5 8358 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x19422 8359 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX 5 8360 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x19423 8361 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX 5 8362 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x19423 8363 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX 5 8364 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x19424 8365 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX 5 8366 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x19425 8367 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX 5 8368 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x19425 8369 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX 5 8370 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x19428 8371 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX 5 8372 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x19428 8373 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX 5 8374 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x19429 8375 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX 5 8376 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x1942a 8377 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX 5 8378 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x1942a 8379 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX 5 8380 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x1942a 8381 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX 5 8382 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x1942b 8383 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX 5 8384 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x1942b 8385 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX 5 8386 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x1942b 8387 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX 5 8388 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x1942c 8389 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX 5 8390 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x1942c 8391 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX 5 8392 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x1942d 8393 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX 5 8394 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x19430 8395 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX 5 8396 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x19430 8397 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX 5 8398 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x19431 8399 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX 5 8400 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x19432 8401 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX 5 8402 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19440 8403 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 8404 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x19441 8405 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 8406 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x19442 8407 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 8408 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x19443 8409 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 8410 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19454 8411 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 8412 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x19455 8413 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 8414 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x19456 8415 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 8416 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x19457 8417 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 8418 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x19458 8419 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX 5 8420 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x19459 8421 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX 5 8422 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x1945a 8423 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 8424 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x1945b 8425 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX 5 8426 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x1945c 8427 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX 5 8428 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x1945d 8429 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX 5 8430 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x1945e 8431 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX 5 8432 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x19462 8433 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 8434 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x19463 8435 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 8436 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x19464 8437 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 8438 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x19465 8439 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 8440 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x194ca 8441 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 8442 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x194cb 8443 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX 5 8444 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x194cb 8445 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX 5 8446 8447 8448 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 8449 // base address: 0x10166000 8450 #define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x19800 8451 #define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX 5 8452 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x19800 8453 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX 5 8454 #define regBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x19801 8455 #define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX 5 8456 #define regBIF_CFG_DEV0_EPF0_VF6_STATUS 0x19801 8457 #define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX 5 8458 #define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x19802 8459 #define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX 5 8460 #define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x19802 8461 #define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX 5 8462 #define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x19802 8463 #define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX 5 8464 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x19802 8465 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX 5 8466 #define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x19803 8467 #define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX 5 8468 #define regBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x19803 8469 #define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX 5 8470 #define regBIF_CFG_DEV0_EPF0_VF6_HEADER 0x19803 8471 #define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX 5 8472 #define regBIF_CFG_DEV0_EPF0_VF6_BIST 0x19803 8473 #define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX 5 8474 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x19804 8475 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX 5 8476 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x19805 8477 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX 5 8478 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x19806 8479 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX 5 8480 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x19807 8481 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX 5 8482 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x19808 8483 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX 5 8484 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x19809 8485 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX 5 8486 #define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x1980a 8487 #define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX 5 8488 #define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x1980b 8489 #define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX 5 8490 #define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x1980c 8491 #define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX 5 8492 #define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x1980d 8493 #define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX 5 8494 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x1980f 8495 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX 5 8496 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x1980f 8497 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX 5 8498 #define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x1980f 8499 #define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX 5 8500 #define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x1980f 8501 #define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX 5 8502 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x19819 8503 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX 5 8504 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x19819 8505 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX 5 8506 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x1981a 8507 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX 5 8508 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x1981b 8509 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX 5 8510 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x1981b 8511 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX 5 8512 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x1981c 8513 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX 5 8514 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x1981d 8515 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX 5 8516 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x1981d 8517 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX 5 8518 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x19822 8519 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX 5 8520 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x19823 8521 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX 5 8522 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x19823 8523 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX 5 8524 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x19824 8525 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX 5 8526 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x19825 8527 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX 5 8528 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x19825 8529 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX 5 8530 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x19828 8531 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX 5 8532 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x19828 8533 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX 5 8534 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x19829 8535 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX 5 8536 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x1982a 8537 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX 5 8538 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x1982a 8539 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX 5 8540 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x1982a 8541 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX 5 8542 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x1982b 8543 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX 5 8544 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x1982b 8545 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX 5 8546 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x1982b 8547 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX 5 8548 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x1982c 8549 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX 5 8550 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x1982c 8551 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX 5 8552 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x1982d 8553 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX 5 8554 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x19830 8555 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX 5 8556 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x19830 8557 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX 5 8558 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x19831 8559 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX 5 8560 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x19832 8561 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX 5 8562 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19840 8563 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 8564 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x19841 8565 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 8566 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x19842 8567 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 8568 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x19843 8569 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 8570 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19854 8571 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 8572 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x19855 8573 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 8574 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x19856 8575 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 8576 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x19857 8577 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 8578 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x19858 8579 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX 5 8580 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x19859 8581 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX 5 8582 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x1985a 8583 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 8584 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x1985b 8585 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX 5 8586 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x1985c 8587 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX 5 8588 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x1985d 8589 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX 5 8590 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x1985e 8591 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX 5 8592 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x19862 8593 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 8594 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x19863 8595 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 8596 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x19864 8597 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 8598 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x19865 8599 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 8600 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x198ca 8601 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 8602 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x198cb 8603 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX 5 8604 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x198cb 8605 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX 5 8606 8607 8608 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 8609 // base address: 0x10167000 8610 #define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x19c00 8611 #define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX 5 8612 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x19c00 8613 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX 5 8614 #define regBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x19c01 8615 #define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX 5 8616 #define regBIF_CFG_DEV0_EPF0_VF7_STATUS 0x19c01 8617 #define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX 5 8618 #define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x19c02 8619 #define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX 5 8620 #define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x19c02 8621 #define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX 5 8622 #define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x19c02 8623 #define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX 5 8624 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x19c02 8625 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX 5 8626 #define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x19c03 8627 #define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX 5 8628 #define regBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x19c03 8629 #define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX 5 8630 #define regBIF_CFG_DEV0_EPF0_VF7_HEADER 0x19c03 8631 #define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX 5 8632 #define regBIF_CFG_DEV0_EPF0_VF7_BIST 0x19c03 8633 #define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX 5 8634 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x19c04 8635 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX 5 8636 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x19c05 8637 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX 5 8638 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x19c06 8639 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX 5 8640 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x19c07 8641 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX 5 8642 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x19c08 8643 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX 5 8644 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x19c09 8645 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX 5 8646 #define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x19c0a 8647 #define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX 5 8648 #define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x19c0b 8649 #define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX 5 8650 #define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x19c0c 8651 #define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX 5 8652 #define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x19c0d 8653 #define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX 5 8654 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x19c0f 8655 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX 5 8656 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x19c0f 8657 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX 5 8658 #define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x19c0f 8659 #define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX 5 8660 #define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x19c0f 8661 #define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX 5 8662 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x19c19 8663 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX 5 8664 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x19c19 8665 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX 5 8666 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x19c1a 8667 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX 5 8668 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x19c1b 8669 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX 5 8670 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x19c1b 8671 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX 5 8672 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x19c1c 8673 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX 5 8674 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x19c1d 8675 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX 5 8676 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x19c1d 8677 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX 5 8678 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x19c22 8679 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX 5 8680 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x19c23 8681 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX 5 8682 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x19c23 8683 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX 5 8684 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x19c24 8685 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX 5 8686 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x19c25 8687 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX 5 8688 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x19c25 8689 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX 5 8690 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x19c28 8691 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX 5 8692 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x19c28 8693 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX 5 8694 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x19c29 8695 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX 5 8696 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x19c2a 8697 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX 5 8698 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x19c2a 8699 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX 5 8700 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x19c2a 8701 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX 5 8702 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x19c2b 8703 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX 5 8704 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x19c2b 8705 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX 5 8706 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x19c2b 8707 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX 5 8708 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x19c2c 8709 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX 5 8710 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x19c2c 8711 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX 5 8712 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x19c2d 8713 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX 5 8714 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x19c30 8715 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX 5 8716 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x19c30 8717 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX 5 8718 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x19c31 8719 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX 5 8720 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x19c32 8721 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX 5 8722 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19c40 8723 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 8724 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x19c41 8725 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 8726 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x19c42 8727 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 8728 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x19c43 8729 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 8730 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19c54 8731 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 8732 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x19c55 8733 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 8734 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x19c56 8735 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 8736 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x19c57 8737 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 8738 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x19c58 8739 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX 5 8740 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x19c59 8741 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX 5 8742 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x19c5a 8743 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 8744 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x19c5b 8745 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX 5 8746 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x19c5c 8747 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX 5 8748 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x19c5d 8749 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX 5 8750 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x19c5e 8751 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX 5 8752 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x19c62 8753 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 8754 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x19c63 8755 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 8756 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x19c64 8757 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 8758 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x19c65 8759 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 8760 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x19cca 8761 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 8762 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x19ccb 8763 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX 5 8764 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x19ccb 8765 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX 5 8766 8767 8768 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 8769 // base address: 0x10168000 8770 #define regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID 0x1a000 8771 #define regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID_BASE_IDX 5 8772 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID 0x1a000 8773 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID_BASE_IDX 5 8774 #define regBIF_CFG_DEV0_EPF0_VF8_COMMAND 0x1a001 8775 #define regBIF_CFG_DEV0_EPF0_VF8_COMMAND_BASE_IDX 5 8776 #define regBIF_CFG_DEV0_EPF0_VF8_STATUS 0x1a001 8777 #define regBIF_CFG_DEV0_EPF0_VF8_STATUS_BASE_IDX 5 8778 #define regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID 0x1a002 8779 #define regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID_BASE_IDX 5 8780 #define regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE 0x1a002 8781 #define regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE_BASE_IDX 5 8782 #define regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS 0x1a002 8783 #define regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS_BASE_IDX 5 8784 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS 0x1a002 8785 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS_BASE_IDX 5 8786 #define regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE 0x1a003 8787 #define regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE_BASE_IDX 5 8788 #define regBIF_CFG_DEV0_EPF0_VF8_LATENCY 0x1a003 8789 #define regBIF_CFG_DEV0_EPF0_VF8_LATENCY_BASE_IDX 5 8790 #define regBIF_CFG_DEV0_EPF0_VF8_HEADER 0x1a003 8791 #define regBIF_CFG_DEV0_EPF0_VF8_HEADER_BASE_IDX 5 8792 #define regBIF_CFG_DEV0_EPF0_VF8_BIST 0x1a003 8793 #define regBIF_CFG_DEV0_EPF0_VF8_BIST_BASE_IDX 5 8794 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1 0x1a004 8795 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1_BASE_IDX 5 8796 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2 0x1a005 8797 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2_BASE_IDX 5 8798 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3 0x1a006 8799 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3_BASE_IDX 5 8800 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4 0x1a007 8801 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4_BASE_IDX 5 8802 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5 0x1a008 8803 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5_BASE_IDX 5 8804 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6 0x1a009 8805 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6_BASE_IDX 5 8806 #define regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR 0x1a00a 8807 #define regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR_BASE_IDX 5 8808 #define regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID 0x1a00b 8809 #define regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID_BASE_IDX 5 8810 #define regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR 0x1a00c 8811 #define regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR_BASE_IDX 5 8812 #define regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR 0x1a00d 8813 #define regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR_BASE_IDX 5 8814 #define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE 0x1a00f 8815 #define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE_BASE_IDX 5 8816 #define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN 0x1a00f 8817 #define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN_BASE_IDX 5 8818 #define regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT 0x1a00f 8819 #define regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT_BASE_IDX 5 8820 #define regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY 0x1a00f 8821 #define regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY_BASE_IDX 5 8822 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST 0x1a019 8823 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST_BASE_IDX 5 8824 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP 0x1a019 8825 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_BASE_IDX 5 8826 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP 0x1a01a 8827 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP_BASE_IDX 5 8828 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL 0x1a01b 8829 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL_BASE_IDX 5 8830 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS 0x1a01b 8831 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS_BASE_IDX 5 8832 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP 0x1a01c 8833 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP_BASE_IDX 5 8834 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL 0x1a01d 8835 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL_BASE_IDX 5 8836 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS 0x1a01d 8837 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS_BASE_IDX 5 8838 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2 0x1a022 8839 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2_BASE_IDX 5 8840 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2 0x1a023 8841 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2_BASE_IDX 5 8842 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2 0x1a023 8843 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2_BASE_IDX 5 8844 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2 0x1a024 8845 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2_BASE_IDX 5 8846 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2 0x1a025 8847 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2_BASE_IDX 5 8848 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2 0x1a025 8849 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2_BASE_IDX 5 8850 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST 0x1a028 8851 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST_BASE_IDX 5 8852 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL 0x1a028 8853 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL_BASE_IDX 5 8854 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO 0x1a029 8855 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO_BASE_IDX 5 8856 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI 0x1a02a 8857 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI_BASE_IDX 5 8858 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA 0x1a02a 8859 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_BASE_IDX 5 8860 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA 0x1a02a 8861 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_BASE_IDX 5 8862 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK 0x1a02b 8863 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_BASE_IDX 5 8864 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64 0x1a02b 8865 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64_BASE_IDX 5 8866 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64 0x1a02b 8867 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64_BASE_IDX 5 8868 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64 0x1a02c 8869 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64_BASE_IDX 5 8870 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING 0x1a02c 8871 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_BASE_IDX 5 8872 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64 0x1a02d 8873 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64_BASE_IDX 5 8874 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST 0x1a030 8875 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST_BASE_IDX 5 8876 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL 0x1a030 8877 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL_BASE_IDX 5 8878 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE 0x1a031 8879 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE_BASE_IDX 5 8880 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA 0x1a032 8881 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA_BASE_IDX 5 8882 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a040 8883 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 8884 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR 0x1a041 8885 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 8886 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1 0x1a042 8887 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 8888 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2 0x1a043 8889 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 8890 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a054 8891 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 8892 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS 0x1a055 8893 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 8894 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK 0x1a056 8895 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 8896 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY 0x1a057 8897 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 8898 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS 0x1a058 8899 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS_BASE_IDX 5 8900 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK 0x1a059 8901 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK_BASE_IDX 5 8902 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL 0x1a05a 8903 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 8904 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0 0x1a05b 8905 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0_BASE_IDX 5 8906 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1 0x1a05c 8907 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1_BASE_IDX 5 8908 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2 0x1a05d 8909 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2_BASE_IDX 5 8910 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3 0x1a05e 8911 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3_BASE_IDX 5 8912 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0 0x1a062 8913 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 8914 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1 0x1a063 8915 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 8916 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2 0x1a064 8917 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 8918 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3 0x1a065 8919 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 8920 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST 0x1a0ca 8921 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 8922 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP 0x1a0cb 8923 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP_BASE_IDX 5 8924 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL 0x1a0cb 8925 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL_BASE_IDX 5 8926 8927 8928 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 8929 // base address: 0x10169000 8930 #define regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID 0x1a400 8931 #define regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID_BASE_IDX 5 8932 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID 0x1a400 8933 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID_BASE_IDX 5 8934 #define regBIF_CFG_DEV0_EPF0_VF9_COMMAND 0x1a401 8935 #define regBIF_CFG_DEV0_EPF0_VF9_COMMAND_BASE_IDX 5 8936 #define regBIF_CFG_DEV0_EPF0_VF9_STATUS 0x1a401 8937 #define regBIF_CFG_DEV0_EPF0_VF9_STATUS_BASE_IDX 5 8938 #define regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID 0x1a402 8939 #define regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID_BASE_IDX 5 8940 #define regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE 0x1a402 8941 #define regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE_BASE_IDX 5 8942 #define regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS 0x1a402 8943 #define regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS_BASE_IDX 5 8944 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS 0x1a402 8945 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS_BASE_IDX 5 8946 #define regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE 0x1a403 8947 #define regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE_BASE_IDX 5 8948 #define regBIF_CFG_DEV0_EPF0_VF9_LATENCY 0x1a403 8949 #define regBIF_CFG_DEV0_EPF0_VF9_LATENCY_BASE_IDX 5 8950 #define regBIF_CFG_DEV0_EPF0_VF9_HEADER 0x1a403 8951 #define regBIF_CFG_DEV0_EPF0_VF9_HEADER_BASE_IDX 5 8952 #define regBIF_CFG_DEV0_EPF0_VF9_BIST 0x1a403 8953 #define regBIF_CFG_DEV0_EPF0_VF9_BIST_BASE_IDX 5 8954 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1 0x1a404 8955 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1_BASE_IDX 5 8956 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2 0x1a405 8957 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2_BASE_IDX 5 8958 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3 0x1a406 8959 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3_BASE_IDX 5 8960 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4 0x1a407 8961 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4_BASE_IDX 5 8962 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5 0x1a408 8963 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5_BASE_IDX 5 8964 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6 0x1a409 8965 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6_BASE_IDX 5 8966 #define regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR 0x1a40a 8967 #define regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR_BASE_IDX 5 8968 #define regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID 0x1a40b 8969 #define regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID_BASE_IDX 5 8970 #define regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR 0x1a40c 8971 #define regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR_BASE_IDX 5 8972 #define regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR 0x1a40d 8973 #define regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR_BASE_IDX 5 8974 #define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE 0x1a40f 8975 #define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE_BASE_IDX 5 8976 #define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN 0x1a40f 8977 #define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN_BASE_IDX 5 8978 #define regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT 0x1a40f 8979 #define regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT_BASE_IDX 5 8980 #define regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY 0x1a40f 8981 #define regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY_BASE_IDX 5 8982 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST 0x1a419 8983 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST_BASE_IDX 5 8984 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP 0x1a419 8985 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_BASE_IDX 5 8986 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP 0x1a41a 8987 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP_BASE_IDX 5 8988 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL 0x1a41b 8989 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL_BASE_IDX 5 8990 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS 0x1a41b 8991 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS_BASE_IDX 5 8992 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP 0x1a41c 8993 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP_BASE_IDX 5 8994 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL 0x1a41d 8995 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL_BASE_IDX 5 8996 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS 0x1a41d 8997 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS_BASE_IDX 5 8998 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2 0x1a422 8999 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2_BASE_IDX 5 9000 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2 0x1a423 9001 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2_BASE_IDX 5 9002 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2 0x1a423 9003 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2_BASE_IDX 5 9004 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2 0x1a424 9005 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2_BASE_IDX 5 9006 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2 0x1a425 9007 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2_BASE_IDX 5 9008 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2 0x1a425 9009 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2_BASE_IDX 5 9010 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST 0x1a428 9011 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST_BASE_IDX 5 9012 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL 0x1a428 9013 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL_BASE_IDX 5 9014 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO 0x1a429 9015 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO_BASE_IDX 5 9016 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI 0x1a42a 9017 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI_BASE_IDX 5 9018 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA 0x1a42a 9019 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_BASE_IDX 5 9020 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA 0x1a42a 9021 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_BASE_IDX 5 9022 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK 0x1a42b 9023 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_BASE_IDX 5 9024 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64 0x1a42b 9025 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64_BASE_IDX 5 9026 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64 0x1a42b 9027 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64_BASE_IDX 5 9028 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64 0x1a42c 9029 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64_BASE_IDX 5 9030 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING 0x1a42c 9031 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_BASE_IDX 5 9032 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64 0x1a42d 9033 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64_BASE_IDX 5 9034 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST 0x1a430 9035 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST_BASE_IDX 5 9036 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL 0x1a430 9037 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL_BASE_IDX 5 9038 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE 0x1a431 9039 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE_BASE_IDX 5 9040 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA 0x1a432 9041 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA_BASE_IDX 5 9042 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a440 9043 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 9044 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR 0x1a441 9045 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 9046 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1 0x1a442 9047 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 9048 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2 0x1a443 9049 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 9050 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a454 9051 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 9052 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS 0x1a455 9053 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 9054 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK 0x1a456 9055 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 9056 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY 0x1a457 9057 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 9058 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS 0x1a458 9059 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS_BASE_IDX 5 9060 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK 0x1a459 9061 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK_BASE_IDX 5 9062 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL 0x1a45a 9063 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 9064 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0 0x1a45b 9065 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0_BASE_IDX 5 9066 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1 0x1a45c 9067 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1_BASE_IDX 5 9068 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2 0x1a45d 9069 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2_BASE_IDX 5 9070 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3 0x1a45e 9071 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3_BASE_IDX 5 9072 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0 0x1a462 9073 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 9074 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1 0x1a463 9075 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 9076 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2 0x1a464 9077 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 9078 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3 0x1a465 9079 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 9080 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST 0x1a4ca 9081 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 9082 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP 0x1a4cb 9083 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP_BASE_IDX 5 9084 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL 0x1a4cb 9085 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL_BASE_IDX 5 9086 9087 9088 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 9089 // base address: 0x1016a000 9090 #define regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID 0x1a800 9091 #define regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID_BASE_IDX 5 9092 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID 0x1a800 9093 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID_BASE_IDX 5 9094 #define regBIF_CFG_DEV0_EPF0_VF10_COMMAND 0x1a801 9095 #define regBIF_CFG_DEV0_EPF0_VF10_COMMAND_BASE_IDX 5 9096 #define regBIF_CFG_DEV0_EPF0_VF10_STATUS 0x1a801 9097 #define regBIF_CFG_DEV0_EPF0_VF10_STATUS_BASE_IDX 5 9098 #define regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID 0x1a802 9099 #define regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID_BASE_IDX 5 9100 #define regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE 0x1a802 9101 #define regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE_BASE_IDX 5 9102 #define regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS 0x1a802 9103 #define regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS_BASE_IDX 5 9104 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS 0x1a802 9105 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS_BASE_IDX 5 9106 #define regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE 0x1a803 9107 #define regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE_BASE_IDX 5 9108 #define regBIF_CFG_DEV0_EPF0_VF10_LATENCY 0x1a803 9109 #define regBIF_CFG_DEV0_EPF0_VF10_LATENCY_BASE_IDX 5 9110 #define regBIF_CFG_DEV0_EPF0_VF10_HEADER 0x1a803 9111 #define regBIF_CFG_DEV0_EPF0_VF10_HEADER_BASE_IDX 5 9112 #define regBIF_CFG_DEV0_EPF0_VF10_BIST 0x1a803 9113 #define regBIF_CFG_DEV0_EPF0_VF10_BIST_BASE_IDX 5 9114 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1 0x1a804 9115 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1_BASE_IDX 5 9116 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2 0x1a805 9117 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2_BASE_IDX 5 9118 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3 0x1a806 9119 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3_BASE_IDX 5 9120 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4 0x1a807 9121 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4_BASE_IDX 5 9122 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5 0x1a808 9123 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5_BASE_IDX 5 9124 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6 0x1a809 9125 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6_BASE_IDX 5 9126 #define regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR 0x1a80a 9127 #define regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR_BASE_IDX 5 9128 #define regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID 0x1a80b 9129 #define regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID_BASE_IDX 5 9130 #define regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR 0x1a80c 9131 #define regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR_BASE_IDX 5 9132 #define regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR 0x1a80d 9133 #define regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR_BASE_IDX 5 9134 #define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE 0x1a80f 9135 #define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE_BASE_IDX 5 9136 #define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN 0x1a80f 9137 #define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN_BASE_IDX 5 9138 #define regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT 0x1a80f 9139 #define regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT_BASE_IDX 5 9140 #define regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY 0x1a80f 9141 #define regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY_BASE_IDX 5 9142 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST 0x1a819 9143 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST_BASE_IDX 5 9144 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP 0x1a819 9145 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_BASE_IDX 5 9146 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP 0x1a81a 9147 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP_BASE_IDX 5 9148 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL 0x1a81b 9149 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL_BASE_IDX 5 9150 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS 0x1a81b 9151 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS_BASE_IDX 5 9152 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP 0x1a81c 9153 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP_BASE_IDX 5 9154 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL 0x1a81d 9155 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL_BASE_IDX 5 9156 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS 0x1a81d 9157 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS_BASE_IDX 5 9158 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2 0x1a822 9159 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2_BASE_IDX 5 9160 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2 0x1a823 9161 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2_BASE_IDX 5 9162 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2 0x1a823 9163 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2_BASE_IDX 5 9164 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2 0x1a824 9165 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2_BASE_IDX 5 9166 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2 0x1a825 9167 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2_BASE_IDX 5 9168 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2 0x1a825 9169 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2_BASE_IDX 5 9170 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST 0x1a828 9171 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST_BASE_IDX 5 9172 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL 0x1a828 9173 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL_BASE_IDX 5 9174 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO 0x1a829 9175 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO_BASE_IDX 5 9176 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI 0x1a82a 9177 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI_BASE_IDX 5 9178 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA 0x1a82a 9179 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_BASE_IDX 5 9180 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA 0x1a82a 9181 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_BASE_IDX 5 9182 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK 0x1a82b 9183 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_BASE_IDX 5 9184 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64 0x1a82b 9185 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64_BASE_IDX 5 9186 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64 0x1a82b 9187 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64_BASE_IDX 5 9188 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64 0x1a82c 9189 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64_BASE_IDX 5 9190 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING 0x1a82c 9191 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_BASE_IDX 5 9192 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64 0x1a82d 9193 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64_BASE_IDX 5 9194 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST 0x1a830 9195 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST_BASE_IDX 5 9196 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL 0x1a830 9197 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL_BASE_IDX 5 9198 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE 0x1a831 9199 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE_BASE_IDX 5 9200 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA 0x1a832 9201 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA_BASE_IDX 5 9202 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a840 9203 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 9204 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR 0x1a841 9205 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 9206 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1 0x1a842 9207 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 9208 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2 0x1a843 9209 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 9210 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a854 9211 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 9212 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS 0x1a855 9213 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 9214 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK 0x1a856 9215 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 9216 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY 0x1a857 9217 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 9218 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS 0x1a858 9219 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS_BASE_IDX 5 9220 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK 0x1a859 9221 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK_BASE_IDX 5 9222 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL 0x1a85a 9223 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 9224 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0 0x1a85b 9225 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0_BASE_IDX 5 9226 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1 0x1a85c 9227 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1_BASE_IDX 5 9228 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2 0x1a85d 9229 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2_BASE_IDX 5 9230 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3 0x1a85e 9231 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3_BASE_IDX 5 9232 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0 0x1a862 9233 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 9234 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1 0x1a863 9235 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 9236 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2 0x1a864 9237 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 9238 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3 0x1a865 9239 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 9240 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST 0x1a8ca 9241 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 9242 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP 0x1a8cb 9243 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP_BASE_IDX 5 9244 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL 0x1a8cb 9245 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL_BASE_IDX 5 9246 9247 9248 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 9249 // base address: 0x1016b000 9250 #define regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID 0x1ac00 9251 #define regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID_BASE_IDX 5 9252 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID 0x1ac00 9253 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID_BASE_IDX 5 9254 #define regBIF_CFG_DEV0_EPF0_VF11_COMMAND 0x1ac01 9255 #define regBIF_CFG_DEV0_EPF0_VF11_COMMAND_BASE_IDX 5 9256 #define regBIF_CFG_DEV0_EPF0_VF11_STATUS 0x1ac01 9257 #define regBIF_CFG_DEV0_EPF0_VF11_STATUS_BASE_IDX 5 9258 #define regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID 0x1ac02 9259 #define regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID_BASE_IDX 5 9260 #define regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE 0x1ac02 9261 #define regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE_BASE_IDX 5 9262 #define regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS 0x1ac02 9263 #define regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS_BASE_IDX 5 9264 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS 0x1ac02 9265 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS_BASE_IDX 5 9266 #define regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE 0x1ac03 9267 #define regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE_BASE_IDX 5 9268 #define regBIF_CFG_DEV0_EPF0_VF11_LATENCY 0x1ac03 9269 #define regBIF_CFG_DEV0_EPF0_VF11_LATENCY_BASE_IDX 5 9270 #define regBIF_CFG_DEV0_EPF0_VF11_HEADER 0x1ac03 9271 #define regBIF_CFG_DEV0_EPF0_VF11_HEADER_BASE_IDX 5 9272 #define regBIF_CFG_DEV0_EPF0_VF11_BIST 0x1ac03 9273 #define regBIF_CFG_DEV0_EPF0_VF11_BIST_BASE_IDX 5 9274 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1 0x1ac04 9275 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1_BASE_IDX 5 9276 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2 0x1ac05 9277 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2_BASE_IDX 5 9278 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3 0x1ac06 9279 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3_BASE_IDX 5 9280 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4 0x1ac07 9281 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4_BASE_IDX 5 9282 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5 0x1ac08 9283 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5_BASE_IDX 5 9284 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6 0x1ac09 9285 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6_BASE_IDX 5 9286 #define regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR 0x1ac0a 9287 #define regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR_BASE_IDX 5 9288 #define regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID 0x1ac0b 9289 #define regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID_BASE_IDX 5 9290 #define regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR 0x1ac0c 9291 #define regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR_BASE_IDX 5 9292 #define regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR 0x1ac0d 9293 #define regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR_BASE_IDX 5 9294 #define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE 0x1ac0f 9295 #define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE_BASE_IDX 5 9296 #define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN 0x1ac0f 9297 #define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN_BASE_IDX 5 9298 #define regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT 0x1ac0f 9299 #define regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT_BASE_IDX 5 9300 #define regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY 0x1ac0f 9301 #define regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY_BASE_IDX 5 9302 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST 0x1ac19 9303 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST_BASE_IDX 5 9304 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP 0x1ac19 9305 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_BASE_IDX 5 9306 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP 0x1ac1a 9307 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP_BASE_IDX 5 9308 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL 0x1ac1b 9309 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL_BASE_IDX 5 9310 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS 0x1ac1b 9311 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS_BASE_IDX 5 9312 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP 0x1ac1c 9313 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP_BASE_IDX 5 9314 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL 0x1ac1d 9315 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL_BASE_IDX 5 9316 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS 0x1ac1d 9317 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS_BASE_IDX 5 9318 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2 0x1ac22 9319 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2_BASE_IDX 5 9320 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2 0x1ac23 9321 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2_BASE_IDX 5 9322 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2 0x1ac23 9323 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2_BASE_IDX 5 9324 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2 0x1ac24 9325 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2_BASE_IDX 5 9326 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2 0x1ac25 9327 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2_BASE_IDX 5 9328 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2 0x1ac25 9329 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2_BASE_IDX 5 9330 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST 0x1ac28 9331 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST_BASE_IDX 5 9332 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL 0x1ac28 9333 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL_BASE_IDX 5 9334 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO 0x1ac29 9335 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO_BASE_IDX 5 9336 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI 0x1ac2a 9337 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI_BASE_IDX 5 9338 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA 0x1ac2a 9339 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_BASE_IDX 5 9340 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA 0x1ac2a 9341 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_BASE_IDX 5 9342 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK 0x1ac2b 9343 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_BASE_IDX 5 9344 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64 0x1ac2b 9345 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64_BASE_IDX 5 9346 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64 0x1ac2b 9347 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64_BASE_IDX 5 9348 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64 0x1ac2c 9349 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64_BASE_IDX 5 9350 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING 0x1ac2c 9351 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_BASE_IDX 5 9352 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64 0x1ac2d 9353 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64_BASE_IDX 5 9354 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST 0x1ac30 9355 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST_BASE_IDX 5 9356 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL 0x1ac30 9357 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL_BASE_IDX 5 9358 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE 0x1ac31 9359 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE_BASE_IDX 5 9360 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA 0x1ac32 9361 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA_BASE_IDX 5 9362 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1ac40 9363 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 9364 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR 0x1ac41 9365 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 9366 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1 0x1ac42 9367 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 9368 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2 0x1ac43 9369 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 9370 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1ac54 9371 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 9372 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS 0x1ac55 9373 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 9374 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK 0x1ac56 9375 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 9376 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY 0x1ac57 9377 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 9378 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS 0x1ac58 9379 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS_BASE_IDX 5 9380 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK 0x1ac59 9381 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK_BASE_IDX 5 9382 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL 0x1ac5a 9383 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 9384 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0 0x1ac5b 9385 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0_BASE_IDX 5 9386 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1 0x1ac5c 9387 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1_BASE_IDX 5 9388 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2 0x1ac5d 9389 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2_BASE_IDX 5 9390 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3 0x1ac5e 9391 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3_BASE_IDX 5 9392 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0 0x1ac62 9393 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 9394 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1 0x1ac63 9395 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 9396 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2 0x1ac64 9397 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 9398 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3 0x1ac65 9399 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 9400 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST 0x1acca 9401 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 9402 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP 0x1accb 9403 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP_BASE_IDX 5 9404 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL 0x1accb 9405 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL_BASE_IDX 5 9406 9407 9408 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 9409 // base address: 0x1016c000 9410 #define regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID 0x1b000 9411 #define regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID_BASE_IDX 5 9412 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID 0x1b000 9413 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID_BASE_IDX 5 9414 #define regBIF_CFG_DEV0_EPF0_VF12_COMMAND 0x1b001 9415 #define regBIF_CFG_DEV0_EPF0_VF12_COMMAND_BASE_IDX 5 9416 #define regBIF_CFG_DEV0_EPF0_VF12_STATUS 0x1b001 9417 #define regBIF_CFG_DEV0_EPF0_VF12_STATUS_BASE_IDX 5 9418 #define regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID 0x1b002 9419 #define regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID_BASE_IDX 5 9420 #define regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE 0x1b002 9421 #define regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE_BASE_IDX 5 9422 #define regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS 0x1b002 9423 #define regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS_BASE_IDX 5 9424 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS 0x1b002 9425 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS_BASE_IDX 5 9426 #define regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE 0x1b003 9427 #define regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE_BASE_IDX 5 9428 #define regBIF_CFG_DEV0_EPF0_VF12_LATENCY 0x1b003 9429 #define regBIF_CFG_DEV0_EPF0_VF12_LATENCY_BASE_IDX 5 9430 #define regBIF_CFG_DEV0_EPF0_VF12_HEADER 0x1b003 9431 #define regBIF_CFG_DEV0_EPF0_VF12_HEADER_BASE_IDX 5 9432 #define regBIF_CFG_DEV0_EPF0_VF12_BIST 0x1b003 9433 #define regBIF_CFG_DEV0_EPF0_VF12_BIST_BASE_IDX 5 9434 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1 0x1b004 9435 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1_BASE_IDX 5 9436 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2 0x1b005 9437 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2_BASE_IDX 5 9438 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3 0x1b006 9439 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3_BASE_IDX 5 9440 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4 0x1b007 9441 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4_BASE_IDX 5 9442 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5 0x1b008 9443 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5_BASE_IDX 5 9444 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6 0x1b009 9445 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6_BASE_IDX 5 9446 #define regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR 0x1b00a 9447 #define regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR_BASE_IDX 5 9448 #define regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID 0x1b00b 9449 #define regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID_BASE_IDX 5 9450 #define regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR 0x1b00c 9451 #define regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR_BASE_IDX 5 9452 #define regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR 0x1b00d 9453 #define regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR_BASE_IDX 5 9454 #define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE 0x1b00f 9455 #define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE_BASE_IDX 5 9456 #define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN 0x1b00f 9457 #define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN_BASE_IDX 5 9458 #define regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT 0x1b00f 9459 #define regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT_BASE_IDX 5 9460 #define regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY 0x1b00f 9461 #define regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY_BASE_IDX 5 9462 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST 0x1b019 9463 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST_BASE_IDX 5 9464 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP 0x1b019 9465 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_BASE_IDX 5 9466 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP 0x1b01a 9467 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP_BASE_IDX 5 9468 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL 0x1b01b 9469 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL_BASE_IDX 5 9470 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS 0x1b01b 9471 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS_BASE_IDX 5 9472 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP 0x1b01c 9473 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP_BASE_IDX 5 9474 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL 0x1b01d 9475 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL_BASE_IDX 5 9476 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS 0x1b01d 9477 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS_BASE_IDX 5 9478 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2 0x1b022 9479 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2_BASE_IDX 5 9480 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2 0x1b023 9481 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2_BASE_IDX 5 9482 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2 0x1b023 9483 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2_BASE_IDX 5 9484 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2 0x1b024 9485 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2_BASE_IDX 5 9486 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2 0x1b025 9487 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2_BASE_IDX 5 9488 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2 0x1b025 9489 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2_BASE_IDX 5 9490 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST 0x1b028 9491 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST_BASE_IDX 5 9492 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL 0x1b028 9493 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL_BASE_IDX 5 9494 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO 0x1b029 9495 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO_BASE_IDX 5 9496 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI 0x1b02a 9497 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI_BASE_IDX 5 9498 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA 0x1b02a 9499 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_BASE_IDX 5 9500 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA 0x1b02a 9501 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_BASE_IDX 5 9502 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK 0x1b02b 9503 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_BASE_IDX 5 9504 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64 0x1b02b 9505 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64_BASE_IDX 5 9506 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64 0x1b02b 9507 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64_BASE_IDX 5 9508 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64 0x1b02c 9509 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64_BASE_IDX 5 9510 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING 0x1b02c 9511 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_BASE_IDX 5 9512 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64 0x1b02d 9513 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64_BASE_IDX 5 9514 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST 0x1b030 9515 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST_BASE_IDX 5 9516 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL 0x1b030 9517 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL_BASE_IDX 5 9518 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE 0x1b031 9519 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE_BASE_IDX 5 9520 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA 0x1b032 9521 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA_BASE_IDX 5 9522 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b040 9523 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 9524 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR 0x1b041 9525 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 9526 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1 0x1b042 9527 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 9528 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2 0x1b043 9529 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 9530 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b054 9531 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 9532 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS 0x1b055 9533 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 9534 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK 0x1b056 9535 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 9536 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY 0x1b057 9537 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 9538 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS 0x1b058 9539 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS_BASE_IDX 5 9540 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK 0x1b059 9541 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK_BASE_IDX 5 9542 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL 0x1b05a 9543 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 9544 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0 0x1b05b 9545 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0_BASE_IDX 5 9546 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1 0x1b05c 9547 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1_BASE_IDX 5 9548 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2 0x1b05d 9549 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2_BASE_IDX 5 9550 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3 0x1b05e 9551 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3_BASE_IDX 5 9552 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0 0x1b062 9553 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 9554 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1 0x1b063 9555 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 9556 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2 0x1b064 9557 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 9558 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3 0x1b065 9559 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 9560 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST 0x1b0ca 9561 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 9562 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP 0x1b0cb 9563 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP_BASE_IDX 5 9564 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL 0x1b0cb 9565 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL_BASE_IDX 5 9566 9567 9568 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 9569 // base address: 0x1016d000 9570 #define regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID 0x1b400 9571 #define regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID_BASE_IDX 5 9572 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID 0x1b400 9573 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID_BASE_IDX 5 9574 #define regBIF_CFG_DEV0_EPF0_VF13_COMMAND 0x1b401 9575 #define regBIF_CFG_DEV0_EPF0_VF13_COMMAND_BASE_IDX 5 9576 #define regBIF_CFG_DEV0_EPF0_VF13_STATUS 0x1b401 9577 #define regBIF_CFG_DEV0_EPF0_VF13_STATUS_BASE_IDX 5 9578 #define regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID 0x1b402 9579 #define regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID_BASE_IDX 5 9580 #define regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE 0x1b402 9581 #define regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE_BASE_IDX 5 9582 #define regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS 0x1b402 9583 #define regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS_BASE_IDX 5 9584 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS 0x1b402 9585 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS_BASE_IDX 5 9586 #define regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE 0x1b403 9587 #define regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE_BASE_IDX 5 9588 #define regBIF_CFG_DEV0_EPF0_VF13_LATENCY 0x1b403 9589 #define regBIF_CFG_DEV0_EPF0_VF13_LATENCY_BASE_IDX 5 9590 #define regBIF_CFG_DEV0_EPF0_VF13_HEADER 0x1b403 9591 #define regBIF_CFG_DEV0_EPF0_VF13_HEADER_BASE_IDX 5 9592 #define regBIF_CFG_DEV0_EPF0_VF13_BIST 0x1b403 9593 #define regBIF_CFG_DEV0_EPF0_VF13_BIST_BASE_IDX 5 9594 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1 0x1b404 9595 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1_BASE_IDX 5 9596 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2 0x1b405 9597 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2_BASE_IDX 5 9598 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3 0x1b406 9599 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3_BASE_IDX 5 9600 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4 0x1b407 9601 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4_BASE_IDX 5 9602 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5 0x1b408 9603 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5_BASE_IDX 5 9604 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6 0x1b409 9605 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6_BASE_IDX 5 9606 #define regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR 0x1b40a 9607 #define regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR_BASE_IDX 5 9608 #define regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID 0x1b40b 9609 #define regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID_BASE_IDX 5 9610 #define regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR 0x1b40c 9611 #define regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR_BASE_IDX 5 9612 #define regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR 0x1b40d 9613 #define regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR_BASE_IDX 5 9614 #define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE 0x1b40f 9615 #define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE_BASE_IDX 5 9616 #define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN 0x1b40f 9617 #define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN_BASE_IDX 5 9618 #define regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT 0x1b40f 9619 #define regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT_BASE_IDX 5 9620 #define regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY 0x1b40f 9621 #define regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY_BASE_IDX 5 9622 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST 0x1b419 9623 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST_BASE_IDX 5 9624 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP 0x1b419 9625 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_BASE_IDX 5 9626 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP 0x1b41a 9627 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP_BASE_IDX 5 9628 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL 0x1b41b 9629 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL_BASE_IDX 5 9630 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS 0x1b41b 9631 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS_BASE_IDX 5 9632 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP 0x1b41c 9633 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP_BASE_IDX 5 9634 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL 0x1b41d 9635 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL_BASE_IDX 5 9636 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS 0x1b41d 9637 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS_BASE_IDX 5 9638 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2 0x1b422 9639 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2_BASE_IDX 5 9640 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2 0x1b423 9641 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2_BASE_IDX 5 9642 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2 0x1b423 9643 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2_BASE_IDX 5 9644 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2 0x1b424 9645 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2_BASE_IDX 5 9646 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2 0x1b425 9647 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2_BASE_IDX 5 9648 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2 0x1b425 9649 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2_BASE_IDX 5 9650 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST 0x1b428 9651 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST_BASE_IDX 5 9652 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL 0x1b428 9653 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL_BASE_IDX 5 9654 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO 0x1b429 9655 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO_BASE_IDX 5 9656 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI 0x1b42a 9657 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI_BASE_IDX 5 9658 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA 0x1b42a 9659 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_BASE_IDX 5 9660 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA 0x1b42a 9661 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_BASE_IDX 5 9662 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK 0x1b42b 9663 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_BASE_IDX 5 9664 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64 0x1b42b 9665 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64_BASE_IDX 5 9666 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64 0x1b42b 9667 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64_BASE_IDX 5 9668 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64 0x1b42c 9669 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64_BASE_IDX 5 9670 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING 0x1b42c 9671 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_BASE_IDX 5 9672 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64 0x1b42d 9673 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64_BASE_IDX 5 9674 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST 0x1b430 9675 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST_BASE_IDX 5 9676 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL 0x1b430 9677 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL_BASE_IDX 5 9678 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE 0x1b431 9679 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE_BASE_IDX 5 9680 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA 0x1b432 9681 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA_BASE_IDX 5 9682 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b440 9683 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 9684 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR 0x1b441 9685 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 9686 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1 0x1b442 9687 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 9688 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2 0x1b443 9689 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 9690 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b454 9691 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 9692 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS 0x1b455 9693 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 9694 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK 0x1b456 9695 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 9696 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY 0x1b457 9697 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 9698 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS 0x1b458 9699 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS_BASE_IDX 5 9700 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK 0x1b459 9701 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK_BASE_IDX 5 9702 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL 0x1b45a 9703 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 9704 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0 0x1b45b 9705 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0_BASE_IDX 5 9706 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1 0x1b45c 9707 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1_BASE_IDX 5 9708 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2 0x1b45d 9709 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2_BASE_IDX 5 9710 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3 0x1b45e 9711 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3_BASE_IDX 5 9712 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0 0x1b462 9713 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 9714 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1 0x1b463 9715 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 9716 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2 0x1b464 9717 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 9718 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3 0x1b465 9719 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 9720 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST 0x1b4ca 9721 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 9722 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP 0x1b4cb 9723 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP_BASE_IDX 5 9724 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL 0x1b4cb 9725 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL_BASE_IDX 5 9726 9727 9728 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 9729 // base address: 0x1016e000 9730 #define regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID 0x1b800 9731 #define regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID_BASE_IDX 5 9732 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID 0x1b800 9733 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID_BASE_IDX 5 9734 #define regBIF_CFG_DEV0_EPF0_VF14_COMMAND 0x1b801 9735 #define regBIF_CFG_DEV0_EPF0_VF14_COMMAND_BASE_IDX 5 9736 #define regBIF_CFG_DEV0_EPF0_VF14_STATUS 0x1b801 9737 #define regBIF_CFG_DEV0_EPF0_VF14_STATUS_BASE_IDX 5 9738 #define regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID 0x1b802 9739 #define regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID_BASE_IDX 5 9740 #define regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE 0x1b802 9741 #define regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE_BASE_IDX 5 9742 #define regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS 0x1b802 9743 #define regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS_BASE_IDX 5 9744 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS 0x1b802 9745 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS_BASE_IDX 5 9746 #define regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE 0x1b803 9747 #define regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE_BASE_IDX 5 9748 #define regBIF_CFG_DEV0_EPF0_VF14_LATENCY 0x1b803 9749 #define regBIF_CFG_DEV0_EPF0_VF14_LATENCY_BASE_IDX 5 9750 #define regBIF_CFG_DEV0_EPF0_VF14_HEADER 0x1b803 9751 #define regBIF_CFG_DEV0_EPF0_VF14_HEADER_BASE_IDX 5 9752 #define regBIF_CFG_DEV0_EPF0_VF14_BIST 0x1b803 9753 #define regBIF_CFG_DEV0_EPF0_VF14_BIST_BASE_IDX 5 9754 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1 0x1b804 9755 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1_BASE_IDX 5 9756 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2 0x1b805 9757 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2_BASE_IDX 5 9758 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3 0x1b806 9759 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3_BASE_IDX 5 9760 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4 0x1b807 9761 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4_BASE_IDX 5 9762 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5 0x1b808 9763 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5_BASE_IDX 5 9764 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6 0x1b809 9765 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6_BASE_IDX 5 9766 #define regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR 0x1b80a 9767 #define regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR_BASE_IDX 5 9768 #define regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID 0x1b80b 9769 #define regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID_BASE_IDX 5 9770 #define regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR 0x1b80c 9771 #define regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR_BASE_IDX 5 9772 #define regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR 0x1b80d 9773 #define regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR_BASE_IDX 5 9774 #define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE 0x1b80f 9775 #define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE_BASE_IDX 5 9776 #define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN 0x1b80f 9777 #define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN_BASE_IDX 5 9778 #define regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT 0x1b80f 9779 #define regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT_BASE_IDX 5 9780 #define regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY 0x1b80f 9781 #define regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY_BASE_IDX 5 9782 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST 0x1b819 9783 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST_BASE_IDX 5 9784 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP 0x1b819 9785 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_BASE_IDX 5 9786 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP 0x1b81a 9787 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP_BASE_IDX 5 9788 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL 0x1b81b 9789 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL_BASE_IDX 5 9790 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS 0x1b81b 9791 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS_BASE_IDX 5 9792 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP 0x1b81c 9793 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP_BASE_IDX 5 9794 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL 0x1b81d 9795 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL_BASE_IDX 5 9796 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS 0x1b81d 9797 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS_BASE_IDX 5 9798 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2 0x1b822 9799 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2_BASE_IDX 5 9800 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2 0x1b823 9801 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2_BASE_IDX 5 9802 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2 0x1b823 9803 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2_BASE_IDX 5 9804 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2 0x1b824 9805 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2_BASE_IDX 5 9806 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2 0x1b825 9807 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2_BASE_IDX 5 9808 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2 0x1b825 9809 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2_BASE_IDX 5 9810 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST 0x1b828 9811 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST_BASE_IDX 5 9812 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL 0x1b828 9813 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL_BASE_IDX 5 9814 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO 0x1b829 9815 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO_BASE_IDX 5 9816 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI 0x1b82a 9817 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI_BASE_IDX 5 9818 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA 0x1b82a 9819 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_BASE_IDX 5 9820 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA 0x1b82a 9821 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_BASE_IDX 5 9822 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK 0x1b82b 9823 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_BASE_IDX 5 9824 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64 0x1b82b 9825 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64_BASE_IDX 5 9826 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64 0x1b82b 9827 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64_BASE_IDX 5 9828 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64 0x1b82c 9829 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64_BASE_IDX 5 9830 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING 0x1b82c 9831 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_BASE_IDX 5 9832 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64 0x1b82d 9833 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64_BASE_IDX 5 9834 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST 0x1b830 9835 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST_BASE_IDX 5 9836 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL 0x1b830 9837 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL_BASE_IDX 5 9838 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE 0x1b831 9839 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE_BASE_IDX 5 9840 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA 0x1b832 9841 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA_BASE_IDX 5 9842 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b840 9843 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 9844 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR 0x1b841 9845 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 9846 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1 0x1b842 9847 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 9848 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2 0x1b843 9849 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 9850 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b854 9851 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 9852 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS 0x1b855 9853 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 9854 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK 0x1b856 9855 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 9856 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY 0x1b857 9857 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 9858 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS 0x1b858 9859 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS_BASE_IDX 5 9860 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK 0x1b859 9861 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK_BASE_IDX 5 9862 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL 0x1b85a 9863 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 9864 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0 0x1b85b 9865 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0_BASE_IDX 5 9866 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1 0x1b85c 9867 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1_BASE_IDX 5 9868 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2 0x1b85d 9869 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2_BASE_IDX 5 9870 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3 0x1b85e 9871 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3_BASE_IDX 5 9872 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0 0x1b862 9873 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 9874 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1 0x1b863 9875 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 9876 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2 0x1b864 9877 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 9878 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3 0x1b865 9879 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 9880 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST 0x1b8ca 9881 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 9882 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP 0x1b8cb 9883 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP_BASE_IDX 5 9884 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL 0x1b8cb 9885 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL_BASE_IDX 5 9886 9887 9888 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 9889 // base address: 0x1016f000 9890 #define regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID 0x1bc00 9891 #define regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID_BASE_IDX 5 9892 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID 0x1bc00 9893 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID_BASE_IDX 5 9894 #define regBIF_CFG_DEV0_EPF0_VF15_COMMAND 0x1bc01 9895 #define regBIF_CFG_DEV0_EPF0_VF15_COMMAND_BASE_IDX 5 9896 #define regBIF_CFG_DEV0_EPF0_VF15_STATUS 0x1bc01 9897 #define regBIF_CFG_DEV0_EPF0_VF15_STATUS_BASE_IDX 5 9898 #define regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID 0x1bc02 9899 #define regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID_BASE_IDX 5 9900 #define regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE 0x1bc02 9901 #define regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE_BASE_IDX 5 9902 #define regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS 0x1bc02 9903 #define regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS_BASE_IDX 5 9904 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS 0x1bc02 9905 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS_BASE_IDX 5 9906 #define regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE 0x1bc03 9907 #define regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE_BASE_IDX 5 9908 #define regBIF_CFG_DEV0_EPF0_VF15_LATENCY 0x1bc03 9909 #define regBIF_CFG_DEV0_EPF0_VF15_LATENCY_BASE_IDX 5 9910 #define regBIF_CFG_DEV0_EPF0_VF15_HEADER 0x1bc03 9911 #define regBIF_CFG_DEV0_EPF0_VF15_HEADER_BASE_IDX 5 9912 #define regBIF_CFG_DEV0_EPF0_VF15_BIST 0x1bc03 9913 #define regBIF_CFG_DEV0_EPF0_VF15_BIST_BASE_IDX 5 9914 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1 0x1bc04 9915 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1_BASE_IDX 5 9916 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2 0x1bc05 9917 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2_BASE_IDX 5 9918 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3 0x1bc06 9919 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3_BASE_IDX 5 9920 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4 0x1bc07 9921 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4_BASE_IDX 5 9922 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5 0x1bc08 9923 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5_BASE_IDX 5 9924 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6 0x1bc09 9925 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6_BASE_IDX 5 9926 #define regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR 0x1bc0a 9927 #define regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR_BASE_IDX 5 9928 #define regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID 0x1bc0b 9929 #define regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID_BASE_IDX 5 9930 #define regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR 0x1bc0c 9931 #define regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR_BASE_IDX 5 9932 #define regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR 0x1bc0d 9933 #define regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR_BASE_IDX 5 9934 #define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE 0x1bc0f 9935 #define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE_BASE_IDX 5 9936 #define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN 0x1bc0f 9937 #define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN_BASE_IDX 5 9938 #define regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT 0x1bc0f 9939 #define regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT_BASE_IDX 5 9940 #define regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY 0x1bc0f 9941 #define regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY_BASE_IDX 5 9942 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST 0x1bc19 9943 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST_BASE_IDX 5 9944 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP 0x1bc19 9945 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_BASE_IDX 5 9946 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP 0x1bc1a 9947 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP_BASE_IDX 5 9948 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL 0x1bc1b 9949 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL_BASE_IDX 5 9950 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS 0x1bc1b 9951 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS_BASE_IDX 5 9952 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP 0x1bc1c 9953 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP_BASE_IDX 5 9954 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL 0x1bc1d 9955 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL_BASE_IDX 5 9956 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS 0x1bc1d 9957 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS_BASE_IDX 5 9958 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2 0x1bc22 9959 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2_BASE_IDX 5 9960 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2 0x1bc23 9961 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2_BASE_IDX 5 9962 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2 0x1bc23 9963 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2_BASE_IDX 5 9964 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2 0x1bc24 9965 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2_BASE_IDX 5 9966 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2 0x1bc25 9967 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2_BASE_IDX 5 9968 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2 0x1bc25 9969 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2_BASE_IDX 5 9970 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST 0x1bc28 9971 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST_BASE_IDX 5 9972 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL 0x1bc28 9973 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL_BASE_IDX 5 9974 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO 0x1bc29 9975 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO_BASE_IDX 5 9976 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI 0x1bc2a 9977 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI_BASE_IDX 5 9978 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA 0x1bc2a 9979 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_BASE_IDX 5 9980 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA 0x1bc2a 9981 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_BASE_IDX 5 9982 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK 0x1bc2b 9983 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_BASE_IDX 5 9984 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64 0x1bc2b 9985 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64_BASE_IDX 5 9986 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64 0x1bc2b 9987 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64_BASE_IDX 5 9988 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64 0x1bc2c 9989 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64_BASE_IDX 5 9990 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING 0x1bc2c 9991 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_BASE_IDX 5 9992 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64 0x1bc2d 9993 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64_BASE_IDX 5 9994 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST 0x1bc30 9995 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST_BASE_IDX 5 9996 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL 0x1bc30 9997 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL_BASE_IDX 5 9998 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE 0x1bc31 9999 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE_BASE_IDX 5 10000 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA 0x1bc32 10001 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA_BASE_IDX 5 10002 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1bc40 10003 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 10004 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR 0x1bc41 10005 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 10006 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1 0x1bc42 10007 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 10008 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2 0x1bc43 10009 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 10010 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1bc54 10011 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 10012 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS 0x1bc55 10013 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 10014 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK 0x1bc56 10015 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 10016 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY 0x1bc57 10017 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 10018 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS 0x1bc58 10019 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS_BASE_IDX 5 10020 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK 0x1bc59 10021 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK_BASE_IDX 5 10022 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL 0x1bc5a 10023 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 10024 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0 0x1bc5b 10025 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0_BASE_IDX 5 10026 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1 0x1bc5c 10027 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1_BASE_IDX 5 10028 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2 0x1bc5d 10029 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2_BASE_IDX 5 10030 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3 0x1bc5e 10031 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3_BASE_IDX 5 10032 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0 0x1bc62 10033 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 10034 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1 0x1bc63 10035 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 10036 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2 0x1bc64 10037 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 10038 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3 0x1bc65 10039 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 10040 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST 0x1bcca 10041 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 10042 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP 0x1bccb 10043 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP_BASE_IDX 5 10044 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL 0x1bccb 10045 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL_BASE_IDX 5 10046 10047 10048 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 10049 // base address: 0x10141000 10050 #define regBIF_CFG_DEV0_EPF1_VENDOR_ID 0x10400 10051 #define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX 5 10052 #define regBIF_CFG_DEV0_EPF1_DEVICE_ID 0x10400 10053 #define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX 5 10054 #define regBIF_CFG_DEV0_EPF1_COMMAND 0x10401 10055 #define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX 5 10056 #define regBIF_CFG_DEV0_EPF1_STATUS 0x10401 10057 #define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX 5 10058 #define regBIF_CFG_DEV0_EPF1_REVISION_ID 0x10402 10059 #define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX 5 10060 #define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x10402 10061 #define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX 5 10062 #define regBIF_CFG_DEV0_EPF1_SUB_CLASS 0x10402 10063 #define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX 5 10064 #define regBIF_CFG_DEV0_EPF1_BASE_CLASS 0x10402 10065 #define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX 5 10066 #define regBIF_CFG_DEV0_EPF1_CACHE_LINE 0x10403 10067 #define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX 5 10068 #define regBIF_CFG_DEV0_EPF1_LATENCY 0x10403 10069 #define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX 5 10070 #define regBIF_CFG_DEV0_EPF1_HEADER 0x10403 10071 #define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX 5 10072 #define regBIF_CFG_DEV0_EPF1_BIST 0x10403 10073 #define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX 5 10074 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x10404 10075 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX 5 10076 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x10405 10077 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX 5 10078 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x10406 10079 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX 5 10080 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x10407 10081 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX 5 10082 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x10408 10083 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX 5 10084 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x10409 10085 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX 5 10086 #define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x1040a 10087 #define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX 5 10088 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x1040b 10089 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX 5 10090 #define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x1040c 10091 #define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX 5 10092 #define regBIF_CFG_DEV0_EPF1_CAP_PTR 0x1040d 10093 #define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX 5 10094 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x1040f 10095 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX 5 10096 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x1040f 10097 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX 5 10098 #define regBIF_CFG_DEV0_EPF1_MIN_GRANT 0x1040f 10099 #define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX 5 10100 #define regBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x1040f 10101 #define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX 5 10102 #define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x10412 10103 #define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX 5 10104 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x10413 10105 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX 5 10106 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x10414 10107 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX 5 10108 #define regBIF_CFG_DEV0_EPF1_PMI_CAP 0x10414 10109 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX 5 10110 #define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x10415 10111 #define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX 5 10112 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x10419 10113 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX 5 10114 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP 0x10419 10115 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX 5 10116 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x1041a 10117 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX 5 10118 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x1041b 10119 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX 5 10120 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x1041b 10121 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX 5 10122 #define regBIF_CFG_DEV0_EPF1_LINK_CAP 0x1041c 10123 #define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX 5 10124 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL 0x1041d 10125 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX 5 10126 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS 0x1041d 10127 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX 5 10128 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x10422 10129 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX 5 10130 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x10423 10131 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX 5 10132 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x10423 10133 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX 5 10134 #define regBIF_CFG_DEV0_EPF1_LINK_CAP2 0x10424 10135 #define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX 5 10136 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x10425 10137 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX 5 10138 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x10425 10139 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX 5 10140 #define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x10428 10141 #define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX 5 10142 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x10428 10143 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX 5 10144 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x10429 10145 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX 5 10146 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x1042a 10147 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX 5 10148 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x1042a 10149 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX 5 10150 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x1042a 10151 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX 5 10152 #define regBIF_CFG_DEV0_EPF1_MSI_MASK 0x1042b 10153 #define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX 5 10154 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x1042b 10155 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX 5 10156 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x1042b 10157 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 10158 #define regBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x1042c 10159 #define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX 5 10160 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING 0x1042c 10161 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX 5 10162 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x1042d 10163 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX 5 10164 #define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x10430 10165 #define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX 5 10166 #define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x10430 10167 #define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX 5 10168 #define regBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x10431 10169 #define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX 5 10170 #define regBIF_CFG_DEV0_EPF1_MSIX_PBA 0x10432 10171 #define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX 5 10172 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 10173 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 10174 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x10441 10175 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 10176 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x10442 10177 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 10178 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x10443 10179 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 10180 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10450 10181 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 10182 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 0x10451 10183 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 10184 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 0x10452 10185 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 10186 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 10187 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 10188 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x10455 10189 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 10190 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x10456 10191 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 10192 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x10457 10193 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 10194 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x10458 10195 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 10196 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x10459 10197 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 10198 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x1045a 10199 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 10200 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x1045b 10201 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX 5 10202 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x1045c 10203 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX 5 10204 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x1045d 10205 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX 5 10206 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x1045e 10207 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX 5 10208 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x10462 10209 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 10210 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x10463 10211 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 10212 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x10464 10213 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 10214 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x10465 10215 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 10216 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x10480 10217 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 10218 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x10481 10219 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX 5 10220 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x10482 10221 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX 5 10222 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x10483 10223 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX 5 10224 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x10484 10225 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX 5 10226 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x10485 10227 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX 5 10228 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x10486 10229 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX 5 10230 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x10487 10231 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX 5 10232 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x10488 10233 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX 5 10234 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x10489 10235 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX 5 10236 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x1048a 10237 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX 5 10238 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x1048b 10239 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX 5 10240 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x1048c 10241 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX 5 10242 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 10243 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 10244 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 10245 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 10246 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x10492 10247 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 10248 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x10493 10249 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 10250 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x10494 10251 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 10252 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x10495 10253 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX 5 10254 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x10496 10255 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 10256 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x10497 10257 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX 5 10258 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x10497 10259 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX 5 10260 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 10261 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 10262 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 10263 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 10264 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 10265 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 10266 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 10267 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 10268 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 10269 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 10270 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 10271 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 10272 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 10273 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 10274 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 10275 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 10276 #define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 0x1049c 10277 #define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 10278 #define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 0x1049d 10279 #define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_BASE_IDX 5 10280 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 0x1049e 10281 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 10282 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 0x1049f 10283 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 10284 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 0x1049f 10285 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 10286 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 0x104a0 10287 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 10288 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 0x104a0 10289 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 10290 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 0x104a1 10291 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 10292 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 0x104a1 10293 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 10294 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 0x104a2 10295 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 10296 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 0x104a2 10297 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 10298 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 0x104a3 10299 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 10300 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 0x104a3 10301 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 10302 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 0x104a4 10303 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 10304 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 0x104a4 10305 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 10306 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 0x104a5 10307 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 10308 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 0x104a5 10309 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 10310 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 0x104a6 10311 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 10312 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 0x104a6 10313 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 10314 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x104a8 10315 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 10316 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x104a9 10317 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX 5 10318 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x104a9 10319 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX 5 10320 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x104b4 10321 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 10322 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x104b5 10323 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX 5 10324 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x104b5 10325 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX 5 10326 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST 0x104bc 10327 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 10328 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP 0x104bd 10329 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP_BASE_IDX 5 10330 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL 0x104bd 10331 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL_BASE_IDX 5 10332 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 0x104be 10333 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0_BASE_IDX 5 10334 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 0x104bf 10335 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1_BASE_IDX 5 10336 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 0x104c0 10337 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0_BASE_IDX 5 10338 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 0x104c1 10339 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1_BASE_IDX 5 10340 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 0x104c2 10341 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 10342 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 0x104c3 10343 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 10344 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x104c4 10345 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 10346 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x104c5 10347 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 10348 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 0x104c8 10349 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 10350 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 0x104c9 10351 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_BASE_IDX 5 10352 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x104ca 10353 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 10354 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x104cb 10355 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX 5 10356 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x104cb 10357 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX 5 10358 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x104cc 10359 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 10360 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x104cd 10361 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX 5 10362 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x104ce 10363 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX 5 10364 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x104ce 10365 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX 5 10366 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x104cf 10367 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 10368 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x104cf 10369 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 10370 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x104d0 10371 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 10372 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x104d0 10373 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 10374 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x104d1 10375 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 10376 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x104d1 10377 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 10378 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x104d2 10379 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 10380 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x104d3 10381 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 10382 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x104d4 10383 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 10384 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x104d5 10385 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 10386 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x104d6 10387 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 10388 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x104d7 10389 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 10390 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x104d8 10391 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 10392 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x104d9 10393 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 10394 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x104da 10395 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 10396 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x104db 10397 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 10398 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10530 10399 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 10400 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x10531 10401 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 10402 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x10532 10403 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 10404 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x10533 10405 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 10406 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x10534 10407 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 10408 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x10535 10409 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 10410 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x10536 10411 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 10412 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x10537 10413 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 10414 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x10538 10415 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 10416 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x10539 10417 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 10418 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x1053a 10419 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 10420 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x1053b 10421 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 10422 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x1053c 10423 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 10424 10425 10426 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp 10427 // base address: 0x10142000 10428 #define regBIF_CFG_DEV0_EPF2_VENDOR_ID 0x10800 10429 #define regBIF_CFG_DEV0_EPF2_VENDOR_ID_BASE_IDX 5 10430 #define regBIF_CFG_DEV0_EPF2_DEVICE_ID 0x10800 10431 #define regBIF_CFG_DEV0_EPF2_DEVICE_ID_BASE_IDX 5 10432 #define regBIF_CFG_DEV0_EPF2_COMMAND 0x10801 10433 #define regBIF_CFG_DEV0_EPF2_COMMAND_BASE_IDX 5 10434 #define regBIF_CFG_DEV0_EPF2_STATUS 0x10801 10435 #define regBIF_CFG_DEV0_EPF2_STATUS_BASE_IDX 5 10436 #define regBIF_CFG_DEV0_EPF2_REVISION_ID 0x10802 10437 #define regBIF_CFG_DEV0_EPF2_REVISION_ID_BASE_IDX 5 10438 #define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE 0x10802 10439 #define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE_BASE_IDX 5 10440 #define regBIF_CFG_DEV0_EPF2_SUB_CLASS 0x10802 10441 #define regBIF_CFG_DEV0_EPF2_SUB_CLASS_BASE_IDX 5 10442 #define regBIF_CFG_DEV0_EPF2_BASE_CLASS 0x10802 10443 #define regBIF_CFG_DEV0_EPF2_BASE_CLASS_BASE_IDX 5 10444 #define regBIF_CFG_DEV0_EPF2_CACHE_LINE 0x10803 10445 #define regBIF_CFG_DEV0_EPF2_CACHE_LINE_BASE_IDX 5 10446 #define regBIF_CFG_DEV0_EPF2_LATENCY 0x10803 10447 #define regBIF_CFG_DEV0_EPF2_LATENCY_BASE_IDX 5 10448 #define regBIF_CFG_DEV0_EPF2_HEADER 0x10803 10449 #define regBIF_CFG_DEV0_EPF2_HEADER_BASE_IDX 5 10450 #define regBIF_CFG_DEV0_EPF2_BIST 0x10803 10451 #define regBIF_CFG_DEV0_EPF2_BIST_BASE_IDX 5 10452 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1 0x10804 10453 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1_BASE_IDX 5 10454 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2 0x10805 10455 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2_BASE_IDX 5 10456 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3 0x10806 10457 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3_BASE_IDX 5 10458 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4 0x10807 10459 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4_BASE_IDX 5 10460 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5 0x10808 10461 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5_BASE_IDX 5 10462 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6 0x10809 10463 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6_BASE_IDX 5 10464 #define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR 0x1080a 10465 #define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_BASE_IDX 5 10466 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID 0x1080b 10467 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_BASE_IDX 5 10468 #define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR 0x1080c 10469 #define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_BASE_IDX 5 10470 #define regBIF_CFG_DEV0_EPF2_CAP_PTR 0x1080d 10471 #define regBIF_CFG_DEV0_EPF2_CAP_PTR_BASE_IDX 5 10472 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE 0x1080f 10473 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_BASE_IDX 5 10474 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN 0x1080f 10475 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_BASE_IDX 5 10476 #define regBIF_CFG_DEV0_EPF2_MIN_GRANT 0x1080f 10477 #define regBIF_CFG_DEV0_EPF2_MIN_GRANT_BASE_IDX 5 10478 #define regBIF_CFG_DEV0_EPF2_MAX_LATENCY 0x1080f 10479 #define regBIF_CFG_DEV0_EPF2_MAX_LATENCY_BASE_IDX 5 10480 #define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST 0x10812 10481 #define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_BASE_IDX 5 10482 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W 0x10813 10483 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_BASE_IDX 5 10484 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST 0x10814 10485 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_BASE_IDX 5 10486 #define regBIF_CFG_DEV0_EPF2_PMI_CAP 0x10814 10487 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_BASE_IDX 5 10488 #define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL 0x10815 10489 #define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_BASE_IDX 5 10490 #define regBIF_CFG_DEV0_EPF2_SBRN 0x10818 10491 #define regBIF_CFG_DEV0_EPF2_SBRN_BASE_IDX 5 10492 #define regBIF_CFG_DEV0_EPF2_FLADJ 0x10818 10493 #define regBIF_CFG_DEV0_EPF2_FLADJ_BASE_IDX 5 10494 #define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD 0x10818 10495 #define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD_BASE_IDX 5 10496 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST 0x10819 10497 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_BASE_IDX 5 10498 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP 0x10819 10499 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_BASE_IDX 5 10500 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP 0x1081a 10501 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP_BASE_IDX 5 10502 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL 0x1081b 10503 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL_BASE_IDX 5 10504 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS 0x1081b 10505 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS_BASE_IDX 5 10506 #define regBIF_CFG_DEV0_EPF2_LINK_CAP 0x1081c 10507 #define regBIF_CFG_DEV0_EPF2_LINK_CAP_BASE_IDX 5 10508 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL 0x1081d 10509 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL_BASE_IDX 5 10510 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS 0x1081d 10511 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS_BASE_IDX 5 10512 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2 0x10822 10513 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2_BASE_IDX 5 10514 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2 0x10823 10515 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_BASE_IDX 5 10516 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2 0x10823 10517 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_BASE_IDX 5 10518 #define regBIF_CFG_DEV0_EPF2_LINK_CAP2 0x10824 10519 #define regBIF_CFG_DEV0_EPF2_LINK_CAP2_BASE_IDX 5 10520 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL2 0x10825 10521 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL2_BASE_IDX 5 10522 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS2 0x10825 10523 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS2_BASE_IDX 5 10524 #define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST 0x10828 10525 #define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_BASE_IDX 5 10526 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL 0x10828 10527 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_BASE_IDX 5 10528 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO 0x10829 10529 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_BASE_IDX 5 10530 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI 0x1082a 10531 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_BASE_IDX 5 10532 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA 0x1082a 10533 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_BASE_IDX 5 10534 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA 0x1082a 10535 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_BASE_IDX 5 10536 #define regBIF_CFG_DEV0_EPF2_MSI_MASK 0x1082b 10537 #define regBIF_CFG_DEV0_EPF2_MSI_MASK_BASE_IDX 5 10538 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 0x1082b 10539 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_BASE_IDX 5 10540 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 0x1082b 10541 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 10542 #define regBIF_CFG_DEV0_EPF2_MSI_MASK_64 0x1082c 10543 #define regBIF_CFG_DEV0_EPF2_MSI_MASK_64_BASE_IDX 5 10544 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING 0x1082c 10545 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_BASE_IDX 5 10546 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64 0x1082d 10547 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64_BASE_IDX 5 10548 #define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST 0x10830 10549 #define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_BASE_IDX 5 10550 #define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL 0x10830 10551 #define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_BASE_IDX 5 10552 #define regBIF_CFG_DEV0_EPF2_MSIX_TABLE 0x10831 10553 #define regBIF_CFG_DEV0_EPF2_MSIX_TABLE_BASE_IDX 5 10554 #define regBIF_CFG_DEV0_EPF2_MSIX_PBA 0x10832 10555 #define regBIF_CFG_DEV0_EPF2_MSIX_PBA_BASE_IDX 5 10556 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10840 10557 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 10558 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR 0x10841 10559 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 10560 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 0x10842 10561 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 10562 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 0x10843 10563 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 10564 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10854 10565 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 10566 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS 0x10855 10567 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 10568 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK 0x10856 10569 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 10570 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY 0x10857 10571 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 10572 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS 0x10858 10573 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 10574 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK 0x10859 10575 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 10576 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL 0x1085a 10577 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 10578 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 0x1085b 10579 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_BASE_IDX 5 10580 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 0x1085c 10581 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_BASE_IDX 5 10582 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 0x1085d 10583 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_BASE_IDX 5 10584 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 0x1085e 10585 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_BASE_IDX 5 10586 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 0x10862 10587 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 10588 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 0x10863 10589 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 10590 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 0x10864 10591 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 10592 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 0x10865 10593 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 10594 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST 0x10880 10595 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 10596 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP 0x10881 10597 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_BASE_IDX 5 10598 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL 0x10882 10599 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_BASE_IDX 5 10600 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP 0x10883 10601 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_BASE_IDX 5 10602 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL 0x10884 10603 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_BASE_IDX 5 10604 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP 0x10885 10605 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_BASE_IDX 5 10606 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL 0x10886 10607 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_BASE_IDX 5 10608 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP 0x10887 10609 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_BASE_IDX 5 10610 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL 0x10888 10611 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_BASE_IDX 5 10612 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP 0x10889 10613 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_BASE_IDX 5 10614 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL 0x1088a 10615 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_BASE_IDX 5 10616 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP 0x1088b 10617 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_BASE_IDX 5 10618 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL 0x1088c 10619 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_BASE_IDX 5 10620 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10890 10621 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 10622 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT 0x10891 10623 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 10624 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA 0x10892 10625 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 10626 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP 0x10893 10627 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 10628 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST 0x10894 10629 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 10630 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP 0x10895 10631 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_BASE_IDX 5 10632 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR 0x10896 10633 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 10634 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS 0x10897 10635 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_BASE_IDX 5 10636 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL 0x10897 10637 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_BASE_IDX 5 10638 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10898 10639 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 10640 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10898 10641 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 10642 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10898 10643 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 10644 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10898 10645 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 10646 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10899 10647 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 10648 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10899 10649 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 10650 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10899 10651 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 10652 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10899 10653 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 10654 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST 0x108a8 10655 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 10656 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP 0x108a9 10657 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_BASE_IDX 5 10658 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL 0x108a9 10659 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_BASE_IDX 5 10660 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST 0x108b4 10661 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 10662 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP 0x108b5 10663 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_BASE_IDX 5 10664 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL 0x108b5 10665 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_BASE_IDX 5 10666 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST 0x108ca 10667 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 10668 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP 0x108cb 10669 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_BASE_IDX 5 10670 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL 0x108cb 10671 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_BASE_IDX 5 10672 10673 10674 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp 10675 // base address: 0x10143000 10676 #define regBIF_CFG_DEV0_EPF3_VENDOR_ID 0x10c00 10677 #define regBIF_CFG_DEV0_EPF3_VENDOR_ID_BASE_IDX 5 10678 #define regBIF_CFG_DEV0_EPF3_DEVICE_ID 0x10c00 10679 #define regBIF_CFG_DEV0_EPF3_DEVICE_ID_BASE_IDX 5 10680 #define regBIF_CFG_DEV0_EPF3_COMMAND 0x10c01 10681 #define regBIF_CFG_DEV0_EPF3_COMMAND_BASE_IDX 5 10682 #define regBIF_CFG_DEV0_EPF3_STATUS 0x10c01 10683 #define regBIF_CFG_DEV0_EPF3_STATUS_BASE_IDX 5 10684 #define regBIF_CFG_DEV0_EPF3_REVISION_ID 0x10c02 10685 #define regBIF_CFG_DEV0_EPF3_REVISION_ID_BASE_IDX 5 10686 #define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE 0x10c02 10687 #define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE_BASE_IDX 5 10688 #define regBIF_CFG_DEV0_EPF3_SUB_CLASS 0x10c02 10689 #define regBIF_CFG_DEV0_EPF3_SUB_CLASS_BASE_IDX 5 10690 #define regBIF_CFG_DEV0_EPF3_BASE_CLASS 0x10c02 10691 #define regBIF_CFG_DEV0_EPF3_BASE_CLASS_BASE_IDX 5 10692 #define regBIF_CFG_DEV0_EPF3_CACHE_LINE 0x10c03 10693 #define regBIF_CFG_DEV0_EPF3_CACHE_LINE_BASE_IDX 5 10694 #define regBIF_CFG_DEV0_EPF3_LATENCY 0x10c03 10695 #define regBIF_CFG_DEV0_EPF3_LATENCY_BASE_IDX 5 10696 #define regBIF_CFG_DEV0_EPF3_HEADER 0x10c03 10697 #define regBIF_CFG_DEV0_EPF3_HEADER_BASE_IDX 5 10698 #define regBIF_CFG_DEV0_EPF3_BIST 0x10c03 10699 #define regBIF_CFG_DEV0_EPF3_BIST_BASE_IDX 5 10700 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1 0x10c04 10701 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1_BASE_IDX 5 10702 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2 0x10c05 10703 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2_BASE_IDX 5 10704 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3 0x10c06 10705 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3_BASE_IDX 5 10706 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4 0x10c07 10707 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4_BASE_IDX 5 10708 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5 0x10c08 10709 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5_BASE_IDX 5 10710 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6 0x10c09 10711 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6_BASE_IDX 5 10712 #define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR 0x10c0a 10713 #define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_BASE_IDX 5 10714 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID 0x10c0b 10715 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_BASE_IDX 5 10716 #define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR 0x10c0c 10717 #define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_BASE_IDX 5 10718 #define regBIF_CFG_DEV0_EPF3_CAP_PTR 0x10c0d 10719 #define regBIF_CFG_DEV0_EPF3_CAP_PTR_BASE_IDX 5 10720 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE 0x10c0f 10721 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_BASE_IDX 5 10722 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN 0x10c0f 10723 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_BASE_IDX 5 10724 #define regBIF_CFG_DEV0_EPF3_MIN_GRANT 0x10c0f 10725 #define regBIF_CFG_DEV0_EPF3_MIN_GRANT_BASE_IDX 5 10726 #define regBIF_CFG_DEV0_EPF3_MAX_LATENCY 0x10c0f 10727 #define regBIF_CFG_DEV0_EPF3_MAX_LATENCY_BASE_IDX 5 10728 #define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST 0x10c12 10729 #define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_BASE_IDX 5 10730 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W 0x10c13 10731 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_BASE_IDX 5 10732 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST 0x10c14 10733 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_BASE_IDX 5 10734 #define regBIF_CFG_DEV0_EPF3_PMI_CAP 0x10c14 10735 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_BASE_IDX 5 10736 #define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL 0x10c15 10737 #define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_BASE_IDX 5 10738 #define regBIF_CFG_DEV0_EPF3_SBRN 0x10c18 10739 #define regBIF_CFG_DEV0_EPF3_SBRN_BASE_IDX 5 10740 #define regBIF_CFG_DEV0_EPF3_FLADJ 0x10c18 10741 #define regBIF_CFG_DEV0_EPF3_FLADJ_BASE_IDX 5 10742 #define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD 0x10c18 10743 #define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD_BASE_IDX 5 10744 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST 0x10c19 10745 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_BASE_IDX 5 10746 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP 0x10c19 10747 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_BASE_IDX 5 10748 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP 0x10c1a 10749 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP_BASE_IDX 5 10750 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL 0x10c1b 10751 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL_BASE_IDX 5 10752 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS 0x10c1b 10753 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS_BASE_IDX 5 10754 #define regBIF_CFG_DEV0_EPF3_LINK_CAP 0x10c1c 10755 #define regBIF_CFG_DEV0_EPF3_LINK_CAP_BASE_IDX 5 10756 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL 0x10c1d 10757 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL_BASE_IDX 5 10758 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS 0x10c1d 10759 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS_BASE_IDX 5 10760 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2 0x10c22 10761 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2_BASE_IDX 5 10762 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2 0x10c23 10763 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_BASE_IDX 5 10764 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2 0x10c23 10765 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_BASE_IDX 5 10766 #define regBIF_CFG_DEV0_EPF3_LINK_CAP2 0x10c24 10767 #define regBIF_CFG_DEV0_EPF3_LINK_CAP2_BASE_IDX 5 10768 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL2 0x10c25 10769 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL2_BASE_IDX 5 10770 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS2 0x10c25 10771 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS2_BASE_IDX 5 10772 #define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST 0x10c28 10773 #define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_BASE_IDX 5 10774 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL 0x10c28 10775 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_BASE_IDX 5 10776 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO 0x10c29 10777 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_BASE_IDX 5 10778 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI 0x10c2a 10779 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_BASE_IDX 5 10780 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA 0x10c2a 10781 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_BASE_IDX 5 10782 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA 0x10c2a 10783 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_BASE_IDX 5 10784 #define regBIF_CFG_DEV0_EPF3_MSI_MASK 0x10c2b 10785 #define regBIF_CFG_DEV0_EPF3_MSI_MASK_BASE_IDX 5 10786 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 0x10c2b 10787 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_BASE_IDX 5 10788 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 0x10c2b 10789 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 10790 #define regBIF_CFG_DEV0_EPF3_MSI_MASK_64 0x10c2c 10791 #define regBIF_CFG_DEV0_EPF3_MSI_MASK_64_BASE_IDX 5 10792 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING 0x10c2c 10793 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_BASE_IDX 5 10794 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64 0x10c2d 10795 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64_BASE_IDX 5 10796 #define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST 0x10c30 10797 #define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_BASE_IDX 5 10798 #define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL 0x10c30 10799 #define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_BASE_IDX 5 10800 #define regBIF_CFG_DEV0_EPF3_MSIX_TABLE 0x10c31 10801 #define regBIF_CFG_DEV0_EPF3_MSIX_TABLE_BASE_IDX 5 10802 #define regBIF_CFG_DEV0_EPF3_MSIX_PBA 0x10c32 10803 #define regBIF_CFG_DEV0_EPF3_MSIX_PBA_BASE_IDX 5 10804 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10c40 10805 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 10806 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR 0x10c41 10807 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 10808 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 0x10c42 10809 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 10810 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 0x10c43 10811 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 10812 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10c54 10813 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 10814 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS 0x10c55 10815 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 10816 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK 0x10c56 10817 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 10818 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY 0x10c57 10819 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 10820 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS 0x10c58 10821 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 10822 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK 0x10c59 10823 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 10824 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL 0x10c5a 10825 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 10826 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 0x10c5b 10827 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_BASE_IDX 5 10828 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 0x10c5c 10829 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_BASE_IDX 5 10830 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 0x10c5d 10831 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_BASE_IDX 5 10832 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 0x10c5e 10833 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_BASE_IDX 5 10834 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 0x10c62 10835 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 10836 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 0x10c63 10837 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 10838 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 0x10c64 10839 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 10840 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 0x10c65 10841 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 10842 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST 0x10c80 10843 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 10844 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP 0x10c81 10845 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_BASE_IDX 5 10846 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL 0x10c82 10847 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_BASE_IDX 5 10848 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP 0x10c83 10849 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_BASE_IDX 5 10850 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL 0x10c84 10851 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_BASE_IDX 5 10852 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP 0x10c85 10853 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_BASE_IDX 5 10854 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL 0x10c86 10855 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_BASE_IDX 5 10856 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP 0x10c87 10857 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_BASE_IDX 5 10858 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL 0x10c88 10859 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_BASE_IDX 5 10860 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP 0x10c89 10861 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_BASE_IDX 5 10862 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL 0x10c8a 10863 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_BASE_IDX 5 10864 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP 0x10c8b 10865 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_BASE_IDX 5 10866 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL 0x10c8c 10867 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_BASE_IDX 5 10868 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10c90 10869 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 10870 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT 0x10c91 10871 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 10872 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA 0x10c92 10873 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 10874 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP 0x10c93 10875 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 10876 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST 0x10c94 10877 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 10878 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP 0x10c95 10879 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_BASE_IDX 5 10880 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR 0x10c96 10881 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 10882 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS 0x10c97 10883 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_BASE_IDX 5 10884 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL 0x10c97 10885 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_BASE_IDX 5 10886 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10c98 10887 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 10888 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10c98 10889 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 10890 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10c98 10891 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 10892 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10c98 10893 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 10894 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10c99 10895 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 10896 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10c99 10897 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 10898 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10c99 10899 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 10900 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10c99 10901 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 10902 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST 0x10ca8 10903 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 10904 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP 0x10ca9 10905 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_BASE_IDX 5 10906 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL 0x10ca9 10907 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_BASE_IDX 5 10908 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST 0x10cb4 10909 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 10910 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP 0x10cb5 10911 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_BASE_IDX 5 10912 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL 0x10cb5 10913 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_BASE_IDX 5 10914 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST 0x10cca 10915 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 10916 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP 0x10ccb 10917 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_BASE_IDX 5 10918 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL 0x10ccb 10919 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_BASE_IDX 5 10920 10921 10922 // addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC 10923 // base address: 0x10131000 10924 #define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 10925 #define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5 10926 #define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 10927 #define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5 10928 #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 10929 #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 10930 #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 10931 #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5 10932 #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 10933 #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5 10934 #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 10935 #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 10936 #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 10937 #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 10938 #define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 10939 #define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5 10940 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 10941 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 10942 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 10943 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 10944 10945 10946 // addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC 10947 // base address: 0x10131000 10948 #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c 10949 #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5 10950 #define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e 10951 #define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5 10952 #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f 10953 #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5 10954 #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 10955 #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5 10956 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 10957 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5 10958 #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 10959 #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5 10960 #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 10961 #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5 10962 #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 10963 #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 10964 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 10965 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5 10966 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 10967 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5 10968 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 10969 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 10970 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 10971 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 10972 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 10973 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 10974 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 10975 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 10976 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 10977 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 10978 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 10979 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 10980 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 10981 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 10982 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 10983 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 10984 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a 10985 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 10986 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a 10987 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 10988 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a 10989 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 10990 #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c 10991 #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5 10992 #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d 10993 #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5 10994 #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f 10995 #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5 10996 #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 10997 #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 10998 #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 10999 #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5 11000 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 11001 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5 11002 #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 11003 #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 11004 11005 11006 // addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC 11007 // base address: 0x10131000 11008 #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 11009 #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5 11010 #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 11011 #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5 11012 #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b 11013 #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5 11014 #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c 11015 #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 11016 #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d 11017 #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5 11018 #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e 11019 #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5 11020 #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f 11021 #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5 11022 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 11023 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5 11024 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 11025 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5 11026 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 11027 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5 11028 11029 11030 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC 11031 // base address: 0x10131000 11032 #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 11033 #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5 11034 #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 11035 #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5 11036 #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 11037 #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 11038 #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 11039 #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5 11040 #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 11041 #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5 11042 #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a 11043 #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 11044 11045 11046 // base address: 0x10170000 11047 #define regPCIEMSIX_VECT0_ADDR_LO 0x1c000 11048 #define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 5 11049 #define regPCIEMSIX_VECT0_ADDR_HI 0x1c001 11050 #define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 5 11051 #define regPCIEMSIX_VECT0_MSG_DATA 0x1c002 11052 #define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 5 11053 #define regPCIEMSIX_VECT0_CONTROL 0x1c003 11054 #define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 5 11055 #define regPCIEMSIX_VECT1_ADDR_LO 0x1c004 11056 #define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 5 11057 #define regPCIEMSIX_VECT1_ADDR_HI 0x1c005 11058 #define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 5 11059 #define regPCIEMSIX_VECT1_MSG_DATA 0x1c006 11060 #define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 5 11061 #define regPCIEMSIX_VECT1_CONTROL 0x1c007 11062 #define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 5 11063 #define regPCIEMSIX_VECT2_ADDR_LO 0x1c008 11064 #define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 5 11065 #define regPCIEMSIX_VECT2_ADDR_HI 0x1c009 11066 #define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 5 11067 #define regPCIEMSIX_VECT2_MSG_DATA 0x1c00a 11068 #define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 5 11069 #define regPCIEMSIX_VECT2_CONTROL 0x1c00b 11070 #define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 5 11071 #define regPCIEMSIX_VECT3_ADDR_LO 0x1c00c 11072 #define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 5 11073 #define regPCIEMSIX_VECT3_ADDR_HI 0x1c00d 11074 #define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 5 11075 #define regPCIEMSIX_VECT3_MSG_DATA 0x1c00e 11076 #define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 5 11077 #define regPCIEMSIX_VECT3_CONTROL 0x1c00f 11078 #define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 5 11079 #define regPCIEMSIX_VECT4_ADDR_LO 0x1c010 11080 #define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 5 11081 #define regPCIEMSIX_VECT4_ADDR_HI 0x1c011 11082 #define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 5 11083 #define regPCIEMSIX_VECT4_MSG_DATA 0x1c012 11084 #define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 5 11085 #define regPCIEMSIX_VECT4_CONTROL 0x1c013 11086 #define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 5 11087 #define regPCIEMSIX_VECT5_ADDR_LO 0x1c014 11088 #define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 5 11089 #define regPCIEMSIX_VECT5_ADDR_HI 0x1c015 11090 #define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 5 11091 #define regPCIEMSIX_VECT5_MSG_DATA 0x1c016 11092 #define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 5 11093 #define regPCIEMSIX_VECT5_CONTROL 0x1c017 11094 #define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 5 11095 #define regPCIEMSIX_VECT6_ADDR_LO 0x1c018 11096 #define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 5 11097 #define regPCIEMSIX_VECT6_ADDR_HI 0x1c019 11098 #define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 5 11099 #define regPCIEMSIX_VECT6_MSG_DATA 0x1c01a 11100 #define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 5 11101 #define regPCIEMSIX_VECT6_CONTROL 0x1c01b 11102 #define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 5 11103 #define regPCIEMSIX_VECT7_ADDR_LO 0x1c01c 11104 #define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 5 11105 #define regPCIEMSIX_VECT7_ADDR_HI 0x1c01d 11106 #define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 5 11107 #define regPCIEMSIX_VECT7_MSG_DATA 0x1c01e 11108 #define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 5 11109 #define regPCIEMSIX_VECT7_CONTROL 0x1c01f 11110 #define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 5 11111 #define regPCIEMSIX_VECT8_ADDR_LO 0x1c020 11112 #define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 5 11113 #define regPCIEMSIX_VECT8_ADDR_HI 0x1c021 11114 #define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 5 11115 #define regPCIEMSIX_VECT8_MSG_DATA 0x1c022 11116 #define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 5 11117 #define regPCIEMSIX_VECT8_CONTROL 0x1c023 11118 #define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 5 11119 #define regPCIEMSIX_VECT9_ADDR_LO 0x1c024 11120 #define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 5 11121 #define regPCIEMSIX_VECT9_ADDR_HI 0x1c025 11122 #define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 5 11123 #define regPCIEMSIX_VECT9_MSG_DATA 0x1c026 11124 #define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 5 11125 #define regPCIEMSIX_VECT9_CONTROL 0x1c027 11126 #define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 5 11127 #define regPCIEMSIX_VECT10_ADDR_LO 0x1c028 11128 #define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 5 11129 #define regPCIEMSIX_VECT10_ADDR_HI 0x1c029 11130 #define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 5 11131 #define regPCIEMSIX_VECT10_MSG_DATA 0x1c02a 11132 #define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 5 11133 #define regPCIEMSIX_VECT10_CONTROL 0x1c02b 11134 #define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 5 11135 #define regPCIEMSIX_VECT11_ADDR_LO 0x1c02c 11136 #define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 5 11137 #define regPCIEMSIX_VECT11_ADDR_HI 0x1c02d 11138 #define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 5 11139 #define regPCIEMSIX_VECT11_MSG_DATA 0x1c02e 11140 #define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 5 11141 #define regPCIEMSIX_VECT11_CONTROL 0x1c02f 11142 #define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 5 11143 #define regPCIEMSIX_VECT12_ADDR_LO 0x1c030 11144 #define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 5 11145 #define regPCIEMSIX_VECT12_ADDR_HI 0x1c031 11146 #define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 5 11147 #define regPCIEMSIX_VECT12_MSG_DATA 0x1c032 11148 #define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 5 11149 #define regPCIEMSIX_VECT12_CONTROL 0x1c033 11150 #define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 5 11151 #define regPCIEMSIX_VECT13_ADDR_LO 0x1c034 11152 #define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 5 11153 #define regPCIEMSIX_VECT13_ADDR_HI 0x1c035 11154 #define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 5 11155 #define regPCIEMSIX_VECT13_MSG_DATA 0x1c036 11156 #define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 5 11157 #define regPCIEMSIX_VECT13_CONTROL 0x1c037 11158 #define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 5 11159 #define regPCIEMSIX_VECT14_ADDR_LO 0x1c038 11160 #define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 5 11161 #define regPCIEMSIX_VECT14_ADDR_HI 0x1c039 11162 #define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 5 11163 #define regPCIEMSIX_VECT14_MSG_DATA 0x1c03a 11164 #define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 5 11165 #define regPCIEMSIX_VECT14_CONTROL 0x1c03b 11166 #define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 5 11167 #define regPCIEMSIX_VECT15_ADDR_LO 0x1c03c 11168 #define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 5 11169 #define regPCIEMSIX_VECT15_ADDR_HI 0x1c03d 11170 #define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 5 11171 #define regPCIEMSIX_VECT15_MSG_DATA 0x1c03e 11172 #define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 5 11173 #define regPCIEMSIX_VECT15_CONTROL 0x1c03f 11174 #define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 5 11175 #define regPCIEMSIX_VECT16_ADDR_LO 0x1c040 11176 #define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 5 11177 #define regPCIEMSIX_VECT16_ADDR_HI 0x1c041 11178 #define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 5 11179 #define regPCIEMSIX_VECT16_MSG_DATA 0x1c042 11180 #define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 5 11181 #define regPCIEMSIX_VECT16_CONTROL 0x1c043 11182 #define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 5 11183 #define regPCIEMSIX_VECT17_ADDR_LO 0x1c044 11184 #define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 5 11185 #define regPCIEMSIX_VECT17_ADDR_HI 0x1c045 11186 #define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 5 11187 #define regPCIEMSIX_VECT17_MSG_DATA 0x1c046 11188 #define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 5 11189 #define regPCIEMSIX_VECT17_CONTROL 0x1c047 11190 #define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 5 11191 #define regPCIEMSIX_VECT18_ADDR_LO 0x1c048 11192 #define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 5 11193 #define regPCIEMSIX_VECT18_ADDR_HI 0x1c049 11194 #define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 5 11195 #define regPCIEMSIX_VECT18_MSG_DATA 0x1c04a 11196 #define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 5 11197 #define regPCIEMSIX_VECT18_CONTROL 0x1c04b 11198 #define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 5 11199 #define regPCIEMSIX_VECT19_ADDR_LO 0x1c04c 11200 #define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 5 11201 #define regPCIEMSIX_VECT19_ADDR_HI 0x1c04d 11202 #define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 5 11203 #define regPCIEMSIX_VECT19_MSG_DATA 0x1c04e 11204 #define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 5 11205 #define regPCIEMSIX_VECT19_CONTROL 0x1c04f 11206 #define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 5 11207 #define regPCIEMSIX_VECT20_ADDR_LO 0x1c050 11208 #define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 5 11209 #define regPCIEMSIX_VECT20_ADDR_HI 0x1c051 11210 #define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 5 11211 #define regPCIEMSIX_VECT20_MSG_DATA 0x1c052 11212 #define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 5 11213 #define regPCIEMSIX_VECT20_CONTROL 0x1c053 11214 #define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 5 11215 #define regPCIEMSIX_VECT21_ADDR_LO 0x1c054 11216 #define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 5 11217 #define regPCIEMSIX_VECT21_ADDR_HI 0x1c055 11218 #define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 5 11219 #define regPCIEMSIX_VECT21_MSG_DATA 0x1c056 11220 #define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 5 11221 #define regPCIEMSIX_VECT21_CONTROL 0x1c057 11222 #define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 5 11223 #define regPCIEMSIX_VECT22_ADDR_LO 0x1c058 11224 #define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 5 11225 #define regPCIEMSIX_VECT22_ADDR_HI 0x1c059 11226 #define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 5 11227 #define regPCIEMSIX_VECT22_MSG_DATA 0x1c05a 11228 #define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 5 11229 #define regPCIEMSIX_VECT22_CONTROL 0x1c05b 11230 #define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 5 11231 #define regPCIEMSIX_VECT23_ADDR_LO 0x1c05c 11232 #define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 5 11233 #define regPCIEMSIX_VECT23_ADDR_HI 0x1c05d 11234 #define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 5 11235 #define regPCIEMSIX_VECT23_MSG_DATA 0x1c05e 11236 #define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 5 11237 #define regPCIEMSIX_VECT23_CONTROL 0x1c05f 11238 #define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 5 11239 #define regPCIEMSIX_VECT24_ADDR_LO 0x1c060 11240 #define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 5 11241 #define regPCIEMSIX_VECT24_ADDR_HI 0x1c061 11242 #define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 5 11243 #define regPCIEMSIX_VECT24_MSG_DATA 0x1c062 11244 #define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 5 11245 #define regPCIEMSIX_VECT24_CONTROL 0x1c063 11246 #define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 5 11247 #define regPCIEMSIX_VECT25_ADDR_LO 0x1c064 11248 #define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 5 11249 #define regPCIEMSIX_VECT25_ADDR_HI 0x1c065 11250 #define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 5 11251 #define regPCIEMSIX_VECT25_MSG_DATA 0x1c066 11252 #define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 5 11253 #define regPCIEMSIX_VECT25_CONTROL 0x1c067 11254 #define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 5 11255 #define regPCIEMSIX_VECT26_ADDR_LO 0x1c068 11256 #define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 5 11257 #define regPCIEMSIX_VECT26_ADDR_HI 0x1c069 11258 #define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 5 11259 #define regPCIEMSIX_VECT26_MSG_DATA 0x1c06a 11260 #define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 5 11261 #define regPCIEMSIX_VECT26_CONTROL 0x1c06b 11262 #define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 5 11263 #define regPCIEMSIX_VECT27_ADDR_LO 0x1c06c 11264 #define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 5 11265 #define regPCIEMSIX_VECT27_ADDR_HI 0x1c06d 11266 #define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 5 11267 #define regPCIEMSIX_VECT27_MSG_DATA 0x1c06e 11268 #define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 5 11269 #define regPCIEMSIX_VECT27_CONTROL 0x1c06f 11270 #define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 5 11271 #define regPCIEMSIX_VECT28_ADDR_LO 0x1c070 11272 #define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 5 11273 #define regPCIEMSIX_VECT28_ADDR_HI 0x1c071 11274 #define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 5 11275 #define regPCIEMSIX_VECT28_MSG_DATA 0x1c072 11276 #define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 5 11277 #define regPCIEMSIX_VECT28_CONTROL 0x1c073 11278 #define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 5 11279 #define regPCIEMSIX_VECT29_ADDR_LO 0x1c074 11280 #define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 5 11281 #define regPCIEMSIX_VECT29_ADDR_HI 0x1c075 11282 #define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 5 11283 #define regPCIEMSIX_VECT29_MSG_DATA 0x1c076 11284 #define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 5 11285 #define regPCIEMSIX_VECT29_CONTROL 0x1c077 11286 #define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 5 11287 #define regPCIEMSIX_VECT30_ADDR_LO 0x1c078 11288 #define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 5 11289 #define regPCIEMSIX_VECT30_ADDR_HI 0x1c079 11290 #define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 5 11291 #define regPCIEMSIX_VECT30_MSG_DATA 0x1c07a 11292 #define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 5 11293 #define regPCIEMSIX_VECT30_CONTROL 0x1c07b 11294 #define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 5 11295 #define regPCIEMSIX_VECT31_ADDR_LO 0x1c07c 11296 #define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 5 11297 #define regPCIEMSIX_VECT31_ADDR_HI 0x1c07d 11298 #define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 5 11299 #define regPCIEMSIX_VECT31_MSG_DATA 0x1c07e 11300 #define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 5 11301 #define regPCIEMSIX_VECT31_CONTROL 0x1c07f 11302 #define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 5 11303 #define regPCIEMSIX_VECT32_ADDR_LO 0x1c080 11304 #define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 5 11305 #define regPCIEMSIX_VECT32_ADDR_HI 0x1c081 11306 #define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 5 11307 #define regPCIEMSIX_VECT32_MSG_DATA 0x1c082 11308 #define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 5 11309 #define regPCIEMSIX_VECT32_CONTROL 0x1c083 11310 #define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 5 11311 #define regPCIEMSIX_VECT33_ADDR_LO 0x1c084 11312 #define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 5 11313 #define regPCIEMSIX_VECT33_ADDR_HI 0x1c085 11314 #define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 5 11315 #define regPCIEMSIX_VECT33_MSG_DATA 0x1c086 11316 #define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 5 11317 #define regPCIEMSIX_VECT33_CONTROL 0x1c087 11318 #define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 5 11319 #define regPCIEMSIX_VECT34_ADDR_LO 0x1c088 11320 #define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 5 11321 #define regPCIEMSIX_VECT34_ADDR_HI 0x1c089 11322 #define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 5 11323 #define regPCIEMSIX_VECT34_MSG_DATA 0x1c08a 11324 #define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 5 11325 #define regPCIEMSIX_VECT34_CONTROL 0x1c08b 11326 #define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 5 11327 #define regPCIEMSIX_VECT35_ADDR_LO 0x1c08c 11328 #define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 5 11329 #define regPCIEMSIX_VECT35_ADDR_HI 0x1c08d 11330 #define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 5 11331 #define regPCIEMSIX_VECT35_MSG_DATA 0x1c08e 11332 #define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 5 11333 #define regPCIEMSIX_VECT35_CONTROL 0x1c08f 11334 #define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 5 11335 #define regPCIEMSIX_VECT36_ADDR_LO 0x1c090 11336 #define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 5 11337 #define regPCIEMSIX_VECT36_ADDR_HI 0x1c091 11338 #define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 5 11339 #define regPCIEMSIX_VECT36_MSG_DATA 0x1c092 11340 #define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 5 11341 #define regPCIEMSIX_VECT36_CONTROL 0x1c093 11342 #define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 5 11343 #define regPCIEMSIX_VECT37_ADDR_LO 0x1c094 11344 #define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 5 11345 #define regPCIEMSIX_VECT37_ADDR_HI 0x1c095 11346 #define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 5 11347 #define regPCIEMSIX_VECT37_MSG_DATA 0x1c096 11348 #define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 5 11349 #define regPCIEMSIX_VECT37_CONTROL 0x1c097 11350 #define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 5 11351 #define regPCIEMSIX_VECT38_ADDR_LO 0x1c098 11352 #define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 5 11353 #define regPCIEMSIX_VECT38_ADDR_HI 0x1c099 11354 #define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 5 11355 #define regPCIEMSIX_VECT38_MSG_DATA 0x1c09a 11356 #define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 5 11357 #define regPCIEMSIX_VECT38_CONTROL 0x1c09b 11358 #define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 5 11359 #define regPCIEMSIX_VECT39_ADDR_LO 0x1c09c 11360 #define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 5 11361 #define regPCIEMSIX_VECT39_ADDR_HI 0x1c09d 11362 #define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 5 11363 #define regPCIEMSIX_VECT39_MSG_DATA 0x1c09e 11364 #define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 5 11365 #define regPCIEMSIX_VECT39_CONTROL 0x1c09f 11366 #define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 5 11367 #define regPCIEMSIX_VECT40_ADDR_LO 0x1c0a0 11368 #define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 5 11369 #define regPCIEMSIX_VECT40_ADDR_HI 0x1c0a1 11370 #define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 5 11371 #define regPCIEMSIX_VECT40_MSG_DATA 0x1c0a2 11372 #define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 5 11373 #define regPCIEMSIX_VECT40_CONTROL 0x1c0a3 11374 #define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 5 11375 #define regPCIEMSIX_VECT41_ADDR_LO 0x1c0a4 11376 #define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 5 11377 #define regPCIEMSIX_VECT41_ADDR_HI 0x1c0a5 11378 #define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 5 11379 #define regPCIEMSIX_VECT41_MSG_DATA 0x1c0a6 11380 #define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 5 11381 #define regPCIEMSIX_VECT41_CONTROL 0x1c0a7 11382 #define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 5 11383 #define regPCIEMSIX_VECT42_ADDR_LO 0x1c0a8 11384 #define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 5 11385 #define regPCIEMSIX_VECT42_ADDR_HI 0x1c0a9 11386 #define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 5 11387 #define regPCIEMSIX_VECT42_MSG_DATA 0x1c0aa 11388 #define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 5 11389 #define regPCIEMSIX_VECT42_CONTROL 0x1c0ab 11390 #define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 5 11391 #define regPCIEMSIX_VECT43_ADDR_LO 0x1c0ac 11392 #define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 5 11393 #define regPCIEMSIX_VECT43_ADDR_HI 0x1c0ad 11394 #define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 5 11395 #define regPCIEMSIX_VECT43_MSG_DATA 0x1c0ae 11396 #define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 5 11397 #define regPCIEMSIX_VECT43_CONTROL 0x1c0af 11398 #define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 5 11399 #define regPCIEMSIX_VECT44_ADDR_LO 0x1c0b0 11400 #define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 5 11401 #define regPCIEMSIX_VECT44_ADDR_HI 0x1c0b1 11402 #define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 5 11403 #define regPCIEMSIX_VECT44_MSG_DATA 0x1c0b2 11404 #define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 5 11405 #define regPCIEMSIX_VECT44_CONTROL 0x1c0b3 11406 #define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 5 11407 #define regPCIEMSIX_VECT45_ADDR_LO 0x1c0b4 11408 #define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 5 11409 #define regPCIEMSIX_VECT45_ADDR_HI 0x1c0b5 11410 #define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 5 11411 #define regPCIEMSIX_VECT45_MSG_DATA 0x1c0b6 11412 #define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 5 11413 #define regPCIEMSIX_VECT45_CONTROL 0x1c0b7 11414 #define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 5 11415 #define regPCIEMSIX_VECT46_ADDR_LO 0x1c0b8 11416 #define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 5 11417 #define regPCIEMSIX_VECT46_ADDR_HI 0x1c0b9 11418 #define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 5 11419 #define regPCIEMSIX_VECT46_MSG_DATA 0x1c0ba 11420 #define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 5 11421 #define regPCIEMSIX_VECT46_CONTROL 0x1c0bb 11422 #define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 5 11423 #define regPCIEMSIX_VECT47_ADDR_LO 0x1c0bc 11424 #define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 5 11425 #define regPCIEMSIX_VECT47_ADDR_HI 0x1c0bd 11426 #define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 5 11427 #define regPCIEMSIX_VECT47_MSG_DATA 0x1c0be 11428 #define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 5 11429 #define regPCIEMSIX_VECT47_CONTROL 0x1c0bf 11430 #define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 5 11431 #define regPCIEMSIX_VECT48_ADDR_LO 0x1c0c0 11432 #define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 5 11433 #define regPCIEMSIX_VECT48_ADDR_HI 0x1c0c1 11434 #define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 5 11435 #define regPCIEMSIX_VECT48_MSG_DATA 0x1c0c2 11436 #define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 5 11437 #define regPCIEMSIX_VECT48_CONTROL 0x1c0c3 11438 #define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 5 11439 #define regPCIEMSIX_VECT49_ADDR_LO 0x1c0c4 11440 #define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 5 11441 #define regPCIEMSIX_VECT49_ADDR_HI 0x1c0c5 11442 #define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 5 11443 #define regPCIEMSIX_VECT49_MSG_DATA 0x1c0c6 11444 #define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 5 11445 #define regPCIEMSIX_VECT49_CONTROL 0x1c0c7 11446 #define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 5 11447 #define regPCIEMSIX_VECT50_ADDR_LO 0x1c0c8 11448 #define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 5 11449 #define regPCIEMSIX_VECT50_ADDR_HI 0x1c0c9 11450 #define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 5 11451 #define regPCIEMSIX_VECT50_MSG_DATA 0x1c0ca 11452 #define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 5 11453 #define regPCIEMSIX_VECT50_CONTROL 0x1c0cb 11454 #define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 5 11455 #define regPCIEMSIX_VECT51_ADDR_LO 0x1c0cc 11456 #define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 5 11457 #define regPCIEMSIX_VECT51_ADDR_HI 0x1c0cd 11458 #define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 5 11459 #define regPCIEMSIX_VECT51_MSG_DATA 0x1c0ce 11460 #define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 5 11461 #define regPCIEMSIX_VECT51_CONTROL 0x1c0cf 11462 #define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 5 11463 #define regPCIEMSIX_VECT52_ADDR_LO 0x1c0d0 11464 #define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 5 11465 #define regPCIEMSIX_VECT52_ADDR_HI 0x1c0d1 11466 #define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 5 11467 #define regPCIEMSIX_VECT52_MSG_DATA 0x1c0d2 11468 #define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 5 11469 #define regPCIEMSIX_VECT52_CONTROL 0x1c0d3 11470 #define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 5 11471 #define regPCIEMSIX_VECT53_ADDR_LO 0x1c0d4 11472 #define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 5 11473 #define regPCIEMSIX_VECT53_ADDR_HI 0x1c0d5 11474 #define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 5 11475 #define regPCIEMSIX_VECT53_MSG_DATA 0x1c0d6 11476 #define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 5 11477 #define regPCIEMSIX_VECT53_CONTROL 0x1c0d7 11478 #define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 5 11479 #define regPCIEMSIX_VECT54_ADDR_LO 0x1c0d8 11480 #define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 5 11481 #define regPCIEMSIX_VECT54_ADDR_HI 0x1c0d9 11482 #define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 5 11483 #define regPCIEMSIX_VECT54_MSG_DATA 0x1c0da 11484 #define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 5 11485 #define regPCIEMSIX_VECT54_CONTROL 0x1c0db 11486 #define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 5 11487 #define regPCIEMSIX_VECT55_ADDR_LO 0x1c0dc 11488 #define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 5 11489 #define regPCIEMSIX_VECT55_ADDR_HI 0x1c0dd 11490 #define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 5 11491 #define regPCIEMSIX_VECT55_MSG_DATA 0x1c0de 11492 #define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 5 11493 #define regPCIEMSIX_VECT55_CONTROL 0x1c0df 11494 #define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 5 11495 #define regPCIEMSIX_VECT56_ADDR_LO 0x1c0e0 11496 #define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 5 11497 #define regPCIEMSIX_VECT56_ADDR_HI 0x1c0e1 11498 #define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 5 11499 #define regPCIEMSIX_VECT56_MSG_DATA 0x1c0e2 11500 #define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 5 11501 #define regPCIEMSIX_VECT56_CONTROL 0x1c0e3 11502 #define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 5 11503 #define regPCIEMSIX_VECT57_ADDR_LO 0x1c0e4 11504 #define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 5 11505 #define regPCIEMSIX_VECT57_ADDR_HI 0x1c0e5 11506 #define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 5 11507 #define regPCIEMSIX_VECT57_MSG_DATA 0x1c0e6 11508 #define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 5 11509 #define regPCIEMSIX_VECT57_CONTROL 0x1c0e7 11510 #define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 5 11511 #define regPCIEMSIX_VECT58_ADDR_LO 0x1c0e8 11512 #define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 5 11513 #define regPCIEMSIX_VECT58_ADDR_HI 0x1c0e9 11514 #define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 5 11515 #define regPCIEMSIX_VECT58_MSG_DATA 0x1c0ea 11516 #define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 5 11517 #define regPCIEMSIX_VECT58_CONTROL 0x1c0eb 11518 #define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 5 11519 #define regPCIEMSIX_VECT59_ADDR_LO 0x1c0ec 11520 #define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 5 11521 #define regPCIEMSIX_VECT59_ADDR_HI 0x1c0ed 11522 #define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 5 11523 #define regPCIEMSIX_VECT59_MSG_DATA 0x1c0ee 11524 #define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 5 11525 #define regPCIEMSIX_VECT59_CONTROL 0x1c0ef 11526 #define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 5 11527 #define regPCIEMSIX_VECT60_ADDR_LO 0x1c0f0 11528 #define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 5 11529 #define regPCIEMSIX_VECT60_ADDR_HI 0x1c0f1 11530 #define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 5 11531 #define regPCIEMSIX_VECT60_MSG_DATA 0x1c0f2 11532 #define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 5 11533 #define regPCIEMSIX_VECT60_CONTROL 0x1c0f3 11534 #define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 5 11535 #define regPCIEMSIX_VECT61_ADDR_LO 0x1c0f4 11536 #define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 5 11537 #define regPCIEMSIX_VECT61_ADDR_HI 0x1c0f5 11538 #define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 5 11539 #define regPCIEMSIX_VECT61_MSG_DATA 0x1c0f6 11540 #define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 5 11541 #define regPCIEMSIX_VECT61_CONTROL 0x1c0f7 11542 #define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 5 11543 #define regPCIEMSIX_VECT62_ADDR_LO 0x1c0f8 11544 #define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 5 11545 #define regPCIEMSIX_VECT62_ADDR_HI 0x1c0f9 11546 #define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 5 11547 #define regPCIEMSIX_VECT62_MSG_DATA 0x1c0fa 11548 #define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 5 11549 #define regPCIEMSIX_VECT62_CONTROL 0x1c0fb 11550 #define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 5 11551 #define regPCIEMSIX_VECT63_ADDR_LO 0x1c0fc 11552 #define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 5 11553 #define regPCIEMSIX_VECT63_ADDR_HI 0x1c0fd 11554 #define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 5 11555 #define regPCIEMSIX_VECT63_MSG_DATA 0x1c0fe 11556 #define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 5 11557 #define regPCIEMSIX_VECT63_CONTROL 0x1c0ff 11558 #define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 5 11559 #define regPCIEMSIX_VECT64_ADDR_LO 0x1c100 11560 #define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 5 11561 #define regPCIEMSIX_VECT64_ADDR_HI 0x1c101 11562 #define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 5 11563 #define regPCIEMSIX_VECT64_MSG_DATA 0x1c102 11564 #define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 5 11565 #define regPCIEMSIX_VECT64_CONTROL 0x1c103 11566 #define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 5 11567 #define regPCIEMSIX_VECT65_ADDR_LO 0x1c104 11568 #define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 5 11569 #define regPCIEMSIX_VECT65_ADDR_HI 0x1c105 11570 #define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 5 11571 #define regPCIEMSIX_VECT65_MSG_DATA 0x1c106 11572 #define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 5 11573 #define regPCIEMSIX_VECT65_CONTROL 0x1c107 11574 #define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 5 11575 #define regPCIEMSIX_VECT66_ADDR_LO 0x1c108 11576 #define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 5 11577 #define regPCIEMSIX_VECT66_ADDR_HI 0x1c109 11578 #define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 5 11579 #define regPCIEMSIX_VECT66_MSG_DATA 0x1c10a 11580 #define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 5 11581 #define regPCIEMSIX_VECT66_CONTROL 0x1c10b 11582 #define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 5 11583 #define regPCIEMSIX_VECT67_ADDR_LO 0x1c10c 11584 #define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 5 11585 #define regPCIEMSIX_VECT67_ADDR_HI 0x1c10d 11586 #define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 5 11587 #define regPCIEMSIX_VECT67_MSG_DATA 0x1c10e 11588 #define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 5 11589 #define regPCIEMSIX_VECT67_CONTROL 0x1c10f 11590 #define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 5 11591 #define regPCIEMSIX_VECT68_ADDR_LO 0x1c110 11592 #define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 5 11593 #define regPCIEMSIX_VECT68_ADDR_HI 0x1c111 11594 #define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 5 11595 #define regPCIEMSIX_VECT68_MSG_DATA 0x1c112 11596 #define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 5 11597 #define regPCIEMSIX_VECT68_CONTROL 0x1c113 11598 #define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 5 11599 #define regPCIEMSIX_VECT69_ADDR_LO 0x1c114 11600 #define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 5 11601 #define regPCIEMSIX_VECT69_ADDR_HI 0x1c115 11602 #define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 5 11603 #define regPCIEMSIX_VECT69_MSG_DATA 0x1c116 11604 #define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 5 11605 #define regPCIEMSIX_VECT69_CONTROL 0x1c117 11606 #define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 5 11607 #define regPCIEMSIX_VECT70_ADDR_LO 0x1c118 11608 #define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 5 11609 #define regPCIEMSIX_VECT70_ADDR_HI 0x1c119 11610 #define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 5 11611 #define regPCIEMSIX_VECT70_MSG_DATA 0x1c11a 11612 #define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 5 11613 #define regPCIEMSIX_VECT70_CONTROL 0x1c11b 11614 #define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 5 11615 #define regPCIEMSIX_VECT71_ADDR_LO 0x1c11c 11616 #define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 5 11617 #define regPCIEMSIX_VECT71_ADDR_HI 0x1c11d 11618 #define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 5 11619 #define regPCIEMSIX_VECT71_MSG_DATA 0x1c11e 11620 #define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 5 11621 #define regPCIEMSIX_VECT71_CONTROL 0x1c11f 11622 #define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 5 11623 #define regPCIEMSIX_VECT72_ADDR_LO 0x1c120 11624 #define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 5 11625 #define regPCIEMSIX_VECT72_ADDR_HI 0x1c121 11626 #define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 5 11627 #define regPCIEMSIX_VECT72_MSG_DATA 0x1c122 11628 #define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 5 11629 #define regPCIEMSIX_VECT72_CONTROL 0x1c123 11630 #define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 5 11631 #define regPCIEMSIX_VECT73_ADDR_LO 0x1c124 11632 #define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 5 11633 #define regPCIEMSIX_VECT73_ADDR_HI 0x1c125 11634 #define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 5 11635 #define regPCIEMSIX_VECT73_MSG_DATA 0x1c126 11636 #define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 5 11637 #define regPCIEMSIX_VECT73_CONTROL 0x1c127 11638 #define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 5 11639 #define regPCIEMSIX_VECT74_ADDR_LO 0x1c128 11640 #define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 5 11641 #define regPCIEMSIX_VECT74_ADDR_HI 0x1c129 11642 #define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 5 11643 #define regPCIEMSIX_VECT74_MSG_DATA 0x1c12a 11644 #define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 5 11645 #define regPCIEMSIX_VECT74_CONTROL 0x1c12b 11646 #define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 5 11647 #define regPCIEMSIX_VECT75_ADDR_LO 0x1c12c 11648 #define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 5 11649 #define regPCIEMSIX_VECT75_ADDR_HI 0x1c12d 11650 #define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 5 11651 #define regPCIEMSIX_VECT75_MSG_DATA 0x1c12e 11652 #define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 5 11653 #define regPCIEMSIX_VECT75_CONTROL 0x1c12f 11654 #define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 5 11655 #define regPCIEMSIX_VECT76_ADDR_LO 0x1c130 11656 #define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 5 11657 #define regPCIEMSIX_VECT76_ADDR_HI 0x1c131 11658 #define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 5 11659 #define regPCIEMSIX_VECT76_MSG_DATA 0x1c132 11660 #define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 5 11661 #define regPCIEMSIX_VECT76_CONTROL 0x1c133 11662 #define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 5 11663 #define regPCIEMSIX_VECT77_ADDR_LO 0x1c134 11664 #define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 5 11665 #define regPCIEMSIX_VECT77_ADDR_HI 0x1c135 11666 #define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 5 11667 #define regPCIEMSIX_VECT77_MSG_DATA 0x1c136 11668 #define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 5 11669 #define regPCIEMSIX_VECT77_CONTROL 0x1c137 11670 #define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 5 11671 #define regPCIEMSIX_VECT78_ADDR_LO 0x1c138 11672 #define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 5 11673 #define regPCIEMSIX_VECT78_ADDR_HI 0x1c139 11674 #define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 5 11675 #define regPCIEMSIX_VECT78_MSG_DATA 0x1c13a 11676 #define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 5 11677 #define regPCIEMSIX_VECT78_CONTROL 0x1c13b 11678 #define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 5 11679 #define regPCIEMSIX_VECT79_ADDR_LO 0x1c13c 11680 #define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 5 11681 #define regPCIEMSIX_VECT79_ADDR_HI 0x1c13d 11682 #define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 5 11683 #define regPCIEMSIX_VECT79_MSG_DATA 0x1c13e 11684 #define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 5 11685 #define regPCIEMSIX_VECT79_CONTROL 0x1c13f 11686 #define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 5 11687 #define regPCIEMSIX_VECT80_ADDR_LO 0x1c140 11688 #define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 5 11689 #define regPCIEMSIX_VECT80_ADDR_HI 0x1c141 11690 #define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 5 11691 #define regPCIEMSIX_VECT80_MSG_DATA 0x1c142 11692 #define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 5 11693 #define regPCIEMSIX_VECT80_CONTROL 0x1c143 11694 #define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 5 11695 #define regPCIEMSIX_VECT81_ADDR_LO 0x1c144 11696 #define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 5 11697 #define regPCIEMSIX_VECT81_ADDR_HI 0x1c145 11698 #define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 5 11699 #define regPCIEMSIX_VECT81_MSG_DATA 0x1c146 11700 #define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 5 11701 #define regPCIEMSIX_VECT81_CONTROL 0x1c147 11702 #define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 5 11703 #define regPCIEMSIX_VECT82_ADDR_LO 0x1c148 11704 #define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 5 11705 #define regPCIEMSIX_VECT82_ADDR_HI 0x1c149 11706 #define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 5 11707 #define regPCIEMSIX_VECT82_MSG_DATA 0x1c14a 11708 #define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 5 11709 #define regPCIEMSIX_VECT82_CONTROL 0x1c14b 11710 #define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 5 11711 #define regPCIEMSIX_VECT83_ADDR_LO 0x1c14c 11712 #define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 5 11713 #define regPCIEMSIX_VECT83_ADDR_HI 0x1c14d 11714 #define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 5 11715 #define regPCIEMSIX_VECT83_MSG_DATA 0x1c14e 11716 #define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 5 11717 #define regPCIEMSIX_VECT83_CONTROL 0x1c14f 11718 #define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 5 11719 #define regPCIEMSIX_VECT84_ADDR_LO 0x1c150 11720 #define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 5 11721 #define regPCIEMSIX_VECT84_ADDR_HI 0x1c151 11722 #define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 5 11723 #define regPCIEMSIX_VECT84_MSG_DATA 0x1c152 11724 #define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 5 11725 #define regPCIEMSIX_VECT84_CONTROL 0x1c153 11726 #define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 5 11727 #define regPCIEMSIX_VECT85_ADDR_LO 0x1c154 11728 #define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 5 11729 #define regPCIEMSIX_VECT85_ADDR_HI 0x1c155 11730 #define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 5 11731 #define regPCIEMSIX_VECT85_MSG_DATA 0x1c156 11732 #define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 5 11733 #define regPCIEMSIX_VECT85_CONTROL 0x1c157 11734 #define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 5 11735 #define regPCIEMSIX_VECT86_ADDR_LO 0x1c158 11736 #define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 5 11737 #define regPCIEMSIX_VECT86_ADDR_HI 0x1c159 11738 #define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 5 11739 #define regPCIEMSIX_VECT86_MSG_DATA 0x1c15a 11740 #define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 5 11741 #define regPCIEMSIX_VECT86_CONTROL 0x1c15b 11742 #define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 5 11743 #define regPCIEMSIX_VECT87_ADDR_LO 0x1c15c 11744 #define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 5 11745 #define regPCIEMSIX_VECT87_ADDR_HI 0x1c15d 11746 #define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 5 11747 #define regPCIEMSIX_VECT87_MSG_DATA 0x1c15e 11748 #define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 5 11749 #define regPCIEMSIX_VECT87_CONTROL 0x1c15f 11750 #define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 5 11751 #define regPCIEMSIX_VECT88_ADDR_LO 0x1c160 11752 #define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 5 11753 #define regPCIEMSIX_VECT88_ADDR_HI 0x1c161 11754 #define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 5 11755 #define regPCIEMSIX_VECT88_MSG_DATA 0x1c162 11756 #define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 5 11757 #define regPCIEMSIX_VECT88_CONTROL 0x1c163 11758 #define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 5 11759 #define regPCIEMSIX_VECT89_ADDR_LO 0x1c164 11760 #define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 5 11761 #define regPCIEMSIX_VECT89_ADDR_HI 0x1c165 11762 #define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 5 11763 #define regPCIEMSIX_VECT89_MSG_DATA 0x1c166 11764 #define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 5 11765 #define regPCIEMSIX_VECT89_CONTROL 0x1c167 11766 #define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 5 11767 #define regPCIEMSIX_VECT90_ADDR_LO 0x1c168 11768 #define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 5 11769 #define regPCIEMSIX_VECT90_ADDR_HI 0x1c169 11770 #define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 5 11771 #define regPCIEMSIX_VECT90_MSG_DATA 0x1c16a 11772 #define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 5 11773 #define regPCIEMSIX_VECT90_CONTROL 0x1c16b 11774 #define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 5 11775 #define regPCIEMSIX_VECT91_ADDR_LO 0x1c16c 11776 #define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 5 11777 #define regPCIEMSIX_VECT91_ADDR_HI 0x1c16d 11778 #define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 5 11779 #define regPCIEMSIX_VECT91_MSG_DATA 0x1c16e 11780 #define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 5 11781 #define regPCIEMSIX_VECT91_CONTROL 0x1c16f 11782 #define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 5 11783 #define regPCIEMSIX_VECT92_ADDR_LO 0x1c170 11784 #define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 5 11785 #define regPCIEMSIX_VECT92_ADDR_HI 0x1c171 11786 #define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 5 11787 #define regPCIEMSIX_VECT92_MSG_DATA 0x1c172 11788 #define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 5 11789 #define regPCIEMSIX_VECT92_CONTROL 0x1c173 11790 #define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 5 11791 #define regPCIEMSIX_VECT93_ADDR_LO 0x1c174 11792 #define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 5 11793 #define regPCIEMSIX_VECT93_ADDR_HI 0x1c175 11794 #define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 5 11795 #define regPCIEMSIX_VECT93_MSG_DATA 0x1c176 11796 #define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 5 11797 #define regPCIEMSIX_VECT93_CONTROL 0x1c177 11798 #define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 5 11799 #define regPCIEMSIX_VECT94_ADDR_LO 0x1c178 11800 #define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 5 11801 #define regPCIEMSIX_VECT94_ADDR_HI 0x1c179 11802 #define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 5 11803 #define regPCIEMSIX_VECT94_MSG_DATA 0x1c17a 11804 #define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 5 11805 #define regPCIEMSIX_VECT94_CONTROL 0x1c17b 11806 #define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 5 11807 #define regPCIEMSIX_VECT95_ADDR_LO 0x1c17c 11808 #define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 5 11809 #define regPCIEMSIX_VECT95_ADDR_HI 0x1c17d 11810 #define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 5 11811 #define regPCIEMSIX_VECT95_MSG_DATA 0x1c17e 11812 #define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 5 11813 #define regPCIEMSIX_VECT95_CONTROL 0x1c17f 11814 #define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 5 11815 #define regPCIEMSIX_VECT96_ADDR_LO 0x1c180 11816 #define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 5 11817 #define regPCIEMSIX_VECT96_ADDR_HI 0x1c181 11818 #define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 5 11819 #define regPCIEMSIX_VECT96_MSG_DATA 0x1c182 11820 #define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 5 11821 #define regPCIEMSIX_VECT96_CONTROL 0x1c183 11822 #define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 5 11823 #define regPCIEMSIX_VECT97_ADDR_LO 0x1c184 11824 #define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 5 11825 #define regPCIEMSIX_VECT97_ADDR_HI 0x1c185 11826 #define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 5 11827 #define regPCIEMSIX_VECT97_MSG_DATA 0x1c186 11828 #define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 5 11829 #define regPCIEMSIX_VECT97_CONTROL 0x1c187 11830 #define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 5 11831 #define regPCIEMSIX_VECT98_ADDR_LO 0x1c188 11832 #define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 5 11833 #define regPCIEMSIX_VECT98_ADDR_HI 0x1c189 11834 #define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 5 11835 #define regPCIEMSIX_VECT98_MSG_DATA 0x1c18a 11836 #define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 5 11837 #define regPCIEMSIX_VECT98_CONTROL 0x1c18b 11838 #define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 5 11839 #define regPCIEMSIX_VECT99_ADDR_LO 0x1c18c 11840 #define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 5 11841 #define regPCIEMSIX_VECT99_ADDR_HI 0x1c18d 11842 #define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 5 11843 #define regPCIEMSIX_VECT99_MSG_DATA 0x1c18e 11844 #define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 5 11845 #define regPCIEMSIX_VECT99_CONTROL 0x1c18f 11846 #define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 5 11847 #define regPCIEMSIX_VECT100_ADDR_LO 0x1c190 11848 #define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 5 11849 #define regPCIEMSIX_VECT100_ADDR_HI 0x1c191 11850 #define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 5 11851 #define regPCIEMSIX_VECT100_MSG_DATA 0x1c192 11852 #define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 5 11853 #define regPCIEMSIX_VECT100_CONTROL 0x1c193 11854 #define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 5 11855 #define regPCIEMSIX_VECT101_ADDR_LO 0x1c194 11856 #define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 5 11857 #define regPCIEMSIX_VECT101_ADDR_HI 0x1c195 11858 #define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 5 11859 #define regPCIEMSIX_VECT101_MSG_DATA 0x1c196 11860 #define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 5 11861 #define regPCIEMSIX_VECT101_CONTROL 0x1c197 11862 #define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 5 11863 #define regPCIEMSIX_VECT102_ADDR_LO 0x1c198 11864 #define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 5 11865 #define regPCIEMSIX_VECT102_ADDR_HI 0x1c199 11866 #define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 5 11867 #define regPCIEMSIX_VECT102_MSG_DATA 0x1c19a 11868 #define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 5 11869 #define regPCIEMSIX_VECT102_CONTROL 0x1c19b 11870 #define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 5 11871 #define regPCIEMSIX_VECT103_ADDR_LO 0x1c19c 11872 #define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 5 11873 #define regPCIEMSIX_VECT103_ADDR_HI 0x1c19d 11874 #define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 5 11875 #define regPCIEMSIX_VECT103_MSG_DATA 0x1c19e 11876 #define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 5 11877 #define regPCIEMSIX_VECT103_CONTROL 0x1c19f 11878 #define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 5 11879 #define regPCIEMSIX_VECT104_ADDR_LO 0x1c1a0 11880 #define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 5 11881 #define regPCIEMSIX_VECT104_ADDR_HI 0x1c1a1 11882 #define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 5 11883 #define regPCIEMSIX_VECT104_MSG_DATA 0x1c1a2 11884 #define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 5 11885 #define regPCIEMSIX_VECT104_CONTROL 0x1c1a3 11886 #define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 5 11887 #define regPCIEMSIX_VECT105_ADDR_LO 0x1c1a4 11888 #define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 5 11889 #define regPCIEMSIX_VECT105_ADDR_HI 0x1c1a5 11890 #define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 5 11891 #define regPCIEMSIX_VECT105_MSG_DATA 0x1c1a6 11892 #define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 5 11893 #define regPCIEMSIX_VECT105_CONTROL 0x1c1a7 11894 #define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 5 11895 #define regPCIEMSIX_VECT106_ADDR_LO 0x1c1a8 11896 #define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 5 11897 #define regPCIEMSIX_VECT106_ADDR_HI 0x1c1a9 11898 #define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 5 11899 #define regPCIEMSIX_VECT106_MSG_DATA 0x1c1aa 11900 #define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 5 11901 #define regPCIEMSIX_VECT106_CONTROL 0x1c1ab 11902 #define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 5 11903 #define regPCIEMSIX_VECT107_ADDR_LO 0x1c1ac 11904 #define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 5 11905 #define regPCIEMSIX_VECT107_ADDR_HI 0x1c1ad 11906 #define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 5 11907 #define regPCIEMSIX_VECT107_MSG_DATA 0x1c1ae 11908 #define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 5 11909 #define regPCIEMSIX_VECT107_CONTROL 0x1c1af 11910 #define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 5 11911 #define regPCIEMSIX_VECT108_ADDR_LO 0x1c1b0 11912 #define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 5 11913 #define regPCIEMSIX_VECT108_ADDR_HI 0x1c1b1 11914 #define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 5 11915 #define regPCIEMSIX_VECT108_MSG_DATA 0x1c1b2 11916 #define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 5 11917 #define regPCIEMSIX_VECT108_CONTROL 0x1c1b3 11918 #define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 5 11919 #define regPCIEMSIX_VECT109_ADDR_LO 0x1c1b4 11920 #define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 5 11921 #define regPCIEMSIX_VECT109_ADDR_HI 0x1c1b5 11922 #define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 5 11923 #define regPCIEMSIX_VECT109_MSG_DATA 0x1c1b6 11924 #define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 5 11925 #define regPCIEMSIX_VECT109_CONTROL 0x1c1b7 11926 #define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 5 11927 #define regPCIEMSIX_VECT110_ADDR_LO 0x1c1b8 11928 #define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 5 11929 #define regPCIEMSIX_VECT110_ADDR_HI 0x1c1b9 11930 #define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 5 11931 #define regPCIEMSIX_VECT110_MSG_DATA 0x1c1ba 11932 #define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 5 11933 #define regPCIEMSIX_VECT110_CONTROL 0x1c1bb 11934 #define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 5 11935 #define regPCIEMSIX_VECT111_ADDR_LO 0x1c1bc 11936 #define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 5 11937 #define regPCIEMSIX_VECT111_ADDR_HI 0x1c1bd 11938 #define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 5 11939 #define regPCIEMSIX_VECT111_MSG_DATA 0x1c1be 11940 #define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 5 11941 #define regPCIEMSIX_VECT111_CONTROL 0x1c1bf 11942 #define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 5 11943 #define regPCIEMSIX_VECT112_ADDR_LO 0x1c1c0 11944 #define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 5 11945 #define regPCIEMSIX_VECT112_ADDR_HI 0x1c1c1 11946 #define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 5 11947 #define regPCIEMSIX_VECT112_MSG_DATA 0x1c1c2 11948 #define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 5 11949 #define regPCIEMSIX_VECT112_CONTROL 0x1c1c3 11950 #define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 5 11951 #define regPCIEMSIX_VECT113_ADDR_LO 0x1c1c4 11952 #define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 5 11953 #define regPCIEMSIX_VECT113_ADDR_HI 0x1c1c5 11954 #define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 5 11955 #define regPCIEMSIX_VECT113_MSG_DATA 0x1c1c6 11956 #define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 5 11957 #define regPCIEMSIX_VECT113_CONTROL 0x1c1c7 11958 #define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 5 11959 #define regPCIEMSIX_VECT114_ADDR_LO 0x1c1c8 11960 #define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 5 11961 #define regPCIEMSIX_VECT114_ADDR_HI 0x1c1c9 11962 #define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 5 11963 #define regPCIEMSIX_VECT114_MSG_DATA 0x1c1ca 11964 #define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 5 11965 #define regPCIEMSIX_VECT114_CONTROL 0x1c1cb 11966 #define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 5 11967 #define regPCIEMSIX_VECT115_ADDR_LO 0x1c1cc 11968 #define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 5 11969 #define regPCIEMSIX_VECT115_ADDR_HI 0x1c1cd 11970 #define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 5 11971 #define regPCIEMSIX_VECT115_MSG_DATA 0x1c1ce 11972 #define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 5 11973 #define regPCIEMSIX_VECT115_CONTROL 0x1c1cf 11974 #define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 5 11975 #define regPCIEMSIX_VECT116_ADDR_LO 0x1c1d0 11976 #define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 5 11977 #define regPCIEMSIX_VECT116_ADDR_HI 0x1c1d1 11978 #define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 5 11979 #define regPCIEMSIX_VECT116_MSG_DATA 0x1c1d2 11980 #define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 5 11981 #define regPCIEMSIX_VECT116_CONTROL 0x1c1d3 11982 #define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 5 11983 #define regPCIEMSIX_VECT117_ADDR_LO 0x1c1d4 11984 #define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 5 11985 #define regPCIEMSIX_VECT117_ADDR_HI 0x1c1d5 11986 #define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 5 11987 #define regPCIEMSIX_VECT117_MSG_DATA 0x1c1d6 11988 #define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 5 11989 #define regPCIEMSIX_VECT117_CONTROL 0x1c1d7 11990 #define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 5 11991 #define regPCIEMSIX_VECT118_ADDR_LO 0x1c1d8 11992 #define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 5 11993 #define regPCIEMSIX_VECT118_ADDR_HI 0x1c1d9 11994 #define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 5 11995 #define regPCIEMSIX_VECT118_MSG_DATA 0x1c1da 11996 #define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 5 11997 #define regPCIEMSIX_VECT118_CONTROL 0x1c1db 11998 #define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 5 11999 #define regPCIEMSIX_VECT119_ADDR_LO 0x1c1dc 12000 #define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 5 12001 #define regPCIEMSIX_VECT119_ADDR_HI 0x1c1dd 12002 #define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 5 12003 #define regPCIEMSIX_VECT119_MSG_DATA 0x1c1de 12004 #define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 5 12005 #define regPCIEMSIX_VECT119_CONTROL 0x1c1df 12006 #define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 5 12007 #define regPCIEMSIX_VECT120_ADDR_LO 0x1c1e0 12008 #define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 5 12009 #define regPCIEMSIX_VECT120_ADDR_HI 0x1c1e1 12010 #define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 5 12011 #define regPCIEMSIX_VECT120_MSG_DATA 0x1c1e2 12012 #define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 5 12013 #define regPCIEMSIX_VECT120_CONTROL 0x1c1e3 12014 #define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 5 12015 #define regPCIEMSIX_VECT121_ADDR_LO 0x1c1e4 12016 #define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 5 12017 #define regPCIEMSIX_VECT121_ADDR_HI 0x1c1e5 12018 #define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 5 12019 #define regPCIEMSIX_VECT121_MSG_DATA 0x1c1e6 12020 #define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 5 12021 #define regPCIEMSIX_VECT121_CONTROL 0x1c1e7 12022 #define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 5 12023 #define regPCIEMSIX_VECT122_ADDR_LO 0x1c1e8 12024 #define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 5 12025 #define regPCIEMSIX_VECT122_ADDR_HI 0x1c1e9 12026 #define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 5 12027 #define regPCIEMSIX_VECT122_MSG_DATA 0x1c1ea 12028 #define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 5 12029 #define regPCIEMSIX_VECT122_CONTROL 0x1c1eb 12030 #define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 5 12031 #define regPCIEMSIX_VECT123_ADDR_LO 0x1c1ec 12032 #define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 5 12033 #define regPCIEMSIX_VECT123_ADDR_HI 0x1c1ed 12034 #define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 5 12035 #define regPCIEMSIX_VECT123_MSG_DATA 0x1c1ee 12036 #define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 5 12037 #define regPCIEMSIX_VECT123_CONTROL 0x1c1ef 12038 #define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 5 12039 #define regPCIEMSIX_VECT124_ADDR_LO 0x1c1f0 12040 #define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 5 12041 #define regPCIEMSIX_VECT124_ADDR_HI 0x1c1f1 12042 #define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 5 12043 #define regPCIEMSIX_VECT124_MSG_DATA 0x1c1f2 12044 #define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 5 12045 #define regPCIEMSIX_VECT124_CONTROL 0x1c1f3 12046 #define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 5 12047 #define regPCIEMSIX_VECT125_ADDR_LO 0x1c1f4 12048 #define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 5 12049 #define regPCIEMSIX_VECT125_ADDR_HI 0x1c1f5 12050 #define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 5 12051 #define regPCIEMSIX_VECT125_MSG_DATA 0x1c1f6 12052 #define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 5 12053 #define regPCIEMSIX_VECT125_CONTROL 0x1c1f7 12054 #define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 5 12055 #define regPCIEMSIX_VECT126_ADDR_LO 0x1c1f8 12056 #define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 5 12057 #define regPCIEMSIX_VECT126_ADDR_HI 0x1c1f9 12058 #define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 5 12059 #define regPCIEMSIX_VECT126_MSG_DATA 0x1c1fa 12060 #define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 5 12061 #define regPCIEMSIX_VECT126_CONTROL 0x1c1fb 12062 #define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 5 12063 #define regPCIEMSIX_VECT127_ADDR_LO 0x1c1fc 12064 #define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 5 12065 #define regPCIEMSIX_VECT127_ADDR_HI 0x1c1fd 12066 #define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 5 12067 #define regPCIEMSIX_VECT127_MSG_DATA 0x1c1fe 12068 #define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 5 12069 #define regPCIEMSIX_VECT127_CONTROL 0x1c1ff 12070 #define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 5 12071 #define regPCIEMSIX_VECT128_ADDR_LO 0x1c200 12072 #define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 5 12073 #define regPCIEMSIX_VECT128_ADDR_HI 0x1c201 12074 #define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 5 12075 #define regPCIEMSIX_VECT128_MSG_DATA 0x1c202 12076 #define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 5 12077 #define regPCIEMSIX_VECT128_CONTROL 0x1c203 12078 #define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 5 12079 #define regPCIEMSIX_VECT129_ADDR_LO 0x1c204 12080 #define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 5 12081 #define regPCIEMSIX_VECT129_ADDR_HI 0x1c205 12082 #define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 5 12083 #define regPCIEMSIX_VECT129_MSG_DATA 0x1c206 12084 #define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 5 12085 #define regPCIEMSIX_VECT129_CONTROL 0x1c207 12086 #define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 5 12087 #define regPCIEMSIX_VECT130_ADDR_LO 0x1c208 12088 #define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 5 12089 #define regPCIEMSIX_VECT130_ADDR_HI 0x1c209 12090 #define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 5 12091 #define regPCIEMSIX_VECT130_MSG_DATA 0x1c20a 12092 #define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 5 12093 #define regPCIEMSIX_VECT130_CONTROL 0x1c20b 12094 #define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 5 12095 #define regPCIEMSIX_VECT131_ADDR_LO 0x1c20c 12096 #define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 5 12097 #define regPCIEMSIX_VECT131_ADDR_HI 0x1c20d 12098 #define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 5 12099 #define regPCIEMSIX_VECT131_MSG_DATA 0x1c20e 12100 #define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 5 12101 #define regPCIEMSIX_VECT131_CONTROL 0x1c20f 12102 #define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 5 12103 #define regPCIEMSIX_VECT132_ADDR_LO 0x1c210 12104 #define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 5 12105 #define regPCIEMSIX_VECT132_ADDR_HI 0x1c211 12106 #define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 5 12107 #define regPCIEMSIX_VECT132_MSG_DATA 0x1c212 12108 #define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 5 12109 #define regPCIEMSIX_VECT132_CONTROL 0x1c213 12110 #define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 5 12111 #define regPCIEMSIX_VECT133_ADDR_LO 0x1c214 12112 #define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 5 12113 #define regPCIEMSIX_VECT133_ADDR_HI 0x1c215 12114 #define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 5 12115 #define regPCIEMSIX_VECT133_MSG_DATA 0x1c216 12116 #define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 5 12117 #define regPCIEMSIX_VECT133_CONTROL 0x1c217 12118 #define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 5 12119 #define regPCIEMSIX_VECT134_ADDR_LO 0x1c218 12120 #define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 5 12121 #define regPCIEMSIX_VECT134_ADDR_HI 0x1c219 12122 #define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 5 12123 #define regPCIEMSIX_VECT134_MSG_DATA 0x1c21a 12124 #define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 5 12125 #define regPCIEMSIX_VECT134_CONTROL 0x1c21b 12126 #define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 5 12127 #define regPCIEMSIX_VECT135_ADDR_LO 0x1c21c 12128 #define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 5 12129 #define regPCIEMSIX_VECT135_ADDR_HI 0x1c21d 12130 #define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 5 12131 #define regPCIEMSIX_VECT135_MSG_DATA 0x1c21e 12132 #define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 5 12133 #define regPCIEMSIX_VECT135_CONTROL 0x1c21f 12134 #define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 5 12135 #define regPCIEMSIX_VECT136_ADDR_LO 0x1c220 12136 #define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 5 12137 #define regPCIEMSIX_VECT136_ADDR_HI 0x1c221 12138 #define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 5 12139 #define regPCIEMSIX_VECT136_MSG_DATA 0x1c222 12140 #define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 5 12141 #define regPCIEMSIX_VECT136_CONTROL 0x1c223 12142 #define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 5 12143 #define regPCIEMSIX_VECT137_ADDR_LO 0x1c224 12144 #define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 5 12145 #define regPCIEMSIX_VECT137_ADDR_HI 0x1c225 12146 #define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 5 12147 #define regPCIEMSIX_VECT137_MSG_DATA 0x1c226 12148 #define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 5 12149 #define regPCIEMSIX_VECT137_CONTROL 0x1c227 12150 #define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 5 12151 #define regPCIEMSIX_VECT138_ADDR_LO 0x1c228 12152 #define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 5 12153 #define regPCIEMSIX_VECT138_ADDR_HI 0x1c229 12154 #define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 5 12155 #define regPCIEMSIX_VECT138_MSG_DATA 0x1c22a 12156 #define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 5 12157 #define regPCIEMSIX_VECT138_CONTROL 0x1c22b 12158 #define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 5 12159 #define regPCIEMSIX_VECT139_ADDR_LO 0x1c22c 12160 #define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 5 12161 #define regPCIEMSIX_VECT139_ADDR_HI 0x1c22d 12162 #define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 5 12163 #define regPCIEMSIX_VECT139_MSG_DATA 0x1c22e 12164 #define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 5 12165 #define regPCIEMSIX_VECT139_CONTROL 0x1c22f 12166 #define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 5 12167 #define regPCIEMSIX_VECT140_ADDR_LO 0x1c230 12168 #define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 5 12169 #define regPCIEMSIX_VECT140_ADDR_HI 0x1c231 12170 #define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 5 12171 #define regPCIEMSIX_VECT140_MSG_DATA 0x1c232 12172 #define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 5 12173 #define regPCIEMSIX_VECT140_CONTROL 0x1c233 12174 #define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 5 12175 #define regPCIEMSIX_VECT141_ADDR_LO 0x1c234 12176 #define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 5 12177 #define regPCIEMSIX_VECT141_ADDR_HI 0x1c235 12178 #define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 5 12179 #define regPCIEMSIX_VECT141_MSG_DATA 0x1c236 12180 #define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 5 12181 #define regPCIEMSIX_VECT141_CONTROL 0x1c237 12182 #define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 5 12183 #define regPCIEMSIX_VECT142_ADDR_LO 0x1c238 12184 #define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 5 12185 #define regPCIEMSIX_VECT142_ADDR_HI 0x1c239 12186 #define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 5 12187 #define regPCIEMSIX_VECT142_MSG_DATA 0x1c23a 12188 #define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 5 12189 #define regPCIEMSIX_VECT142_CONTROL 0x1c23b 12190 #define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 5 12191 #define regPCIEMSIX_VECT143_ADDR_LO 0x1c23c 12192 #define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 5 12193 #define regPCIEMSIX_VECT143_ADDR_HI 0x1c23d 12194 #define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 5 12195 #define regPCIEMSIX_VECT143_MSG_DATA 0x1c23e 12196 #define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 5 12197 #define regPCIEMSIX_VECT143_CONTROL 0x1c23f 12198 #define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 5 12199 #define regPCIEMSIX_VECT144_ADDR_LO 0x1c240 12200 #define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 5 12201 #define regPCIEMSIX_VECT144_ADDR_HI 0x1c241 12202 #define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 5 12203 #define regPCIEMSIX_VECT144_MSG_DATA 0x1c242 12204 #define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 5 12205 #define regPCIEMSIX_VECT144_CONTROL 0x1c243 12206 #define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 5 12207 #define regPCIEMSIX_VECT145_ADDR_LO 0x1c244 12208 #define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 5 12209 #define regPCIEMSIX_VECT145_ADDR_HI 0x1c245 12210 #define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 5 12211 #define regPCIEMSIX_VECT145_MSG_DATA 0x1c246 12212 #define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 5 12213 #define regPCIEMSIX_VECT145_CONTROL 0x1c247 12214 #define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 5 12215 #define regPCIEMSIX_VECT146_ADDR_LO 0x1c248 12216 #define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 5 12217 #define regPCIEMSIX_VECT146_ADDR_HI 0x1c249 12218 #define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 5 12219 #define regPCIEMSIX_VECT146_MSG_DATA 0x1c24a 12220 #define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 5 12221 #define regPCIEMSIX_VECT146_CONTROL 0x1c24b 12222 #define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 5 12223 #define regPCIEMSIX_VECT147_ADDR_LO 0x1c24c 12224 #define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 5 12225 #define regPCIEMSIX_VECT147_ADDR_HI 0x1c24d 12226 #define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 5 12227 #define regPCIEMSIX_VECT147_MSG_DATA 0x1c24e 12228 #define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 5 12229 #define regPCIEMSIX_VECT147_CONTROL 0x1c24f 12230 #define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 5 12231 #define regPCIEMSIX_VECT148_ADDR_LO 0x1c250 12232 #define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 5 12233 #define regPCIEMSIX_VECT148_ADDR_HI 0x1c251 12234 #define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 5 12235 #define regPCIEMSIX_VECT148_MSG_DATA 0x1c252 12236 #define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 5 12237 #define regPCIEMSIX_VECT148_CONTROL 0x1c253 12238 #define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 5 12239 #define regPCIEMSIX_VECT149_ADDR_LO 0x1c254 12240 #define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 5 12241 #define regPCIEMSIX_VECT149_ADDR_HI 0x1c255 12242 #define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 5 12243 #define regPCIEMSIX_VECT149_MSG_DATA 0x1c256 12244 #define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 5 12245 #define regPCIEMSIX_VECT149_CONTROL 0x1c257 12246 #define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 5 12247 #define regPCIEMSIX_VECT150_ADDR_LO 0x1c258 12248 #define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 5 12249 #define regPCIEMSIX_VECT150_ADDR_HI 0x1c259 12250 #define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 5 12251 #define regPCIEMSIX_VECT150_MSG_DATA 0x1c25a 12252 #define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 5 12253 #define regPCIEMSIX_VECT150_CONTROL 0x1c25b 12254 #define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 5 12255 #define regPCIEMSIX_VECT151_ADDR_LO 0x1c25c 12256 #define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 5 12257 #define regPCIEMSIX_VECT151_ADDR_HI 0x1c25d 12258 #define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 5 12259 #define regPCIEMSIX_VECT151_MSG_DATA 0x1c25e 12260 #define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 5 12261 #define regPCIEMSIX_VECT151_CONTROL 0x1c25f 12262 #define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 5 12263 #define regPCIEMSIX_VECT152_ADDR_LO 0x1c260 12264 #define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 5 12265 #define regPCIEMSIX_VECT152_ADDR_HI 0x1c261 12266 #define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 5 12267 #define regPCIEMSIX_VECT152_MSG_DATA 0x1c262 12268 #define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 5 12269 #define regPCIEMSIX_VECT152_CONTROL 0x1c263 12270 #define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 5 12271 #define regPCIEMSIX_VECT153_ADDR_LO 0x1c264 12272 #define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 5 12273 #define regPCIEMSIX_VECT153_ADDR_HI 0x1c265 12274 #define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 5 12275 #define regPCIEMSIX_VECT153_MSG_DATA 0x1c266 12276 #define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 5 12277 #define regPCIEMSIX_VECT153_CONTROL 0x1c267 12278 #define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 5 12279 #define regPCIEMSIX_VECT154_ADDR_LO 0x1c268 12280 #define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 5 12281 #define regPCIEMSIX_VECT154_ADDR_HI 0x1c269 12282 #define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 5 12283 #define regPCIEMSIX_VECT154_MSG_DATA 0x1c26a 12284 #define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 5 12285 #define regPCIEMSIX_VECT154_CONTROL 0x1c26b 12286 #define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 5 12287 #define regPCIEMSIX_VECT155_ADDR_LO 0x1c26c 12288 #define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 5 12289 #define regPCIEMSIX_VECT155_ADDR_HI 0x1c26d 12290 #define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 5 12291 #define regPCIEMSIX_VECT155_MSG_DATA 0x1c26e 12292 #define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 5 12293 #define regPCIEMSIX_VECT155_CONTROL 0x1c26f 12294 #define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 5 12295 #define regPCIEMSIX_VECT156_ADDR_LO 0x1c270 12296 #define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 5 12297 #define regPCIEMSIX_VECT156_ADDR_HI 0x1c271 12298 #define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 5 12299 #define regPCIEMSIX_VECT156_MSG_DATA 0x1c272 12300 #define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 5 12301 #define regPCIEMSIX_VECT156_CONTROL 0x1c273 12302 #define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 5 12303 #define regPCIEMSIX_VECT157_ADDR_LO 0x1c274 12304 #define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 5 12305 #define regPCIEMSIX_VECT157_ADDR_HI 0x1c275 12306 #define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 5 12307 #define regPCIEMSIX_VECT157_MSG_DATA 0x1c276 12308 #define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 5 12309 #define regPCIEMSIX_VECT157_CONTROL 0x1c277 12310 #define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 5 12311 #define regPCIEMSIX_VECT158_ADDR_LO 0x1c278 12312 #define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 5 12313 #define regPCIEMSIX_VECT158_ADDR_HI 0x1c279 12314 #define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 5 12315 #define regPCIEMSIX_VECT158_MSG_DATA 0x1c27a 12316 #define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 5 12317 #define regPCIEMSIX_VECT158_CONTROL 0x1c27b 12318 #define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 5 12319 #define regPCIEMSIX_VECT159_ADDR_LO 0x1c27c 12320 #define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 5 12321 #define regPCIEMSIX_VECT159_ADDR_HI 0x1c27d 12322 #define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 5 12323 #define regPCIEMSIX_VECT159_MSG_DATA 0x1c27e 12324 #define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 5 12325 #define regPCIEMSIX_VECT159_CONTROL 0x1c27f 12326 #define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 5 12327 #define regPCIEMSIX_VECT160_ADDR_LO 0x1c280 12328 #define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 5 12329 #define regPCIEMSIX_VECT160_ADDR_HI 0x1c281 12330 #define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 5 12331 #define regPCIEMSIX_VECT160_MSG_DATA 0x1c282 12332 #define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 5 12333 #define regPCIEMSIX_VECT160_CONTROL 0x1c283 12334 #define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 5 12335 #define regPCIEMSIX_VECT161_ADDR_LO 0x1c284 12336 #define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 5 12337 #define regPCIEMSIX_VECT161_ADDR_HI 0x1c285 12338 #define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 5 12339 #define regPCIEMSIX_VECT161_MSG_DATA 0x1c286 12340 #define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 5 12341 #define regPCIEMSIX_VECT161_CONTROL 0x1c287 12342 #define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 5 12343 #define regPCIEMSIX_VECT162_ADDR_LO 0x1c288 12344 #define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 5 12345 #define regPCIEMSIX_VECT162_ADDR_HI 0x1c289 12346 #define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 5 12347 #define regPCIEMSIX_VECT162_MSG_DATA 0x1c28a 12348 #define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 5 12349 #define regPCIEMSIX_VECT162_CONTROL 0x1c28b 12350 #define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 5 12351 #define regPCIEMSIX_VECT163_ADDR_LO 0x1c28c 12352 #define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 5 12353 #define regPCIEMSIX_VECT163_ADDR_HI 0x1c28d 12354 #define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 5 12355 #define regPCIEMSIX_VECT163_MSG_DATA 0x1c28e 12356 #define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 5 12357 #define regPCIEMSIX_VECT163_CONTROL 0x1c28f 12358 #define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 5 12359 #define regPCIEMSIX_VECT164_ADDR_LO 0x1c290 12360 #define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 5 12361 #define regPCIEMSIX_VECT164_ADDR_HI 0x1c291 12362 #define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 5 12363 #define regPCIEMSIX_VECT164_MSG_DATA 0x1c292 12364 #define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 5 12365 #define regPCIEMSIX_VECT164_CONTROL 0x1c293 12366 #define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 5 12367 #define regPCIEMSIX_VECT165_ADDR_LO 0x1c294 12368 #define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 5 12369 #define regPCIEMSIX_VECT165_ADDR_HI 0x1c295 12370 #define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 5 12371 #define regPCIEMSIX_VECT165_MSG_DATA 0x1c296 12372 #define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 5 12373 #define regPCIEMSIX_VECT165_CONTROL 0x1c297 12374 #define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 5 12375 #define regPCIEMSIX_VECT166_ADDR_LO 0x1c298 12376 #define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 5 12377 #define regPCIEMSIX_VECT166_ADDR_HI 0x1c299 12378 #define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 5 12379 #define regPCIEMSIX_VECT166_MSG_DATA 0x1c29a 12380 #define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 5 12381 #define regPCIEMSIX_VECT166_CONTROL 0x1c29b 12382 #define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 5 12383 #define regPCIEMSIX_VECT167_ADDR_LO 0x1c29c 12384 #define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 5 12385 #define regPCIEMSIX_VECT167_ADDR_HI 0x1c29d 12386 #define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 5 12387 #define regPCIEMSIX_VECT167_MSG_DATA 0x1c29e 12388 #define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 5 12389 #define regPCIEMSIX_VECT167_CONTROL 0x1c29f 12390 #define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 5 12391 #define regPCIEMSIX_VECT168_ADDR_LO 0x1c2a0 12392 #define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 5 12393 #define regPCIEMSIX_VECT168_ADDR_HI 0x1c2a1 12394 #define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 5 12395 #define regPCIEMSIX_VECT168_MSG_DATA 0x1c2a2 12396 #define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 5 12397 #define regPCIEMSIX_VECT168_CONTROL 0x1c2a3 12398 #define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 5 12399 #define regPCIEMSIX_VECT169_ADDR_LO 0x1c2a4 12400 #define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 5 12401 #define regPCIEMSIX_VECT169_ADDR_HI 0x1c2a5 12402 #define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 5 12403 #define regPCIEMSIX_VECT169_MSG_DATA 0x1c2a6 12404 #define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 5 12405 #define regPCIEMSIX_VECT169_CONTROL 0x1c2a7 12406 #define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 5 12407 #define regPCIEMSIX_VECT170_ADDR_LO 0x1c2a8 12408 #define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 5 12409 #define regPCIEMSIX_VECT170_ADDR_HI 0x1c2a9 12410 #define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 5 12411 #define regPCIEMSIX_VECT170_MSG_DATA 0x1c2aa 12412 #define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 5 12413 #define regPCIEMSIX_VECT170_CONTROL 0x1c2ab 12414 #define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 5 12415 #define regPCIEMSIX_VECT171_ADDR_LO 0x1c2ac 12416 #define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 5 12417 #define regPCIEMSIX_VECT171_ADDR_HI 0x1c2ad 12418 #define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 5 12419 #define regPCIEMSIX_VECT171_MSG_DATA 0x1c2ae 12420 #define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 5 12421 #define regPCIEMSIX_VECT171_CONTROL 0x1c2af 12422 #define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 5 12423 #define regPCIEMSIX_VECT172_ADDR_LO 0x1c2b0 12424 #define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 5 12425 #define regPCIEMSIX_VECT172_ADDR_HI 0x1c2b1 12426 #define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 5 12427 #define regPCIEMSIX_VECT172_MSG_DATA 0x1c2b2 12428 #define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 5 12429 #define regPCIEMSIX_VECT172_CONTROL 0x1c2b3 12430 #define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 5 12431 #define regPCIEMSIX_VECT173_ADDR_LO 0x1c2b4 12432 #define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 5 12433 #define regPCIEMSIX_VECT173_ADDR_HI 0x1c2b5 12434 #define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 5 12435 #define regPCIEMSIX_VECT173_MSG_DATA 0x1c2b6 12436 #define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 5 12437 #define regPCIEMSIX_VECT173_CONTROL 0x1c2b7 12438 #define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 5 12439 #define regPCIEMSIX_VECT174_ADDR_LO 0x1c2b8 12440 #define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 5 12441 #define regPCIEMSIX_VECT174_ADDR_HI 0x1c2b9 12442 #define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 5 12443 #define regPCIEMSIX_VECT174_MSG_DATA 0x1c2ba 12444 #define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 5 12445 #define regPCIEMSIX_VECT174_CONTROL 0x1c2bb 12446 #define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 5 12447 #define regPCIEMSIX_VECT175_ADDR_LO 0x1c2bc 12448 #define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 5 12449 #define regPCIEMSIX_VECT175_ADDR_HI 0x1c2bd 12450 #define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 5 12451 #define regPCIEMSIX_VECT175_MSG_DATA 0x1c2be 12452 #define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 5 12453 #define regPCIEMSIX_VECT175_CONTROL 0x1c2bf 12454 #define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 5 12455 #define regPCIEMSIX_VECT176_ADDR_LO 0x1c2c0 12456 #define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 5 12457 #define regPCIEMSIX_VECT176_ADDR_HI 0x1c2c1 12458 #define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 5 12459 #define regPCIEMSIX_VECT176_MSG_DATA 0x1c2c2 12460 #define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 5 12461 #define regPCIEMSIX_VECT176_CONTROL 0x1c2c3 12462 #define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 5 12463 #define regPCIEMSIX_VECT177_ADDR_LO 0x1c2c4 12464 #define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 5 12465 #define regPCIEMSIX_VECT177_ADDR_HI 0x1c2c5 12466 #define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 5 12467 #define regPCIEMSIX_VECT177_MSG_DATA 0x1c2c6 12468 #define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 5 12469 #define regPCIEMSIX_VECT177_CONTROL 0x1c2c7 12470 #define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 5 12471 #define regPCIEMSIX_VECT178_ADDR_LO 0x1c2c8 12472 #define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 5 12473 #define regPCIEMSIX_VECT178_ADDR_HI 0x1c2c9 12474 #define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 5 12475 #define regPCIEMSIX_VECT178_MSG_DATA 0x1c2ca 12476 #define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 5 12477 #define regPCIEMSIX_VECT178_CONTROL 0x1c2cb 12478 #define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 5 12479 #define regPCIEMSIX_VECT179_ADDR_LO 0x1c2cc 12480 #define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 5 12481 #define regPCIEMSIX_VECT179_ADDR_HI 0x1c2cd 12482 #define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 5 12483 #define regPCIEMSIX_VECT179_MSG_DATA 0x1c2ce 12484 #define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 5 12485 #define regPCIEMSIX_VECT179_CONTROL 0x1c2cf 12486 #define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 5 12487 #define regPCIEMSIX_VECT180_ADDR_LO 0x1c2d0 12488 #define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 5 12489 #define regPCIEMSIX_VECT180_ADDR_HI 0x1c2d1 12490 #define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 5 12491 #define regPCIEMSIX_VECT180_MSG_DATA 0x1c2d2 12492 #define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 5 12493 #define regPCIEMSIX_VECT180_CONTROL 0x1c2d3 12494 #define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 5 12495 #define regPCIEMSIX_VECT181_ADDR_LO 0x1c2d4 12496 #define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 5 12497 #define regPCIEMSIX_VECT181_ADDR_HI 0x1c2d5 12498 #define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 5 12499 #define regPCIEMSIX_VECT181_MSG_DATA 0x1c2d6 12500 #define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 5 12501 #define regPCIEMSIX_VECT181_CONTROL 0x1c2d7 12502 #define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 5 12503 #define regPCIEMSIX_VECT182_ADDR_LO 0x1c2d8 12504 #define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 5 12505 #define regPCIEMSIX_VECT182_ADDR_HI 0x1c2d9 12506 #define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 5 12507 #define regPCIEMSIX_VECT182_MSG_DATA 0x1c2da 12508 #define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 5 12509 #define regPCIEMSIX_VECT182_CONTROL 0x1c2db 12510 #define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 5 12511 #define regPCIEMSIX_VECT183_ADDR_LO 0x1c2dc 12512 #define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 5 12513 #define regPCIEMSIX_VECT183_ADDR_HI 0x1c2dd 12514 #define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 5 12515 #define regPCIEMSIX_VECT183_MSG_DATA 0x1c2de 12516 #define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 5 12517 #define regPCIEMSIX_VECT183_CONTROL 0x1c2df 12518 #define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 5 12519 #define regPCIEMSIX_VECT184_ADDR_LO 0x1c2e0 12520 #define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 5 12521 #define regPCIEMSIX_VECT184_ADDR_HI 0x1c2e1 12522 #define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 5 12523 #define regPCIEMSIX_VECT184_MSG_DATA 0x1c2e2 12524 #define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 5 12525 #define regPCIEMSIX_VECT184_CONTROL 0x1c2e3 12526 #define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 5 12527 #define regPCIEMSIX_VECT185_ADDR_LO 0x1c2e4 12528 #define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 5 12529 #define regPCIEMSIX_VECT185_ADDR_HI 0x1c2e5 12530 #define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 5 12531 #define regPCIEMSIX_VECT185_MSG_DATA 0x1c2e6 12532 #define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 5 12533 #define regPCIEMSIX_VECT185_CONTROL 0x1c2e7 12534 #define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 5 12535 #define regPCIEMSIX_VECT186_ADDR_LO 0x1c2e8 12536 #define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 5 12537 #define regPCIEMSIX_VECT186_ADDR_HI 0x1c2e9 12538 #define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 5 12539 #define regPCIEMSIX_VECT186_MSG_DATA 0x1c2ea 12540 #define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 5 12541 #define regPCIEMSIX_VECT186_CONTROL 0x1c2eb 12542 #define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 5 12543 #define regPCIEMSIX_VECT187_ADDR_LO 0x1c2ec 12544 #define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 5 12545 #define regPCIEMSIX_VECT187_ADDR_HI 0x1c2ed 12546 #define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 5 12547 #define regPCIEMSIX_VECT187_MSG_DATA 0x1c2ee 12548 #define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 5 12549 #define regPCIEMSIX_VECT187_CONTROL 0x1c2ef 12550 #define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 5 12551 #define regPCIEMSIX_VECT188_ADDR_LO 0x1c2f0 12552 #define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 5 12553 #define regPCIEMSIX_VECT188_ADDR_HI 0x1c2f1 12554 #define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 5 12555 #define regPCIEMSIX_VECT188_MSG_DATA 0x1c2f2 12556 #define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 5 12557 #define regPCIEMSIX_VECT188_CONTROL 0x1c2f3 12558 #define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 5 12559 #define regPCIEMSIX_VECT189_ADDR_LO 0x1c2f4 12560 #define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 5 12561 #define regPCIEMSIX_VECT189_ADDR_HI 0x1c2f5 12562 #define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 5 12563 #define regPCIEMSIX_VECT189_MSG_DATA 0x1c2f6 12564 #define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 5 12565 #define regPCIEMSIX_VECT189_CONTROL 0x1c2f7 12566 #define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 5 12567 #define regPCIEMSIX_VECT190_ADDR_LO 0x1c2f8 12568 #define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 5 12569 #define regPCIEMSIX_VECT190_ADDR_HI 0x1c2f9 12570 #define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 5 12571 #define regPCIEMSIX_VECT190_MSG_DATA 0x1c2fa 12572 #define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 5 12573 #define regPCIEMSIX_VECT190_CONTROL 0x1c2fb 12574 #define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 5 12575 #define regPCIEMSIX_VECT191_ADDR_LO 0x1c2fc 12576 #define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 5 12577 #define regPCIEMSIX_VECT191_ADDR_HI 0x1c2fd 12578 #define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 5 12579 #define regPCIEMSIX_VECT191_MSG_DATA 0x1c2fe 12580 #define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 5 12581 #define regPCIEMSIX_VECT191_CONTROL 0x1c2ff 12582 #define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 5 12583 #define regPCIEMSIX_VECT192_ADDR_LO 0x1c300 12584 #define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 5 12585 #define regPCIEMSIX_VECT192_ADDR_HI 0x1c301 12586 #define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 5 12587 #define regPCIEMSIX_VECT192_MSG_DATA 0x1c302 12588 #define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 5 12589 #define regPCIEMSIX_VECT192_CONTROL 0x1c303 12590 #define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 5 12591 #define regPCIEMSIX_VECT193_ADDR_LO 0x1c304 12592 #define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 5 12593 #define regPCIEMSIX_VECT193_ADDR_HI 0x1c305 12594 #define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 5 12595 #define regPCIEMSIX_VECT193_MSG_DATA 0x1c306 12596 #define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 5 12597 #define regPCIEMSIX_VECT193_CONTROL 0x1c307 12598 #define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 5 12599 #define regPCIEMSIX_VECT194_ADDR_LO 0x1c308 12600 #define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 5 12601 #define regPCIEMSIX_VECT194_ADDR_HI 0x1c309 12602 #define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 5 12603 #define regPCIEMSIX_VECT194_MSG_DATA 0x1c30a 12604 #define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 5 12605 #define regPCIEMSIX_VECT194_CONTROL 0x1c30b 12606 #define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 5 12607 #define regPCIEMSIX_VECT195_ADDR_LO 0x1c30c 12608 #define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 5 12609 #define regPCIEMSIX_VECT195_ADDR_HI 0x1c30d 12610 #define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 5 12611 #define regPCIEMSIX_VECT195_MSG_DATA 0x1c30e 12612 #define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 5 12613 #define regPCIEMSIX_VECT195_CONTROL 0x1c30f 12614 #define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 5 12615 #define regPCIEMSIX_VECT196_ADDR_LO 0x1c310 12616 #define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 5 12617 #define regPCIEMSIX_VECT196_ADDR_HI 0x1c311 12618 #define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 5 12619 #define regPCIEMSIX_VECT196_MSG_DATA 0x1c312 12620 #define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 5 12621 #define regPCIEMSIX_VECT196_CONTROL 0x1c313 12622 #define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 5 12623 #define regPCIEMSIX_VECT197_ADDR_LO 0x1c314 12624 #define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 5 12625 #define regPCIEMSIX_VECT197_ADDR_HI 0x1c315 12626 #define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 5 12627 #define regPCIEMSIX_VECT197_MSG_DATA 0x1c316 12628 #define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 5 12629 #define regPCIEMSIX_VECT197_CONTROL 0x1c317 12630 #define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 5 12631 #define regPCIEMSIX_VECT198_ADDR_LO 0x1c318 12632 #define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 5 12633 #define regPCIEMSIX_VECT198_ADDR_HI 0x1c319 12634 #define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 5 12635 #define regPCIEMSIX_VECT198_MSG_DATA 0x1c31a 12636 #define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 5 12637 #define regPCIEMSIX_VECT198_CONTROL 0x1c31b 12638 #define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 5 12639 #define regPCIEMSIX_VECT199_ADDR_LO 0x1c31c 12640 #define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 5 12641 #define regPCIEMSIX_VECT199_ADDR_HI 0x1c31d 12642 #define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 5 12643 #define regPCIEMSIX_VECT199_MSG_DATA 0x1c31e 12644 #define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 5 12645 #define regPCIEMSIX_VECT199_CONTROL 0x1c31f 12646 #define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 5 12647 #define regPCIEMSIX_VECT200_ADDR_LO 0x1c320 12648 #define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 5 12649 #define regPCIEMSIX_VECT200_ADDR_HI 0x1c321 12650 #define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 5 12651 #define regPCIEMSIX_VECT200_MSG_DATA 0x1c322 12652 #define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 5 12653 #define regPCIEMSIX_VECT200_CONTROL 0x1c323 12654 #define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 5 12655 #define regPCIEMSIX_VECT201_ADDR_LO 0x1c324 12656 #define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 5 12657 #define regPCIEMSIX_VECT201_ADDR_HI 0x1c325 12658 #define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 5 12659 #define regPCIEMSIX_VECT201_MSG_DATA 0x1c326 12660 #define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 5 12661 #define regPCIEMSIX_VECT201_CONTROL 0x1c327 12662 #define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 5 12663 #define regPCIEMSIX_VECT202_ADDR_LO 0x1c328 12664 #define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 5 12665 #define regPCIEMSIX_VECT202_ADDR_HI 0x1c329 12666 #define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 5 12667 #define regPCIEMSIX_VECT202_MSG_DATA 0x1c32a 12668 #define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 5 12669 #define regPCIEMSIX_VECT202_CONTROL 0x1c32b 12670 #define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 5 12671 #define regPCIEMSIX_VECT203_ADDR_LO 0x1c32c 12672 #define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 5 12673 #define regPCIEMSIX_VECT203_ADDR_HI 0x1c32d 12674 #define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 5 12675 #define regPCIEMSIX_VECT203_MSG_DATA 0x1c32e 12676 #define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 5 12677 #define regPCIEMSIX_VECT203_CONTROL 0x1c32f 12678 #define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 5 12679 #define regPCIEMSIX_VECT204_ADDR_LO 0x1c330 12680 #define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 5 12681 #define regPCIEMSIX_VECT204_ADDR_HI 0x1c331 12682 #define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 5 12683 #define regPCIEMSIX_VECT204_MSG_DATA 0x1c332 12684 #define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 5 12685 #define regPCIEMSIX_VECT204_CONTROL 0x1c333 12686 #define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 5 12687 #define regPCIEMSIX_VECT205_ADDR_LO 0x1c334 12688 #define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 5 12689 #define regPCIEMSIX_VECT205_ADDR_HI 0x1c335 12690 #define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 5 12691 #define regPCIEMSIX_VECT205_MSG_DATA 0x1c336 12692 #define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 5 12693 #define regPCIEMSIX_VECT205_CONTROL 0x1c337 12694 #define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 5 12695 #define regPCIEMSIX_VECT206_ADDR_LO 0x1c338 12696 #define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 5 12697 #define regPCIEMSIX_VECT206_ADDR_HI 0x1c339 12698 #define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 5 12699 #define regPCIEMSIX_VECT206_MSG_DATA 0x1c33a 12700 #define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 5 12701 #define regPCIEMSIX_VECT206_CONTROL 0x1c33b 12702 #define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 5 12703 #define regPCIEMSIX_VECT207_ADDR_LO 0x1c33c 12704 #define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 5 12705 #define regPCIEMSIX_VECT207_ADDR_HI 0x1c33d 12706 #define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 5 12707 #define regPCIEMSIX_VECT207_MSG_DATA 0x1c33e 12708 #define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 5 12709 #define regPCIEMSIX_VECT207_CONTROL 0x1c33f 12710 #define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 5 12711 #define regPCIEMSIX_VECT208_ADDR_LO 0x1c340 12712 #define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 5 12713 #define regPCIEMSIX_VECT208_ADDR_HI 0x1c341 12714 #define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 5 12715 #define regPCIEMSIX_VECT208_MSG_DATA 0x1c342 12716 #define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 5 12717 #define regPCIEMSIX_VECT208_CONTROL 0x1c343 12718 #define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 5 12719 #define regPCIEMSIX_VECT209_ADDR_LO 0x1c344 12720 #define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 5 12721 #define regPCIEMSIX_VECT209_ADDR_HI 0x1c345 12722 #define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 5 12723 #define regPCIEMSIX_VECT209_MSG_DATA 0x1c346 12724 #define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 5 12725 #define regPCIEMSIX_VECT209_CONTROL 0x1c347 12726 #define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 5 12727 #define regPCIEMSIX_VECT210_ADDR_LO 0x1c348 12728 #define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 5 12729 #define regPCIEMSIX_VECT210_ADDR_HI 0x1c349 12730 #define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 5 12731 #define regPCIEMSIX_VECT210_MSG_DATA 0x1c34a 12732 #define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 5 12733 #define regPCIEMSIX_VECT210_CONTROL 0x1c34b 12734 #define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 5 12735 #define regPCIEMSIX_VECT211_ADDR_LO 0x1c34c 12736 #define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 5 12737 #define regPCIEMSIX_VECT211_ADDR_HI 0x1c34d 12738 #define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 5 12739 #define regPCIEMSIX_VECT211_MSG_DATA 0x1c34e 12740 #define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 5 12741 #define regPCIEMSIX_VECT211_CONTROL 0x1c34f 12742 #define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 5 12743 #define regPCIEMSIX_VECT212_ADDR_LO 0x1c350 12744 #define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 5 12745 #define regPCIEMSIX_VECT212_ADDR_HI 0x1c351 12746 #define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 5 12747 #define regPCIEMSIX_VECT212_MSG_DATA 0x1c352 12748 #define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 5 12749 #define regPCIEMSIX_VECT212_CONTROL 0x1c353 12750 #define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 5 12751 #define regPCIEMSIX_VECT213_ADDR_LO 0x1c354 12752 #define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 5 12753 #define regPCIEMSIX_VECT213_ADDR_HI 0x1c355 12754 #define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 5 12755 #define regPCIEMSIX_VECT213_MSG_DATA 0x1c356 12756 #define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 5 12757 #define regPCIEMSIX_VECT213_CONTROL 0x1c357 12758 #define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 5 12759 #define regPCIEMSIX_VECT214_ADDR_LO 0x1c358 12760 #define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 5 12761 #define regPCIEMSIX_VECT214_ADDR_HI 0x1c359 12762 #define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 5 12763 #define regPCIEMSIX_VECT214_MSG_DATA 0x1c35a 12764 #define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 5 12765 #define regPCIEMSIX_VECT214_CONTROL 0x1c35b 12766 #define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 5 12767 #define regPCIEMSIX_VECT215_ADDR_LO 0x1c35c 12768 #define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 5 12769 #define regPCIEMSIX_VECT215_ADDR_HI 0x1c35d 12770 #define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 5 12771 #define regPCIEMSIX_VECT215_MSG_DATA 0x1c35e 12772 #define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 5 12773 #define regPCIEMSIX_VECT215_CONTROL 0x1c35f 12774 #define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 5 12775 #define regPCIEMSIX_VECT216_ADDR_LO 0x1c360 12776 #define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 5 12777 #define regPCIEMSIX_VECT216_ADDR_HI 0x1c361 12778 #define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 5 12779 #define regPCIEMSIX_VECT216_MSG_DATA 0x1c362 12780 #define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 5 12781 #define regPCIEMSIX_VECT216_CONTROL 0x1c363 12782 #define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 5 12783 #define regPCIEMSIX_VECT217_ADDR_LO 0x1c364 12784 #define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 5 12785 #define regPCIEMSIX_VECT217_ADDR_HI 0x1c365 12786 #define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 5 12787 #define regPCIEMSIX_VECT217_MSG_DATA 0x1c366 12788 #define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 5 12789 #define regPCIEMSIX_VECT217_CONTROL 0x1c367 12790 #define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 5 12791 #define regPCIEMSIX_VECT218_ADDR_LO 0x1c368 12792 #define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 5 12793 #define regPCIEMSIX_VECT218_ADDR_HI 0x1c369 12794 #define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 5 12795 #define regPCIEMSIX_VECT218_MSG_DATA 0x1c36a 12796 #define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 5 12797 #define regPCIEMSIX_VECT218_CONTROL 0x1c36b 12798 #define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 5 12799 #define regPCIEMSIX_VECT219_ADDR_LO 0x1c36c 12800 #define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 5 12801 #define regPCIEMSIX_VECT219_ADDR_HI 0x1c36d 12802 #define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 5 12803 #define regPCIEMSIX_VECT219_MSG_DATA 0x1c36e 12804 #define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 5 12805 #define regPCIEMSIX_VECT219_CONTROL 0x1c36f 12806 #define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 5 12807 #define regPCIEMSIX_VECT220_ADDR_LO 0x1c370 12808 #define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 5 12809 #define regPCIEMSIX_VECT220_ADDR_HI 0x1c371 12810 #define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 5 12811 #define regPCIEMSIX_VECT220_MSG_DATA 0x1c372 12812 #define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 5 12813 #define regPCIEMSIX_VECT220_CONTROL 0x1c373 12814 #define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 5 12815 #define regPCIEMSIX_VECT221_ADDR_LO 0x1c374 12816 #define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 5 12817 #define regPCIEMSIX_VECT221_ADDR_HI 0x1c375 12818 #define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 5 12819 #define regPCIEMSIX_VECT221_MSG_DATA 0x1c376 12820 #define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 5 12821 #define regPCIEMSIX_VECT221_CONTROL 0x1c377 12822 #define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 5 12823 #define regPCIEMSIX_VECT222_ADDR_LO 0x1c378 12824 #define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 5 12825 #define regPCIEMSIX_VECT222_ADDR_HI 0x1c379 12826 #define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 5 12827 #define regPCIEMSIX_VECT222_MSG_DATA 0x1c37a 12828 #define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 5 12829 #define regPCIEMSIX_VECT222_CONTROL 0x1c37b 12830 #define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 5 12831 #define regPCIEMSIX_VECT223_ADDR_LO 0x1c37c 12832 #define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 5 12833 #define regPCIEMSIX_VECT223_ADDR_HI 0x1c37d 12834 #define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 5 12835 #define regPCIEMSIX_VECT223_MSG_DATA 0x1c37e 12836 #define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 5 12837 #define regPCIEMSIX_VECT223_CONTROL 0x1c37f 12838 #define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 5 12839 #define regPCIEMSIX_VECT224_ADDR_LO 0x1c380 12840 #define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 5 12841 #define regPCIEMSIX_VECT224_ADDR_HI 0x1c381 12842 #define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 5 12843 #define regPCIEMSIX_VECT224_MSG_DATA 0x1c382 12844 #define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 5 12845 #define regPCIEMSIX_VECT224_CONTROL 0x1c383 12846 #define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 5 12847 #define regPCIEMSIX_VECT225_ADDR_LO 0x1c384 12848 #define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 5 12849 #define regPCIEMSIX_VECT225_ADDR_HI 0x1c385 12850 #define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 5 12851 #define regPCIEMSIX_VECT225_MSG_DATA 0x1c386 12852 #define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 5 12853 #define regPCIEMSIX_VECT225_CONTROL 0x1c387 12854 #define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 5 12855 #define regPCIEMSIX_VECT226_ADDR_LO 0x1c388 12856 #define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 5 12857 #define regPCIEMSIX_VECT226_ADDR_HI 0x1c389 12858 #define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 5 12859 #define regPCIEMSIX_VECT226_MSG_DATA 0x1c38a 12860 #define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 5 12861 #define regPCIEMSIX_VECT226_CONTROL 0x1c38b 12862 #define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 5 12863 #define regPCIEMSIX_VECT227_ADDR_LO 0x1c38c 12864 #define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 5 12865 #define regPCIEMSIX_VECT227_ADDR_HI 0x1c38d 12866 #define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 5 12867 #define regPCIEMSIX_VECT227_MSG_DATA 0x1c38e 12868 #define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 5 12869 #define regPCIEMSIX_VECT227_CONTROL 0x1c38f 12870 #define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 5 12871 #define regPCIEMSIX_VECT228_ADDR_LO 0x1c390 12872 #define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 5 12873 #define regPCIEMSIX_VECT228_ADDR_HI 0x1c391 12874 #define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 5 12875 #define regPCIEMSIX_VECT228_MSG_DATA 0x1c392 12876 #define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 5 12877 #define regPCIEMSIX_VECT228_CONTROL 0x1c393 12878 #define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 5 12879 #define regPCIEMSIX_VECT229_ADDR_LO 0x1c394 12880 #define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 5 12881 #define regPCIEMSIX_VECT229_ADDR_HI 0x1c395 12882 #define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 5 12883 #define regPCIEMSIX_VECT229_MSG_DATA 0x1c396 12884 #define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 5 12885 #define regPCIEMSIX_VECT229_CONTROL 0x1c397 12886 #define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 5 12887 #define regPCIEMSIX_VECT230_ADDR_LO 0x1c398 12888 #define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 5 12889 #define regPCIEMSIX_VECT230_ADDR_HI 0x1c399 12890 #define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 5 12891 #define regPCIEMSIX_VECT230_MSG_DATA 0x1c39a 12892 #define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 5 12893 #define regPCIEMSIX_VECT230_CONTROL 0x1c39b 12894 #define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 5 12895 #define regPCIEMSIX_VECT231_ADDR_LO 0x1c39c 12896 #define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 5 12897 #define regPCIEMSIX_VECT231_ADDR_HI 0x1c39d 12898 #define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 5 12899 #define regPCIEMSIX_VECT231_MSG_DATA 0x1c39e 12900 #define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 5 12901 #define regPCIEMSIX_VECT231_CONTROL 0x1c39f 12902 #define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 5 12903 #define regPCIEMSIX_VECT232_ADDR_LO 0x1c3a0 12904 #define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 5 12905 #define regPCIEMSIX_VECT232_ADDR_HI 0x1c3a1 12906 #define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 5 12907 #define regPCIEMSIX_VECT232_MSG_DATA 0x1c3a2 12908 #define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 5 12909 #define regPCIEMSIX_VECT232_CONTROL 0x1c3a3 12910 #define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 5 12911 #define regPCIEMSIX_VECT233_ADDR_LO 0x1c3a4 12912 #define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 5 12913 #define regPCIEMSIX_VECT233_ADDR_HI 0x1c3a5 12914 #define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 5 12915 #define regPCIEMSIX_VECT233_MSG_DATA 0x1c3a6 12916 #define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 5 12917 #define regPCIEMSIX_VECT233_CONTROL 0x1c3a7 12918 #define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 5 12919 #define regPCIEMSIX_VECT234_ADDR_LO 0x1c3a8 12920 #define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 5 12921 #define regPCIEMSIX_VECT234_ADDR_HI 0x1c3a9 12922 #define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 5 12923 #define regPCIEMSIX_VECT234_MSG_DATA 0x1c3aa 12924 #define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 5 12925 #define regPCIEMSIX_VECT234_CONTROL 0x1c3ab 12926 #define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 5 12927 #define regPCIEMSIX_VECT235_ADDR_LO 0x1c3ac 12928 #define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 5 12929 #define regPCIEMSIX_VECT235_ADDR_HI 0x1c3ad 12930 #define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 5 12931 #define regPCIEMSIX_VECT235_MSG_DATA 0x1c3ae 12932 #define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 5 12933 #define regPCIEMSIX_VECT235_CONTROL 0x1c3af 12934 #define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 5 12935 #define regPCIEMSIX_VECT236_ADDR_LO 0x1c3b0 12936 #define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 5 12937 #define regPCIEMSIX_VECT236_ADDR_HI 0x1c3b1 12938 #define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 5 12939 #define regPCIEMSIX_VECT236_MSG_DATA 0x1c3b2 12940 #define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 5 12941 #define regPCIEMSIX_VECT236_CONTROL 0x1c3b3 12942 #define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 5 12943 #define regPCIEMSIX_VECT237_ADDR_LO 0x1c3b4 12944 #define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 5 12945 #define regPCIEMSIX_VECT237_ADDR_HI 0x1c3b5 12946 #define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 5 12947 #define regPCIEMSIX_VECT237_MSG_DATA 0x1c3b6 12948 #define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 5 12949 #define regPCIEMSIX_VECT237_CONTROL 0x1c3b7 12950 #define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 5 12951 #define regPCIEMSIX_VECT238_ADDR_LO 0x1c3b8 12952 #define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 5 12953 #define regPCIEMSIX_VECT238_ADDR_HI 0x1c3b9 12954 #define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 5 12955 #define regPCIEMSIX_VECT238_MSG_DATA 0x1c3ba 12956 #define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 5 12957 #define regPCIEMSIX_VECT238_CONTROL 0x1c3bb 12958 #define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 5 12959 #define regPCIEMSIX_VECT239_ADDR_LO 0x1c3bc 12960 #define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 5 12961 #define regPCIEMSIX_VECT239_ADDR_HI 0x1c3bd 12962 #define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 5 12963 #define regPCIEMSIX_VECT239_MSG_DATA 0x1c3be 12964 #define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 5 12965 #define regPCIEMSIX_VECT239_CONTROL 0x1c3bf 12966 #define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 5 12967 #define regPCIEMSIX_VECT240_ADDR_LO 0x1c3c0 12968 #define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 5 12969 #define regPCIEMSIX_VECT240_ADDR_HI 0x1c3c1 12970 #define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 5 12971 #define regPCIEMSIX_VECT240_MSG_DATA 0x1c3c2 12972 #define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 5 12973 #define regPCIEMSIX_VECT240_CONTROL 0x1c3c3 12974 #define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 5 12975 #define regPCIEMSIX_VECT241_ADDR_LO 0x1c3c4 12976 #define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 5 12977 #define regPCIEMSIX_VECT241_ADDR_HI 0x1c3c5 12978 #define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 5 12979 #define regPCIEMSIX_VECT241_MSG_DATA 0x1c3c6 12980 #define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 5 12981 #define regPCIEMSIX_VECT241_CONTROL 0x1c3c7 12982 #define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 5 12983 #define regPCIEMSIX_VECT242_ADDR_LO 0x1c3c8 12984 #define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 5 12985 #define regPCIEMSIX_VECT242_ADDR_HI 0x1c3c9 12986 #define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 5 12987 #define regPCIEMSIX_VECT242_MSG_DATA 0x1c3ca 12988 #define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 5 12989 #define regPCIEMSIX_VECT242_CONTROL 0x1c3cb 12990 #define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 5 12991 #define regPCIEMSIX_VECT243_ADDR_LO 0x1c3cc 12992 #define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 5 12993 #define regPCIEMSIX_VECT243_ADDR_HI 0x1c3cd 12994 #define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 5 12995 #define regPCIEMSIX_VECT243_MSG_DATA 0x1c3ce 12996 #define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 5 12997 #define regPCIEMSIX_VECT243_CONTROL 0x1c3cf 12998 #define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 5 12999 #define regPCIEMSIX_VECT244_ADDR_LO 0x1c3d0 13000 #define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 5 13001 #define regPCIEMSIX_VECT244_ADDR_HI 0x1c3d1 13002 #define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 5 13003 #define regPCIEMSIX_VECT244_MSG_DATA 0x1c3d2 13004 #define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 5 13005 #define regPCIEMSIX_VECT244_CONTROL 0x1c3d3 13006 #define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 5 13007 #define regPCIEMSIX_VECT245_ADDR_LO 0x1c3d4 13008 #define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 5 13009 #define regPCIEMSIX_VECT245_ADDR_HI 0x1c3d5 13010 #define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 5 13011 #define regPCIEMSIX_VECT245_MSG_DATA 0x1c3d6 13012 #define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 5 13013 #define regPCIEMSIX_VECT245_CONTROL 0x1c3d7 13014 #define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 5 13015 #define regPCIEMSIX_VECT246_ADDR_LO 0x1c3d8 13016 #define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 5 13017 #define regPCIEMSIX_VECT246_ADDR_HI 0x1c3d9 13018 #define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 5 13019 #define regPCIEMSIX_VECT246_MSG_DATA 0x1c3da 13020 #define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 5 13021 #define regPCIEMSIX_VECT246_CONTROL 0x1c3db 13022 #define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 5 13023 #define regPCIEMSIX_VECT247_ADDR_LO 0x1c3dc 13024 #define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 5 13025 #define regPCIEMSIX_VECT247_ADDR_HI 0x1c3dd 13026 #define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 5 13027 #define regPCIEMSIX_VECT247_MSG_DATA 0x1c3de 13028 #define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 5 13029 #define regPCIEMSIX_VECT247_CONTROL 0x1c3df 13030 #define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 5 13031 #define regPCIEMSIX_VECT248_ADDR_LO 0x1c3e0 13032 #define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 5 13033 #define regPCIEMSIX_VECT248_ADDR_HI 0x1c3e1 13034 #define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 5 13035 #define regPCIEMSIX_VECT248_MSG_DATA 0x1c3e2 13036 #define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 5 13037 #define regPCIEMSIX_VECT248_CONTROL 0x1c3e3 13038 #define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 5 13039 #define regPCIEMSIX_VECT249_ADDR_LO 0x1c3e4 13040 #define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 5 13041 #define regPCIEMSIX_VECT249_ADDR_HI 0x1c3e5 13042 #define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 5 13043 #define regPCIEMSIX_VECT249_MSG_DATA 0x1c3e6 13044 #define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 5 13045 #define regPCIEMSIX_VECT249_CONTROL 0x1c3e7 13046 #define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 5 13047 #define regPCIEMSIX_VECT250_ADDR_LO 0x1c3e8 13048 #define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 5 13049 #define regPCIEMSIX_VECT250_ADDR_HI 0x1c3e9 13050 #define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 5 13051 #define regPCIEMSIX_VECT250_MSG_DATA 0x1c3ea 13052 #define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 5 13053 #define regPCIEMSIX_VECT250_CONTROL 0x1c3eb 13054 #define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 5 13055 #define regPCIEMSIX_VECT251_ADDR_LO 0x1c3ec 13056 #define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 5 13057 #define regPCIEMSIX_VECT251_ADDR_HI 0x1c3ed 13058 #define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 5 13059 #define regPCIEMSIX_VECT251_MSG_DATA 0x1c3ee 13060 #define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 5 13061 #define regPCIEMSIX_VECT251_CONTROL 0x1c3ef 13062 #define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 5 13063 #define regPCIEMSIX_VECT252_ADDR_LO 0x1c3f0 13064 #define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 5 13065 #define regPCIEMSIX_VECT252_ADDR_HI 0x1c3f1 13066 #define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 5 13067 #define regPCIEMSIX_VECT252_MSG_DATA 0x1c3f2 13068 #define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 5 13069 #define regPCIEMSIX_VECT252_CONTROL 0x1c3f3 13070 #define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 5 13071 #define regPCIEMSIX_VECT253_ADDR_LO 0x1c3f4 13072 #define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 5 13073 #define regPCIEMSIX_VECT253_ADDR_HI 0x1c3f5 13074 #define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 5 13075 #define regPCIEMSIX_VECT253_MSG_DATA 0x1c3f6 13076 #define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 5 13077 #define regPCIEMSIX_VECT253_CONTROL 0x1c3f7 13078 #define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 5 13079 #define regPCIEMSIX_VECT254_ADDR_LO 0x1c3f8 13080 #define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 5 13081 #define regPCIEMSIX_VECT254_ADDR_HI 0x1c3f9 13082 #define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 5 13083 #define regPCIEMSIX_VECT254_MSG_DATA 0x1c3fa 13084 #define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 5 13085 #define regPCIEMSIX_VECT254_CONTROL 0x1c3fb 13086 #define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 5 13087 #define regPCIEMSIX_VECT255_ADDR_LO 0x1c3fc 13088 #define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 5 13089 #define regPCIEMSIX_VECT255_ADDR_HI 0x1c3fd 13090 #define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 5 13091 #define regPCIEMSIX_VECT255_MSG_DATA 0x1c3fe 13092 #define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 5 13093 #define regPCIEMSIX_VECT255_CONTROL 0x1c3ff 13094 #define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 5 13095 13096 13097 // base address: 0x10171000 13098 #define regPCIEMSIX_PBA_0 0x1c400 13099 #define regPCIEMSIX_PBA_0_BASE_IDX 5 13100 #define regPCIEMSIX_PBA_1 0x1c401 13101 #define regPCIEMSIX_PBA_1_BASE_IDX 5 13102 #define regPCIEMSIX_PBA_2 0x1c402 13103 #define regPCIEMSIX_PBA_2_BASE_IDX 5 13104 #define regPCIEMSIX_PBA_3 0x1c403 13105 #define regPCIEMSIX_PBA_3_BASE_IDX 5 13106 #define regPCIEMSIX_PBA_4 0x1c404 13107 #define regPCIEMSIX_PBA_4_BASE_IDX 5 13108 #define regPCIEMSIX_PBA_5 0x1c405 13109 #define regPCIEMSIX_PBA_5_BASE_IDX 5 13110 #define regPCIEMSIX_PBA_6 0x1c406 13111 #define regPCIEMSIX_PBA_6_BASE_IDX 5 13112 #define regPCIEMSIX_PBA_7 0x1c407 13113 #define regPCIEMSIX_PBA_7_BASE_IDX 5 13114 13115 13116 // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec 13117 // base address: 0x10130000 13118 #define regSHADOW_COMMAND 0xc001 13119 #define regSHADOW_COMMAND_BASE_IDX 5 13120 #define regSHADOW_BASE_ADDR_1 0xc004 13121 #define regSHADOW_BASE_ADDR_1_BASE_IDX 5 13122 #define regSHADOW_BASE_ADDR_2 0xc005 13123 #define regSHADOW_BASE_ADDR_2_BASE_IDX 5 13124 #define regSHADOW_SUB_BUS_NUMBER_LATENCY 0xc006 13125 #define regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 13126 #define regSHADOW_IO_BASE_LIMIT 0xc007 13127 #define regSHADOW_IO_BASE_LIMIT_BASE_IDX 5 13128 #define regSHADOW_MEM_BASE_LIMIT 0xc008 13129 #define regSHADOW_MEM_BASE_LIMIT_BASE_IDX 5 13130 #define regSHADOW_PREF_BASE_LIMIT 0xc009 13131 #define regSHADOW_PREF_BASE_LIMIT_BASE_IDX 5 13132 #define regSHADOW_PREF_BASE_UPPER 0xc00a 13133 #define regSHADOW_PREF_BASE_UPPER_BASE_IDX 5 13134 #define regSHADOW_PREF_LIMIT_UPPER 0xc00b 13135 #define regSHADOW_PREF_LIMIT_UPPER_BASE_IDX 5 13136 #define regSHADOW_IO_BASE_LIMIT_HI 0xc00c 13137 #define regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX 5 13138 #define regSUC_INDEX 0xc038 13139 #define regSUC_INDEX_BASE_IDX 5 13140 #define regSUC_DATA 0xc039 13141 #define regSUC_DATA_BASE_IDX 5 13142 13143 13144 // addressBlock: nbio_nbif0_bif_swus_SUMDEC 13145 // base address: 0x1013b000 13146 #define regSUM_INDEX 0xec38 13147 #define regSUM_INDEX_BASE_IDX 5 13148 #define regSUM_DATA 0xec39 13149 #define regSUM_DATA_BASE_IDX 5 13150 #define regSUM_INDEX_HI 0xec3b 13151 #define regSUM_INDEX_HI_BASE_IDX 5 13152 13153 13154 // addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal 13155 // base address: 0x10100000 13156 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 13157 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 13158 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 13159 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 13160 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 13161 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 13162 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 13163 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 13164 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 13165 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 13166 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 13167 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 13168 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 13169 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 13170 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 13171 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 13172 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 13173 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 13174 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 13175 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 13176 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a 13177 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 13178 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b 13179 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 13180 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c 13181 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 13182 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d 13183 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 13184 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e 13185 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 13186 #define regRCC_DEV1_PORT_STRAP0 0xc480 13187 #define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5 13188 #define regRCC_DEV1_PORT_STRAP1 0xc481 13189 #define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5 13190 #define regRCC_DEV1_PORT_STRAP2 0xc482 13191 #define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5 13192 #define regRCC_DEV1_PORT_STRAP3 0xc483 13193 #define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5 13194 #define regRCC_DEV1_PORT_STRAP4 0xc484 13195 #define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5 13196 #define regRCC_DEV1_PORT_STRAP5 0xc485 13197 #define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5 13198 #define regRCC_DEV1_PORT_STRAP6 0xc486 13199 #define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5 13200 #define regRCC_DEV1_PORT_STRAP7 0xc487 13201 #define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5 13202 #define regRCC_DEV1_PORT_STRAP8 0xc488 13203 #define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5 13204 #define regRCC_DEV1_PORT_STRAP9 0xc489 13205 #define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5 13206 #define regRCC_DEV1_PORT_STRAP10 0xc48a 13207 #define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5 13208 #define regRCC_DEV1_PORT_STRAP11 0xc48b 13209 #define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5 13210 #define regRCC_DEV1_PORT_STRAP12 0xc48c 13211 #define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5 13212 #define regRCC_DEV1_PORT_STRAP13 0xc48d 13213 #define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5 13214 #define regRCC_DEV1_PORT_STRAP14 0xc48e 13215 #define regRCC_DEV1_PORT_STRAP14_BASE_IDX 5 13216 #define regRCC_DEV2_PORT_STRAP0 0xc500 13217 #define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5 13218 #define regRCC_DEV2_PORT_STRAP1 0xc501 13219 #define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5 13220 #define regRCC_DEV2_PORT_STRAP2 0xc502 13221 #define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5 13222 #define regRCC_DEV2_PORT_STRAP3 0xc503 13223 #define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5 13224 #define regRCC_DEV2_PORT_STRAP4 0xc504 13225 #define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5 13226 #define regRCC_DEV2_PORT_STRAP5 0xc505 13227 #define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5 13228 #define regRCC_DEV2_PORT_STRAP6 0xc506 13229 #define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5 13230 #define regRCC_DEV2_PORT_STRAP7 0xc507 13231 #define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5 13232 #define regRCC_DEV2_PORT_STRAP8 0xc508 13233 #define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5 13234 #define regRCC_DEV2_PORT_STRAP9 0xc509 13235 #define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5 13236 #define regRCC_DEV2_PORT_STRAP10 0xc50a 13237 #define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5 13238 #define regRCC_DEV2_PORT_STRAP11 0xc50b 13239 #define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5 13240 #define regRCC_DEV2_PORT_STRAP12 0xc50c 13241 #define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5 13242 #define regRCC_DEV2_PORT_STRAP13 0xc50d 13243 #define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5 13244 #define regRCC_DEV2_PORT_STRAP14 0xc50e 13245 #define regRCC_DEV2_PORT_STRAP14_BASE_IDX 5 13246 #define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 13247 #define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5 13248 #define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 13249 #define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5 13250 #define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 13251 #define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5 13252 #define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 13253 #define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5 13254 #define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 13255 #define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5 13256 #define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 13257 #define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5 13258 #define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 13259 #define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5 13260 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 13261 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 13262 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 13263 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 13264 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 13265 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 13266 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 13267 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 13268 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 13269 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 13270 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 13271 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 13272 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 13273 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 13274 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 13275 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 13276 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d 13277 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 13278 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e 13279 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 13280 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f 13281 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 13282 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 13283 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 13284 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 13285 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 13286 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 13287 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 13288 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 0xd01a 13289 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX 5 13290 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 13291 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 13292 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 13293 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 13294 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 13295 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 13296 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 13297 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 13298 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 13299 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 13300 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 13301 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 13302 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 13303 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 13304 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 13305 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 13306 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 13307 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 13308 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 0xd096 13309 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX 5 13310 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 13311 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 13312 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 13313 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 13314 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 0xd099 13315 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX 5 13316 #define regRCC_DEV0_EPF2_STRAP0 0xd100 13317 #define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5 13318 #define regRCC_DEV0_EPF2_STRAP2 0xd102 13319 #define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5 13320 #define regRCC_DEV0_EPF2_STRAP3 0xd103 13321 #define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5 13322 #define regRCC_DEV0_EPF2_STRAP4 0xd104 13323 #define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5 13324 #define regRCC_DEV0_EPF2_STRAP5 0xd105 13325 #define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5 13326 #define regRCC_DEV0_EPF2_STRAP6 0xd106 13327 #define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5 13328 #define regRCC_DEV0_EPF2_STRAP7 0xd107 13329 #define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5 13330 #define regRCC_DEV0_EPF2_STRAP10 0xd10a 13331 #define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5 13332 #define regRCC_DEV0_EPF2_STRAP11 0xd10b 13333 #define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5 13334 #define regRCC_DEV0_EPF2_STRAP12 0xd10c 13335 #define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5 13336 #define regRCC_DEV0_EPF2_STRAP13 0xd10d 13337 #define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5 13338 #define regRCC_DEV0_EPF2_STRAP14 0xd10e 13339 #define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5 13340 #define regRCC_DEV0_EPF2_STRAP20 0xd114 13341 #define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 5 13342 #define regRCC_DEV0_EPF3_STRAP0 0xd180 13343 #define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5 13344 #define regRCC_DEV0_EPF3_STRAP2 0xd182 13345 #define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5 13346 #define regRCC_DEV0_EPF3_STRAP3 0xd183 13347 #define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5 13348 #define regRCC_DEV0_EPF3_STRAP4 0xd184 13349 #define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5 13350 #define regRCC_DEV0_EPF3_STRAP5 0xd185 13351 #define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5 13352 #define regRCC_DEV0_EPF3_STRAP6 0xd186 13353 #define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5 13354 #define regRCC_DEV0_EPF3_STRAP7 0xd187 13355 #define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5 13356 #define regRCC_DEV0_EPF3_STRAP10 0xd18a 13357 #define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5 13358 #define regRCC_DEV0_EPF3_STRAP11 0xd18b 13359 #define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5 13360 #define regRCC_DEV0_EPF3_STRAP12 0xd18c 13361 #define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5 13362 #define regRCC_DEV0_EPF3_STRAP13 0xd18d 13363 #define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5 13364 #define regRCC_DEV0_EPF3_STRAP14 0xd18e 13365 #define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5 13366 #define regRCC_DEV0_EPF3_STRAP20 0xd194 13367 #define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 5 13368 #define regRCC_DEV0_EPF4_STRAP0 0xd200 13369 #define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5 13370 #define regRCC_DEV0_EPF4_STRAP2 0xd202 13371 #define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5 13372 #define regRCC_DEV0_EPF4_STRAP3 0xd203 13373 #define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5 13374 #define regRCC_DEV0_EPF4_STRAP4 0xd204 13375 #define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5 13376 #define regRCC_DEV0_EPF4_STRAP5 0xd205 13377 #define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5 13378 #define regRCC_DEV0_EPF4_STRAP6 0xd206 13379 #define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5 13380 #define regRCC_DEV0_EPF4_STRAP7 0xd207 13381 #define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5 13382 #define regRCC_DEV0_EPF4_STRAP13 0xd20d 13383 #define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5 13384 #define regRCC_DEV0_EPF4_STRAP14 0xd20e 13385 #define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5 13386 #define regRCC_DEV0_EPF5_STRAP0 0xd280 13387 #define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5 13388 #define regRCC_DEV0_EPF5_STRAP2 0xd282 13389 #define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5 13390 #define regRCC_DEV0_EPF5_STRAP3 0xd283 13391 #define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5 13392 #define regRCC_DEV0_EPF5_STRAP4 0xd284 13393 #define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5 13394 #define regRCC_DEV0_EPF5_STRAP5 0xd285 13395 #define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5 13396 #define regRCC_DEV0_EPF5_STRAP6 0xd286 13397 #define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5 13398 #define regRCC_DEV0_EPF5_STRAP7 0xd287 13399 #define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5 13400 #define regRCC_DEV0_EPF5_STRAP13 0xd28d 13401 #define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5 13402 #define regRCC_DEV0_EPF5_STRAP14 0xd28e 13403 #define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5 13404 #define regRCC_DEV0_EPF6_STRAP0 0xd300 13405 #define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5 13406 #define regRCC_DEV0_EPF6_STRAP2 0xd302 13407 #define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5 13408 #define regRCC_DEV0_EPF6_STRAP3 0xd303 13409 #define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5 13410 #define regRCC_DEV0_EPF6_STRAP4 0xd304 13411 #define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5 13412 #define regRCC_DEV0_EPF6_STRAP5 0xd305 13413 #define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5 13414 #define regRCC_DEV0_EPF6_STRAP6 0xd306 13415 #define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5 13416 #define regRCC_DEV0_EPF6_STRAP13 0xd30d 13417 #define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5 13418 #define regRCC_DEV0_EPF6_STRAP14 0xd30e 13419 #define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5 13420 #define regRCC_DEV0_EPF7_STRAP0 0xd380 13421 #define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5 13422 #define regRCC_DEV0_EPF7_STRAP2 0xd382 13423 #define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5 13424 #define regRCC_DEV0_EPF7_STRAP3 0xd383 13425 #define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5 13426 #define regRCC_DEV0_EPF7_STRAP4 0xd384 13427 #define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5 13428 #define regRCC_DEV0_EPF7_STRAP5 0xd385 13429 #define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5 13430 #define regRCC_DEV0_EPF7_STRAP6 0xd386 13431 #define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5 13432 #define regRCC_DEV0_EPF7_STRAP7 0xd387 13433 #define regRCC_DEV0_EPF7_STRAP7_BASE_IDX 5 13434 #define regRCC_DEV0_EPF7_STRAP13 0xd38d 13435 #define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5 13436 #define regRCC_DEV0_EPF7_STRAP14 0xd38e 13437 #define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5 13438 #define regRCC_DEV1_EPF0_STRAP0 0xd400 13439 #define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5 13440 #define regRCC_DEV1_EPF0_STRAP2 0xd402 13441 #define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5 13442 #define regRCC_DEV1_EPF0_STRAP3 0xd403 13443 #define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5 13444 #define regRCC_DEV1_EPF0_STRAP4 0xd404 13445 #define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5 13446 #define regRCC_DEV1_EPF0_STRAP5 0xd405 13447 #define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5 13448 #define regRCC_DEV1_EPF0_STRAP6 0xd406 13449 #define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5 13450 #define regRCC_DEV1_EPF0_STRAP7 0xd407 13451 #define regRCC_DEV1_EPF0_STRAP7_BASE_IDX 5 13452 #define regRCC_DEV1_EPF0_STRAP13 0xd40d 13453 #define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5 13454 #define regRCC_DEV1_EPF0_STRAP14 0xd40e 13455 #define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5 13456 #define regRCC_DEV1_EPF1_STRAP0 0xd480 13457 #define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5 13458 #define regRCC_DEV1_EPF1_STRAP2 0xd482 13459 #define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5 13460 #define regRCC_DEV1_EPF1_STRAP3 0xd483 13461 #define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5 13462 #define regRCC_DEV1_EPF1_STRAP4 0xd484 13463 #define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5 13464 #define regRCC_DEV1_EPF1_STRAP5 0xd485 13465 #define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5 13466 #define regRCC_DEV1_EPF1_STRAP6 0xd486 13467 #define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5 13468 #define regRCC_DEV1_EPF1_STRAP7 0xd487 13469 #define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 5 13470 #define regRCC_DEV1_EPF1_STRAP13 0xd48d 13471 #define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 5 13472 #define regRCC_DEV1_EPF1_STRAP14 0xd48e 13473 #define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 5 13474 #define regRCC_DEV1_EPF2_STRAP0 0xd500 13475 #define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5 13476 #define regRCC_DEV1_EPF2_STRAP2 0xd502 13477 #define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5 13478 #define regRCC_DEV1_EPF2_STRAP3 0xd503 13479 #define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5 13480 #define regRCC_DEV1_EPF2_STRAP4 0xd504 13481 #define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5 13482 #define regRCC_DEV1_EPF2_STRAP5 0xd505 13483 #define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5 13484 #define regRCC_DEV1_EPF2_STRAP6 0xd506 13485 #define regRCC_DEV1_EPF2_STRAP6_BASE_IDX 5 13486 #define regRCC_DEV1_EPF2_STRAP13 0xd50d 13487 #define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5 13488 #define regRCC_DEV1_EPF2_STRAP14 0xd50e 13489 #define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5 13490 #define regRCC_DEV1_EPF3_STRAP0 0xd580 13491 #define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5 13492 #define regRCC_DEV1_EPF3_STRAP2 0xd582 13493 #define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5 13494 #define regRCC_DEV1_EPF3_STRAP3 0xd583 13495 #define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5 13496 #define regRCC_DEV1_EPF3_STRAP4 0xd584 13497 #define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5 13498 #define regRCC_DEV1_EPF3_STRAP5 0xd585 13499 #define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5 13500 #define regRCC_DEV1_EPF3_STRAP6 0xd586 13501 #define regRCC_DEV1_EPF3_STRAP6_BASE_IDX 5 13502 #define regRCC_DEV1_EPF3_STRAP13 0xd58d 13503 #define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5 13504 #define regRCC_DEV1_EPF3_STRAP14 0xd58e 13505 #define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5 13506 #define regRCC_DEV1_EPF4_STRAP0 0xd600 13507 #define regRCC_DEV1_EPF4_STRAP0_BASE_IDX 5 13508 #define regRCC_DEV1_EPF4_STRAP2 0xd602 13509 #define regRCC_DEV1_EPF4_STRAP2_BASE_IDX 5 13510 #define regRCC_DEV1_EPF4_STRAP3 0xd603 13511 #define regRCC_DEV1_EPF4_STRAP3_BASE_IDX 5 13512 #define regRCC_DEV1_EPF4_STRAP4 0xd604 13513 #define regRCC_DEV1_EPF4_STRAP4_BASE_IDX 5 13514 #define regRCC_DEV1_EPF4_STRAP5 0xd605 13515 #define regRCC_DEV1_EPF4_STRAP5_BASE_IDX 5 13516 #define regRCC_DEV1_EPF4_STRAP6 0xd606 13517 #define regRCC_DEV1_EPF4_STRAP6_BASE_IDX 5 13518 #define regRCC_DEV1_EPF4_STRAP13 0xd60d 13519 #define regRCC_DEV1_EPF4_STRAP13_BASE_IDX 5 13520 #define regRCC_DEV1_EPF4_STRAP14 0xd60e 13521 #define regRCC_DEV1_EPF4_STRAP14_BASE_IDX 5 13522 #define regRCC_DEV1_EPF5_STRAP0 0xd680 13523 #define regRCC_DEV1_EPF5_STRAP0_BASE_IDX 5 13524 #define regRCC_DEV1_EPF5_STRAP2 0xd682 13525 #define regRCC_DEV1_EPF5_STRAP2_BASE_IDX 5 13526 #define regRCC_DEV1_EPF5_STRAP3 0xd683 13527 #define regRCC_DEV1_EPF5_STRAP3_BASE_IDX 5 13528 #define regRCC_DEV1_EPF5_STRAP4 0xd684 13529 #define regRCC_DEV1_EPF5_STRAP4_BASE_IDX 5 13530 #define regRCC_DEV1_EPF5_STRAP5 0xd685 13531 #define regRCC_DEV1_EPF5_STRAP5_BASE_IDX 5 13532 #define regRCC_DEV1_EPF5_STRAP6 0xd686 13533 #define regRCC_DEV1_EPF5_STRAP6_BASE_IDX 5 13534 #define regRCC_DEV1_EPF5_STRAP13 0xd68d 13535 #define regRCC_DEV1_EPF5_STRAP13_BASE_IDX 5 13536 #define regRCC_DEV1_EPF5_STRAP14 0xd68e 13537 #define regRCC_DEV1_EPF5_STRAP14_BASE_IDX 5 13538 #define regRCC_DEV2_EPF0_STRAP0 0xd800 13539 #define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5 13540 #define regRCC_DEV2_EPF0_STRAP2 0xd802 13541 #define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5 13542 #define regRCC_DEV2_EPF0_STRAP3 0xd803 13543 #define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5 13544 #define regRCC_DEV2_EPF0_STRAP4 0xd804 13545 #define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5 13546 #define regRCC_DEV2_EPF0_STRAP5 0xd805 13547 #define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5 13548 #define regRCC_DEV2_EPF0_STRAP6 0xd806 13549 #define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5 13550 #define regRCC_DEV2_EPF0_STRAP7 0xd807 13551 #define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5 13552 #define regRCC_DEV2_EPF0_STRAP13 0xd80d 13553 #define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5 13554 #define regRCC_DEV2_EPF0_STRAP14 0xd80e 13555 #define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5 13556 #define regRCC_DEV2_EPF1_STRAP0 0xd880 13557 #define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5 13558 #define regRCC_DEV2_EPF1_STRAP2 0xd882 13559 #define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5 13560 #define regRCC_DEV2_EPF1_STRAP3 0xd883 13561 #define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5 13562 #define regRCC_DEV2_EPF1_STRAP4 0xd884 13563 #define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5 13564 #define regRCC_DEV2_EPF1_STRAP5 0xd885 13565 #define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5 13566 #define regRCC_DEV2_EPF1_STRAP6 0xd886 13567 #define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5 13568 #define regRCC_DEV2_EPF1_STRAP13 0xd88d 13569 #define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5 13570 #define regRCC_DEV2_EPF1_STRAP14 0xd88e 13571 #define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5 13572 #define regRCC_DEV2_EPF2_STRAP0 0xd900 13573 #define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5 13574 #define regRCC_DEV2_EPF2_STRAP2 0xd902 13575 #define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5 13576 #define regRCC_DEV2_EPF2_STRAP3 0xd903 13577 #define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5 13578 #define regRCC_DEV2_EPF2_STRAP4 0xd904 13579 #define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5 13580 #define regRCC_DEV2_EPF2_STRAP5 0xd905 13581 #define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5 13582 #define regRCC_DEV2_EPF2_STRAP6 0xd906 13583 #define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5 13584 #define regRCC_DEV2_EPF2_STRAP13 0xd90d 13585 #define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5 13586 #define regRCC_DEV2_EPF2_STRAP14 0xd90e 13587 #define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5 13588 13589 13590 // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk 13591 // base address: 0x10100000 13592 #define regHARD_RST_CTRL 0xe000 13593 #define regHARD_RST_CTRL_BASE_IDX 5 13594 #define regSELF_SOFT_RST 0xe002 13595 #define regSELF_SOFT_RST_BASE_IDX 5 13596 #define regBIF_GFX_DRV_VPU_RST 0xe003 13597 #define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5 13598 #define regBIF_RST_MISC_CTRL 0xe004 13599 #define regBIF_RST_MISC_CTRL_BASE_IDX 5 13600 #define regBIF_RST_MISC_CTRL2 0xe005 13601 #define regBIF_RST_MISC_CTRL2_BASE_IDX 5 13602 #define regBIF_RST_MISC_CTRL3 0xe006 13603 #define regBIF_RST_MISC_CTRL3_BASE_IDX 5 13604 #define regDEV0_PF0_FLR_RST_CTRL 0xe008 13605 #define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5 13606 #define regDEV0_PF1_FLR_RST_CTRL 0xe009 13607 #define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5 13608 #define regDEV0_PF2_FLR_RST_CTRL 0xe00a 13609 #define regDEV0_PF2_FLR_RST_CTRL_BASE_IDX 5 13610 #define regDEV0_PF3_FLR_RST_CTRL 0xe00b 13611 #define regDEV0_PF3_FLR_RST_CTRL_BASE_IDX 5 13612 #define regBIF_INST_RESET_INTR_STS 0xe010 13613 #define regBIF_INST_RESET_INTR_STS_BASE_IDX 5 13614 #define regBIF_PF_FLR_INTR_STS 0xe011 13615 #define regBIF_PF_FLR_INTR_STS_BASE_IDX 5 13616 #define regBIF_D3HOTD0_INTR_STS 0xe012 13617 #define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5 13618 #define regBIF_POWER_INTR_STS 0xe014 13619 #define regBIF_POWER_INTR_STS_BASE_IDX 5 13620 #define regBIF_PF_DSTATE_INTR_STS 0xe015 13621 #define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5 13622 #define regSELF_SOFT_RST_2 0xe016 13623 #define regSELF_SOFT_RST_2_BASE_IDX 5 13624 #define regBIF_INST_RESET_INTR_MASK 0xe020 13625 #define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5 13626 #define regBIF_PF_FLR_INTR_MASK 0xe021 13627 #define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5 13628 #define regBIF_D3HOTD0_INTR_MASK 0xe022 13629 #define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5 13630 #define regBIF_POWER_INTR_MASK 0xe024 13631 #define regBIF_POWER_INTR_MASK_BASE_IDX 5 13632 #define regBIF_PF_DSTATE_INTR_MASK 0xe025 13633 #define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5 13634 #define regBIF_PF_FLR_RST 0xe040 13635 #define regBIF_PF_FLR_RST_BASE_IDX 5 13636 #define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 13637 #define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5 13638 #define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 13639 #define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5 13640 #define regBIF_DEV0_PF2_DSTATE_VALUE 0xe052 13641 #define regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX 5 13642 #define regBIF_DEV0_PF3_DSTATE_VALUE 0xe053 13643 #define regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX 5 13644 #define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 13645 #define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 13646 #define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 13647 #define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 13648 #define regDEV0_PF2_D3HOTD0_RST_CTRL 0xe07a 13649 #define regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX 5 13650 #define regDEV0_PF3_D3HOTD0_RST_CTRL 0xe07b 13651 #define regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX 5 13652 #define regBIF_PORT0_DSTATE_VALUE 0xe230 13653 #define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5 13654 13655 13656 // addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk 13657 // base address: 0x10100000 13658 #define regREGS_ROM_OFFSET_CTRL 0xcc23 13659 #define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5 13660 #define regNBIF_STRAP_BIOS_CNTL 0xcc81 13661 #define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5 13662 #define regMISC_SCRATCH 0xe800 13663 #define regMISC_SCRATCH_BASE_IDX 5 13664 #define regINTR_LINE_POLARITY 0xe801 13665 #define regINTR_LINE_POLARITY_BASE_IDX 5 13666 #define regINTR_LINE_ENABLE 0xe802 13667 #define regINTR_LINE_ENABLE_BASE_IDX 5 13668 #define regOUTSTANDING_VC_ALLOC 0xe803 13669 #define regOUTSTANDING_VC_ALLOC_BASE_IDX 5 13670 #define regBIFC_MISC_CTRL0 0xe804 13671 #define regBIFC_MISC_CTRL0_BASE_IDX 5 13672 #define regBIFC_MISC_CTRL1 0xe805 13673 #define regBIFC_MISC_CTRL1_BASE_IDX 5 13674 #define regBIFC_BME_ERR_LOG_LB 0xe806 13675 #define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5 13676 #define regBIFC_LC_TIMER_CTRL 0xe807 13677 #define regBIFC_LC_TIMER_CTRL_BASE_IDX 5 13678 #define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 13679 #define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5 13680 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a 13681 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5 13682 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b 13683 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5 13684 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c 13685 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5 13686 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d 13687 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5 13688 #define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a 13689 #define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5 13690 #define regBME_DUMMY_CNTL_0 0xe825 13691 #define regBME_DUMMY_CNTL_0_BASE_IDX 5 13692 #define regBIFC_HSTARB_CNTL 0xe828 13693 #define regBIFC_HSTARB_CNTL_BASE_IDX 5 13694 #define regBIFC_GSI_CNTL 0xe829 13695 #define regBIFC_GSI_CNTL_BASE_IDX 5 13696 #define regBIFC_PCIEFUNC_CNTL 0xe82a 13697 #define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5 13698 #define regBIFC_PASID_CHECK_DIS 0xe82b 13699 #define regBIFC_PASID_CHECK_DIS_BASE_IDX 5 13700 #define regBIFC_SDP_CNTL_0 0xe82c 13701 #define regBIFC_SDP_CNTL_0_BASE_IDX 5 13702 #define regBIFC_SDP_CNTL_1 0xe82d 13703 #define regBIFC_SDP_CNTL_1_BASE_IDX 5 13704 #define regBIFC_PASID_STS 0xe82e 13705 #define regBIFC_PASID_STS_BASE_IDX 5 13706 #define regBIFC_ATHUB_ACT_CNTL 0xe82f 13707 #define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5 13708 #define regBIFC_PERF_CNTL_0 0xe830 13709 #define regBIFC_PERF_CNTL_0_BASE_IDX 5 13710 #define regBIFC_PERF_CNTL_1 0xe831 13711 #define regBIFC_PERF_CNTL_1_BASE_IDX 5 13712 #define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 13713 #define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5 13714 #define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 13715 #define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5 13716 #define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 13717 #define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5 13718 #define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 13719 #define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5 13720 #define regNBIF_REGIF_ERRSET_CTRL 0xe836 13721 #define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5 13722 #define regBIFC_SDP_CNTL_2 0xe837 13723 #define regBIFC_SDP_CNTL_2_BASE_IDX 5 13724 #define regNBIF_PGMST_CTRL 0xe838 13725 #define regNBIF_PGMST_CTRL_BASE_IDX 5 13726 #define regNBIF_PGSLV_CTRL 0xe839 13727 #define regNBIF_PGSLV_CTRL_BASE_IDX 5 13728 #define regNBIF_PG_MISC_CTRL 0xe83a 13729 #define regNBIF_PG_MISC_CTRL_BASE_IDX 5 13730 #define regSMN_MST_EP_CNTL3 0xe83c 13731 #define regSMN_MST_EP_CNTL3_BASE_IDX 5 13732 #define regSMN_MST_EP_CNTL4 0xe83d 13733 #define regSMN_MST_EP_CNTL4_BASE_IDX 5 13734 #define regSMN_MST_CNTL1 0xe83e 13735 #define regSMN_MST_CNTL1_BASE_IDX 5 13736 #define regSMN_MST_EP_CNTL5 0xe83f 13737 #define regSMN_MST_EP_CNTL5_BASE_IDX 5 13738 #define regBIF_SELFRING_BUFFER_VID 0xe840 13739 #define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5 13740 #define regBIF_SELFRING_VECTOR_CNTL 0xe841 13741 #define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5 13742 #define regNBIF_STRAP_WRITE_CTRL 0xe845 13743 #define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5 13744 #define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 13745 #define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5 13746 #define regNBIF_PENDING_MISC_CNTL 0xe847 13747 #define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5 13748 #define regBIF_GMI_WRR_WEIGHT 0xe848 13749 #define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5 13750 #define regBIF_GMI_WRR_WEIGHT2 0xe849 13751 #define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5 13752 #define regBIF_GMI_WRR_WEIGHT3 0xe84a 13753 #define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5 13754 #define regNBIF_PWRBRK_REQUEST 0xe84c 13755 #define regNBIF_PWRBRK_REQUEST_BASE_IDX 5 13756 #define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 13757 #define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5 13758 #define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 13759 #define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5 13760 #define regBIF_ATOMIC_ERR_LOG_DEV0_F2 0xe852 13761 #define regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX 5 13762 #define regBIF_ATOMIC_ERR_LOG_DEV0_F3 0xe853 13763 #define regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX 5 13764 #define regBIF_DMA_MP4_ERR_LOG 0xe870 13765 #define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5 13766 #define regBIF_PASID_ERR_LOG 0xe871 13767 #define regBIF_PASID_ERR_LOG_BASE_IDX 5 13768 #define regBIF_PASID_ERR_CLR 0xe872 13769 #define regBIF_PASID_ERR_CLR_BASE_IDX 5 13770 #define regNBIF_VWIRE_CTRL 0xe880 13771 #define regNBIF_VWIRE_CTRL_BASE_IDX 5 13772 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 13773 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 5 13774 #define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 13775 #define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 5 13776 #define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 13777 #define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 5 13778 #define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 13779 #define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 5 13780 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 13781 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 5 13782 #define regNBIF_MGCG_CTRL_LCLK 0xe887 13783 #define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5 13784 #define regNBIF_DS_CTRL_LCLK 0xe888 13785 #define regNBIF_DS_CTRL_LCLK_BASE_IDX 5 13786 #define regSMN_MST_CNTL0 0xe889 13787 #define regSMN_MST_CNTL0_BASE_IDX 5 13788 #define regSMN_MST_EP_CNTL1 0xe88a 13789 #define regSMN_MST_EP_CNTL1_BASE_IDX 5 13790 #define regSMN_MST_EP_CNTL2 0xe88b 13791 #define regSMN_MST_EP_CNTL2_BASE_IDX 5 13792 #define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c 13793 #define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5 13794 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d 13795 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5 13796 #define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e 13797 #define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5 13798 #define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f 13799 #define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5 13800 #define regNBIF_SHUB_TODET_CTRL 0xe898 13801 #define regNBIF_SHUB_TODET_CTRL_BASE_IDX 5 13802 #define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 13803 #define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 5 13804 #define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a 13805 #define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 5 13806 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b 13807 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 5 13808 #define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c 13809 #define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 5 13810 #define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d 13811 #define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 5 13812 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e 13813 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 5 13814 #define regBIFC_BME_ERR_LOG_HB 0xe8ab 13815 #define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5 13816 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 13817 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 13818 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 13819 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 13820 #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 13821 #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 13822 #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 13823 #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 13824 #define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4 13825 #define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 13826 #define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5 13827 #define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 13828 #define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 13829 #define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5 13830 #define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 13831 #define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5 13832 #define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 13833 #define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5 13834 #define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 13835 #define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5 13836 #define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 13837 #define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5 13838 #define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 13839 #define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5 13840 13841 13842 // addressBlock: nbio_nbif0_bif_misc_pfvf_bif_misc_pfvf_regblk 13843 // base address: 0x10100000 13844 13845 13846 // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk 13847 // base address: 0x10100000 13848 #define regBIFL_RAS_CENTRAL_CNTL 0xe400 13849 #define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5 13850 #define regBIFL_RAS_CENTRAL_STATUS 0xe410 13851 #define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5 13852 #define regBIFL_RAS_LEAF0_CTRL 0xe420 13853 #define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5 13854 #define regBIFL_RAS_LEAF1_CTRL 0xe421 13855 #define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5 13856 #define regBIFL_RAS_LEAF2_CTRL 0xe422 13857 #define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5 13858 #define regBIFL_RAS_LEAF3_CTRL 0xe423 13859 #define regBIFL_RAS_LEAF3_CTRL_BASE_IDX 5 13860 #define regBIFL_RAS_LEAF0_STATUS 0xe430 13861 #define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5 13862 #define regBIFL_RAS_LEAF1_STATUS 0xe431 13863 #define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5 13864 #define regBIFL_RAS_LEAF2_STATUS 0xe432 13865 #define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5 13866 #define regBIFL_RAS_LEAF3_STATUS 0xe433 13867 #define regBIFL_RAS_LEAF3_STATUS_BASE_IDX 5 13868 #define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe 13869 #define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5 13870 #define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff 13871 #define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5 13872 13873 13874 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 13875 // base address: 0x10120000 13876 #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80 13877 #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5 13878 #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81 13879 #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5 13880 #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83 13881 #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5 13882 #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84 13883 #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 13884 #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85 13885 #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5 13886 #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86 13887 #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5 13888 #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87 13889 #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5 13890 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88 13891 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5 13892 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89 13893 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5 13894 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a 13895 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5 13896 13897 13898 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 13899 // base address: 0x10120000 13900 #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c 13901 #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5 13902 #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d 13903 #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5 13904 #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e 13905 #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5 13906 #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f 13907 #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5 13908 #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90 13909 #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5 13910 #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91 13911 #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 13912 13913 13914 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 13915 // base address: 0x10120000 13916 #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d60 13917 #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5 13918 #define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d62 13919 #define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5 13920 #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d63 13921 #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5 13922 #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d64 13923 #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5 13924 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d65 13925 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5 13926 #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d66 13927 #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5 13928 #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d67 13929 #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5 13930 #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d69 13931 #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 13932 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6a 13933 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 13934 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6a 13935 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 13936 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6a 13937 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 13938 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6a 13939 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 13940 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6b 13941 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 13942 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6b 13943 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 13944 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6b 13945 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 13946 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6b 13947 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 13948 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6c 13949 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5 13950 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6d 13951 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5 13952 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d6f 13953 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 13954 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d70 13955 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 13956 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d70 13957 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 13958 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d70 13959 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 13960 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d71 13961 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 13962 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d71 13963 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 13964 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d71 13965 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 13966 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d71 13967 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 13968 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d72 13969 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 13970 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d72 13971 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 13972 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d72 13973 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 13974 #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d72 13975 #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5 13976 #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d73 13977 #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5 13978 #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d75 13979 #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5 13980 #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d76 13981 #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 13982 #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d77 13983 #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5 13984 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d78 13985 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5 13986 #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d79 13987 #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 13988 13989 13990 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 13991 // base address: 0x10120000 13992 #define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 13993 #define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5 13994 #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 13995 #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5 13996 #define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 13997 #define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5 13998 #define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 13999 #define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5 14000 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa 14001 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 14002 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab 14003 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 14004 #define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac 14005 #define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5 14006 #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad 14007 #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5 14008 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae 14009 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5 14010 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf 14011 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5 14012 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf 14013 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5 14014 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde 14015 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5 14016 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf 14017 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5 14018 #define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 14019 #define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5 14020 #define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 14021 #define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5 14022 #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 14023 #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5 14024 #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 14025 #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5 14026 #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 14027 #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5 14028 #define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 14029 #define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5 14030 #define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea 14031 #define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5 14032 #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb 14033 #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 14034 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec 14035 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5 14036 #define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded 14037 #define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5 14038 #define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee 14039 #define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5 14040 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def 14041 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5 14042 #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 14043 #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5 14044 #define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 14045 #define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5 14046 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 14047 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5 14048 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 14049 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5 14050 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 14051 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5 14052 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 14053 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5 14054 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 14055 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5 14056 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 14057 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5 14058 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 14059 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5 14060 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 14061 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5 14062 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa 14063 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5 14064 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb 14065 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5 14066 #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd 14067 #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5 14068 #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe 14069 #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5 14070 #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff 14071 #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 14072 #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 14073 #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 14074 #define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 14075 #define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5 14076 14077 14078 // addressBlock: nbio_nbif0_bif_bx_SYSDEC 14079 // base address: 0x10120000 14080 #define regBIF_BX1_PCIE_INDEX 0x800c 14081 #define regBIF_BX1_PCIE_INDEX_BASE_IDX 5 14082 #define regBIF_BX1_PCIE_DATA 0x800d 14083 #define regBIF_BX1_PCIE_DATA_BASE_IDX 5 14084 #define regBIF_BX1_PCIE_INDEX2 0x800e 14085 #define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5 14086 #define regBIF_BX1_PCIE_DATA2 0x800f 14087 #define regBIF_BX1_PCIE_DATA2_BASE_IDX 5 14088 #define regBIF_BX1_PCIE_INDEX_HI 0x8010 14089 #define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 5 14090 #define regBIF_BX1_PCIE_INDEX2_HI 0x8011 14091 #define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 5 14092 #define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 14093 #define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5 14094 #define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 14095 #define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5 14096 #define regBIF_BX1_SBIOS_SCRATCH_2 0x804a 14097 #define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5 14098 #define regBIF_BX1_SBIOS_SCRATCH_3 0x804b 14099 #define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5 14100 #define regBIF_BX1_BIOS_SCRATCH_0 0x804c 14101 #define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5 14102 #define regBIF_BX1_BIOS_SCRATCH_1 0x804d 14103 #define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5 14104 #define regBIF_BX1_BIOS_SCRATCH_2 0x804e 14105 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5 14106 #define regBIF_BX1_BIOS_SCRATCH_3 0x804f 14107 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5 14108 #define regBIF_BX1_BIOS_SCRATCH_4 0x8050 14109 #define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5 14110 #define regBIF_BX1_BIOS_SCRATCH_5 0x8051 14111 #define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5 14112 #define regBIF_BX1_BIOS_SCRATCH_6 0x8052 14113 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5 14114 #define regBIF_BX1_BIOS_SCRATCH_7 0x8053 14115 #define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5 14116 #define regBIF_BX1_BIOS_SCRATCH_8 0x8054 14117 #define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5 14118 #define regBIF_BX1_BIOS_SCRATCH_9 0x8055 14119 #define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5 14120 #define regBIF_BX1_BIOS_SCRATCH_10 0x8056 14121 #define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5 14122 #define regBIF_BX1_BIOS_SCRATCH_11 0x8057 14123 #define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5 14124 #define regBIF_BX1_BIOS_SCRATCH_12 0x8058 14125 #define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5 14126 #define regBIF_BX1_BIOS_SCRATCH_13 0x8059 14127 #define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5 14128 #define regBIF_BX1_BIOS_SCRATCH_14 0x805a 14129 #define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5 14130 #define regBIF_BX1_BIOS_SCRATCH_15 0x805b 14131 #define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5 14132 #define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 14133 #define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5 14134 #define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 14135 #define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5 14136 #define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 14137 #define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5 14138 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 14139 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5 14140 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 14141 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5 14142 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 14143 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5 14144 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 14145 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5 14146 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 14147 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5 14148 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 14149 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5 14150 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 14151 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5 14152 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 14153 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5 14154 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 14155 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5 14156 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 14157 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5 14158 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a 14159 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5 14160 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b 14161 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5 14162 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c 14163 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5 14164 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d 14165 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5 14166 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e 14167 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5 14168 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f 14169 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5 14170 #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 14171 #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5 14172 #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 14173 #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5 14174 #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 14175 #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5 14176 #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 14177 #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5 14178 #define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 14179 #define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 5 14180 #define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 14181 #define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 5 14182 #define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 14183 #define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 5 14184 #define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 14185 #define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 5 14186 #define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 14187 #define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 5 14188 #define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 14189 #define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 5 14190 #define regBIF_BX1_DRIVER_SCRATCH_6 0x809a 14191 #define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 5 14192 #define regBIF_BX1_DRIVER_SCRATCH_7 0x809b 14193 #define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 5 14194 #define regBIF_BX1_DRIVER_SCRATCH_8 0x809c 14195 #define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 5 14196 #define regBIF_BX1_DRIVER_SCRATCH_9 0x809d 14197 #define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 5 14198 #define regBIF_BX1_DRIVER_SCRATCH_10 0x809e 14199 #define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 5 14200 #define regBIF_BX1_DRIVER_SCRATCH_11 0x809f 14201 #define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 5 14202 #define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 14203 #define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 5 14204 #define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 14205 #define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 5 14206 #define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 14207 #define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 5 14208 #define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 14209 #define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 5 14210 #define regBIF_BX1_FW_SCRATCH_0 0x80a4 14211 #define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 5 14212 #define regBIF_BX1_FW_SCRATCH_1 0x80a5 14213 #define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 5 14214 #define regBIF_BX1_FW_SCRATCH_2 0x80a6 14215 #define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 5 14216 #define regBIF_BX1_FW_SCRATCH_3 0x80a7 14217 #define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 5 14218 #define regBIF_BX1_FW_SCRATCH_4 0x80a8 14219 #define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 5 14220 #define regBIF_BX1_FW_SCRATCH_5 0x80a9 14221 #define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 5 14222 #define regBIF_BX1_FW_SCRATCH_6 0x80aa 14223 #define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 5 14224 #define regBIF_BX1_FW_SCRATCH_7 0x80ab 14225 #define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 5 14226 #define regBIF_BX1_FW_SCRATCH_8 0x80ac 14227 #define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 5 14228 #define regBIF_BX1_FW_SCRATCH_9 0x80ad 14229 #define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 5 14230 #define regBIF_BX1_FW_SCRATCH_10 0x80ae 14231 #define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 5 14232 #define regBIF_BX1_FW_SCRATCH_11 0x80af 14233 #define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 5 14234 #define regBIF_BX1_FW_SCRATCH_12 0x80b0 14235 #define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 5 14236 #define regBIF_BX1_FW_SCRATCH_13 0x80b1 14237 #define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 5 14238 #define regBIF_BX1_FW_SCRATCH_14 0x80b2 14239 #define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 5 14240 #define regBIF_BX1_FW_SCRATCH_15 0x80b3 14241 #define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 5 14242 #define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 14243 #define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 5 14244 #define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 14245 #define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 5 14246 #define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 14247 #define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 5 14248 #define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 14249 #define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 5 14250 #define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 14251 #define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 5 14252 #define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 14253 #define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 5 14254 #define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba 14255 #define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 5 14256 #define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb 14257 #define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 5 14258 #define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc 14259 #define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 5 14260 #define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd 14261 #define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 5 14262 #define regBIF_BX1_SBIOS_SCRATCH_14 0x80be 14263 #define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 5 14264 #define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf 14265 #define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 5 14266 14267 14268 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 14269 // base address: 0x10120000 14270 #define regBIF_BX_PF1_MM_INDEX 0x8000 14271 #define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5 14272 #define regBIF_BX_PF1_MM_DATA 0x8001 14273 #define regBIF_BX_PF1_MM_DATA_BASE_IDX 5 14274 #define regBIF_BX_PF1_MM_INDEX_HI 0x8006 14275 #define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5 14276 14277 14278 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 14279 // base address: 0x10120000 14280 #define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 14281 #define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5 14282 #define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 14283 #define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5 14284 #define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 14285 #define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5 14286 #define regBIF_BX1_BUS_CNTL 0x8e07 14287 #define regBIF_BX1_BUS_CNTL_BASE_IDX 5 14288 #define regBIF_BX1_BIF_SCRATCH0 0x8e08 14289 #define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5 14290 #define regBIF_BX1_BIF_SCRATCH1 0x8e09 14291 #define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5 14292 #define regBIF_BX1_BX_RESET_EN 0x8e0d 14293 #define regBIF_BX1_BX_RESET_EN_BASE_IDX 5 14294 #define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e 14295 #define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5 14296 #define regBIF_BX1_BX_RESET_CNTL 0x8e10 14297 #define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5 14298 #define regBIF_BX1_INTERRUPT_CNTL 0x8e11 14299 #define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5 14300 #define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 14301 #define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5 14302 #define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 14303 #define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5 14304 #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b 14305 #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5 14306 #define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c 14307 #define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 5 14308 #define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d 14309 #define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5 14310 #define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e 14311 #define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5 14312 #define regBIF_BX1_BIF_FB_EN 0x8e20 14313 #define regBIF_BX1_BIF_FB_EN_BASE_IDX 5 14314 #define regBIF_BX1_BIF_INTR_CNTL 0x8e21 14315 #define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5 14316 #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 14317 #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5 14318 #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a 14319 #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5 14320 #define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 14321 #define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5 14322 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 14323 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 5 14324 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 14325 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 5 14326 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 14327 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 5 14328 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 14329 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 5 14330 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 14331 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 5 14332 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 14333 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 5 14334 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 14335 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 5 14336 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a 14337 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 5 14338 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b 14339 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 5 14340 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c 14341 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 5 14342 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d 14343 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 5 14344 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e 14345 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 5 14346 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f 14347 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 5 14348 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 14349 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 5 14350 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 14351 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 5 14352 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 14353 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 5 14354 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 14355 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 5 14356 #define regBIF_BX1_VF_REGWR_EN 0x8e44 14357 #define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5 14358 #define regBIF_BX1_VF_DOORBELL_EN 0x8e45 14359 #define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5 14360 #define regBIF_BX1_VF_FB_EN 0x8e46 14361 #define regBIF_BX1_VF_FB_EN_BASE_IDX 5 14362 #define regBIF_BX1_VF_REGWR_STATUS 0x8e47 14363 #define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5 14364 #define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 14365 #define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5 14366 #define regBIF_BX1_VF_FB_STATUS 0x8e49 14367 #define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5 14368 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d 14369 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5 14370 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e 14371 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5 14372 #define regBIF_BX1_BIF_RB_CNTL 0x8e4f 14373 #define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5 14374 #define regBIF_BX1_BIF_RB_BASE 0x8e50 14375 #define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5 14376 #define regBIF_BX1_BIF_RB_RPTR 0x8e51 14377 #define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5 14378 #define regBIF_BX1_BIF_RB_WPTR 0x8e52 14379 #define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5 14380 #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 14381 #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5 14382 #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 14383 #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5 14384 #define regBIF_BX1_MAILBOX_INDEX 0x8e55 14385 #define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5 14386 #define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 14387 #define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 5 14388 #define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0x8e63 14389 #define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 5 14390 #define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0x8e64 14391 #define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 5 14392 #define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x8e65 14393 #define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 5 14394 #define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e68 14395 #define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5 14396 #define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e69 14397 #define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5 14398 #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e6a 14399 #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5 14400 #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e6b 14401 #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5 14402 #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e6c 14403 #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5 14404 #define regBIF_BX1_BIF_WAKEB_PAD_CNTL 0x8e6d 14405 #define regBIF_BX1_BIF_WAKEB_PAD_CNTL_BASE_IDX 5 14406 #define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL 0x8e6e 14407 #define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX 5 14408 #define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL 0x8e70 14409 #define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX 5 14410 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0 0x8e71 14411 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX 5 14412 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1 0x8e72 14413 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1_BASE_IDX 5 14414 #define regBIF_BX1_BIF_S5_DUMMY_REGS 0x8e73 14415 #define regBIF_BX1_BIF_S5_DUMMY_REGS_BASE_IDX 5 14416 14417 14418 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 14419 // base address: 0x10120000 14420 #define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b 14421 #define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5 14422 #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c 14423 #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 14424 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 14425 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 14426 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 14427 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 14428 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 14429 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 14430 #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 14431 #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 14432 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 14433 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 14434 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 14435 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 14436 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a 14437 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 14438 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 14439 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5 14440 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 14441 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5 14442 #define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 14443 #define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5 14444 #define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 14445 #define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 14446 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 14447 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 14448 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 14449 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 14450 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 14451 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 14452 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 14453 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 14454 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a 14455 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 14456 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b 14457 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 14458 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c 14459 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 14460 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d 14461 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 14462 #define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e 14463 #define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5 14464 #define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f 14465 #define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5 14466 #define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 14467 #define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5 14468 14469 14470 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1 14471 // base address: 0x10120000 14472 #define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 14473 #define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5 14474 #define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 14475 #define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5 14476 #define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d22 14477 #define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5 14478 #define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d23 14479 #define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5 14480 #define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d24 14481 #define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5 14482 #define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d25 14483 #define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5 14484 #define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d26 14485 #define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5 14486 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d27 14487 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 14488 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d28 14489 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 14490 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d29 14491 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 14492 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d2a 14493 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 14494 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d2b 14495 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 14496 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d2c 14497 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 14498 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d2d 14499 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 14500 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d2e 14501 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 14502 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d2f 14503 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 14504 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d30 14505 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 14506 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d31 14507 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 14508 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d32 14509 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 14510 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d33 14511 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 14512 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d34 14513 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 14514 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d35 14515 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 14516 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d36 14517 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 14518 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d37 14519 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 14520 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d38 14521 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 14522 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d39 14523 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 14524 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d3a 14525 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 14526 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d3b 14527 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 14528 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d3c 14529 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 14530 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d3d 14531 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 14532 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d3e 14533 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 14534 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 0x8d3f 14535 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX 5 14536 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d40 14537 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 14538 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d41 14539 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 14540 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d42 14541 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 14542 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d43 14543 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 14544 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d44 14545 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 14546 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d45 14547 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 14548 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d51 14549 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 14550 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d52 14551 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 14552 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d53 14553 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 14554 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 0x8d54 14555 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX 5 14556 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d55 14557 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 14558 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d56 14559 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 14560 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 0x8d57 14561 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX 5 14562 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d58 14563 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 14564 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d59 14565 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 14566 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5a 14567 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 14568 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5b 14569 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 14570 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5c 14571 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 14572 14573 14574 // addressBlock: nbio_nbif0_gdc_dma_sion_SIONDEC 14575 // base address: 0x1400000 14576 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7400 14577 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 14578 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7401 14579 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 14580 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7402 14581 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 14582 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7403 14583 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 14584 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7404 14585 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 14586 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7405 14587 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 14588 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7406 14589 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 14590 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7407 14591 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 14592 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 0x4f7408 14593 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 14594 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 0x4f7409 14595 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 14596 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 0x4f740a 14597 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 14598 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 0x4f740b 14599 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 14600 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f740c 14601 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 14602 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f740d 14603 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 14604 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f740e 14605 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 14606 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f740f 14607 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 14608 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7410 14609 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 14610 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7411 14611 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 14612 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7412 14613 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 14614 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7413 14615 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 14616 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7414 14617 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 14618 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7415 14619 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 14620 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7416 14621 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 14622 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7417 14623 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 14624 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7418 14625 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 14626 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7419 14627 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 14628 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 0x4f741a 14629 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 14630 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 0x4f741b 14631 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 14632 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 0x4f741c 14633 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 14634 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 0x4f741d 14635 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 14636 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 0x4f741e 14637 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 14638 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 0x4f741f 14639 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 14640 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7420 14641 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 14642 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7421 14643 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 14644 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7422 14645 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 14646 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7423 14647 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 14648 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7424 14649 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 14650 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7425 14651 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 14652 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7426 14653 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 14654 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7427 14655 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 14656 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7428 14657 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 14658 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7429 14659 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 14660 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 0x4f742a 14661 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 14662 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 0x4f742b 14663 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 14664 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 0x4f742c 14665 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 14666 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 0x4f742d 14667 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 14668 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 0x4f742e 14669 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 14670 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 0x4f742f 14671 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 14672 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 0x4f7430 14673 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 14674 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 0x4f7431 14675 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 14676 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 0x4f7432 14677 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 14678 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 0x4f7433 14679 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 14680 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7434 14681 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 14682 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7435 14683 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 14684 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7436 14685 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 14686 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7437 14687 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 14688 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7438 14689 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 14690 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7439 14691 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 14692 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f743a 14693 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 14694 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f743b 14695 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 14696 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0 0x4f743c 14697 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0_BASE_IDX 3 14698 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1 0x4f743d 14699 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1_BASE_IDX 3 14700 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0 0x4f743e 14701 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0_BASE_IDX 3 14702 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1 0x4f743f 14703 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1_BASE_IDX 3 14704 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0 0x4f7440 14705 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0_BASE_IDX 3 14706 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1 0x4f7441 14707 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1_BASE_IDX 3 14708 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0 0x4f7442 14709 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0_BASE_IDX 3 14710 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1 0x4f7443 14711 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1_BASE_IDX 3 14712 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0 0x4f7444 14713 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0_BASE_IDX 3 14714 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1 0x4f7445 14715 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1_BASE_IDX 3 14716 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0 0x4f7446 14717 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0_BASE_IDX 3 14718 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1 0x4f7447 14719 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1_BASE_IDX 3 14720 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0 0x4f7448 14721 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 14722 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1 0x4f7449 14723 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 14724 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0 0x4f744a 14725 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0_BASE_IDX 3 14726 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1 0x4f744b 14727 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1_BASE_IDX 3 14728 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0 0x4f744c 14729 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 14730 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1 0x4f744d 14731 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 14732 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0 0x4f744e 14733 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 14734 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1 0x4f744f 14735 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 14736 #define regGDC_DMA_SION_CNTL_REG0 0x4f7450 14737 #define regGDC_DMA_SION_CNTL_REG0_BASE_IDX 3 14738 #define regGDC_DMA_SION_CNTL_REG1 0x4f7451 14739 #define regGDC_DMA_SION_CNTL_REG1_BASE_IDX 3 14740 14741 14742 // addressBlock: nbio_nbif0_gdc_hst_sion_SIONDEC 14743 // base address: 0x1400000 14744 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7600 14745 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 14746 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7601 14747 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 14748 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7602 14749 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 14750 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7603 14751 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 14752 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7604 14753 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 14754 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7605 14755 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 14756 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7606 14757 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 14758 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7607 14759 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 14760 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG0 0x4f7608 14761 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 14762 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG1 0x4f7609 14763 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 14764 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG0 0x4f760a 14765 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 14766 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG1 0x4f760b 14767 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 14768 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f760c 14769 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 14770 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f760d 14771 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 14772 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f760e 14773 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 14774 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f760f 14775 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 14776 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7610 14777 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 14778 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7611 14779 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 14780 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7612 14781 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 14782 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7613 14783 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 14784 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7614 14785 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 14786 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7615 14787 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 14788 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7616 14789 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 14790 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7617 14791 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 14792 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7618 14793 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 14794 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7619 14795 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 14796 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 0x4f761a 14797 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 14798 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 0x4f761b 14799 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 14800 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG0 0x4f761c 14801 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 14802 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG1 0x4f761d 14803 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 14804 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG0 0x4f761e 14805 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 14806 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG1 0x4f761f 14807 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 14808 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7620 14809 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 14810 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7621 14811 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 14812 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7622 14813 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 14814 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7623 14815 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 14816 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7624 14817 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 14818 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7625 14819 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 14820 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7626 14821 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 14822 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7627 14823 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 14824 #define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7628 14825 #define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 14826 #define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7629 14827 #define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 14828 #define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0 0x4f762a 14829 #define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 14830 #define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1 0x4f762b 14831 #define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 14832 #define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0 0x4f762c 14833 #define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 14834 #define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1 0x4f762d 14835 #define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 14836 #define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0 0x4f762e 14837 #define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 14838 #define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1 0x4f762f 14839 #define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 14840 #define regGDC_HST_SION_CL2_Req_BurstTarget_REG0 0x4f7630 14841 #define regGDC_HST_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 14842 #define regGDC_HST_SION_CL2_Req_BurstTarget_REG1 0x4f7631 14843 #define regGDC_HST_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 14844 #define regGDC_HST_SION_CL2_Req_TimeSlot_REG0 0x4f7632 14845 #define regGDC_HST_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 14846 #define regGDC_HST_SION_CL2_Req_TimeSlot_REG1 0x4f7633 14847 #define regGDC_HST_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 14848 #define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7634 14849 #define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 14850 #define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7635 14851 #define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 14852 #define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7636 14853 #define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 14854 #define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7637 14855 #define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 14856 #define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7638 14857 #define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 14858 #define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7639 14859 #define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 14860 #define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f763a 14861 #define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 14862 #define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f763b 14863 #define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 14864 #define regGDC_HST_SION_CNTL_REG0 0x4f763c 14865 #define regGDC_HST_SION_CNTL_REG0_BASE_IDX 3 14866 #define regGDC_HST_SION_CNTL_REG1 0x4f763d 14867 #define regGDC_HST_SION_CNTL_REG1_BASE_IDX 3 14868 #define regS2A_DOORBELL_ENTRY_0_CTRL 0x4f7640 14869 #define regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3 14870 #define regS2A_DOORBELL_ENTRY_1_CTRL 0x4f7641 14871 #define regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3 14872 #define regS2A_DOORBELL_ENTRY_2_CTRL 0x4f7642 14873 #define regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3 14874 #define regS2A_DOORBELL_ENTRY_3_CTRL 0x4f7643 14875 #define regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3 14876 #define regS2A_DOORBELL_ENTRY_4_CTRL 0x4f7644 14877 #define regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3 14878 #define regS2A_DOORBELL_ENTRY_5_CTRL 0x4f7645 14879 #define regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3 14880 #define regS2A_DOORBELL_ENTRY_6_CTRL 0x4f7646 14881 #define regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 3 14882 #define regS2A_DOORBELL_ENTRY_7_CTRL 0x4f7647 14883 #define regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 3 14884 #define regS2A_DOORBELL_ENTRY_8_CTRL 0x4f7648 14885 #define regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 3 14886 #define regS2A_DOORBELL_ENTRY_9_CTRL 0x4f7649 14887 #define regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 3 14888 #define regS2A_DOORBELL_ENTRY_10_CTRL 0x4f764a 14889 #define regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 3 14890 #define regS2A_DOORBELL_ENTRY_11_CTRL 0x4f764b 14891 #define regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 3 14892 #define regS2A_DOORBELL_ENTRY_12_CTRL 0x4f764c 14893 #define regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 3 14894 #define regS2A_DOORBELL_ENTRY_13_CTRL 0x4f764d 14895 #define regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 3 14896 #define regS2A_DOORBELL_ENTRY_14_CTRL 0x4f764e 14897 #define regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 3 14898 #define regS2A_DOORBELL_ENTRY_15_CTRL 0x4f764f 14899 #define regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 3 14900 #define regS2A_DOORBELL_COMMON_CTRL_REG 0x4f7650 14901 #define regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 3 14902 14903 14904 // addressBlock: nbio_nbif0_gdc_GDCDEC 14905 // base address: 0x1400000 14906 #define regGDC1_SHUB_REGS_IF_CTL 0x4f0ae3 14907 #define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 3 14908 #define regGDC1_NGDC_MGCG_CTRL 0x4f0aea 14909 #define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 3 14910 #define regGDC1_NGDC_RESERVED_0 0x4f0aeb 14911 #define regGDC1_NGDC_RESERVED_0_BASE_IDX 3 14912 #define regGDC1_NGDC_RESERVED_1 0x4f0aec 14913 #define regGDC1_NGDC_RESERVED_1_BASE_IDX 3 14914 #define regGDC1_NBIF_GFX_DOORBELL_STATUS 0x4f0aef 14915 #define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 14916 #define regGDC1_ATDMA_MISC_CNTL 0x4f0afd 14917 #define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 3 14918 #define regGDC1_S2A_MISC_CNTL 0x4f0aff 14919 #define regGDC1_S2A_MISC_CNTL_BASE_IDX 3 14920 #define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x4f0b01 14921 #define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 3 14922 #define regGDC1_NGDC_PG_MISC_CTRL 0x4f0b18 14923 #define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 3 14924 #define regGDC1_NGDC_PGMST_CTRL 0x4f0b19 14925 #define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 3 14926 #define regGDC1_NGDC_PGSLV_CTRL 0x4f0b1a 14927 #define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 3 14928 14929 14930 // addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk 14931 // base address: 0x1400000 14932 #define regGDCSOC_ERR_RSP_CNTL 0x4f5c00 14933 #define regGDCSOC_ERR_RSP_CNTL_BASE_IDX 3 14934 #define regGDCSOC_RAS_CENTRAL_STATUS 0x4f5c10 14935 #define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX 3 14936 #define regGDCSOC_RAS_LEAF0_CTRL 0x4f5c20 14937 #define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX 3 14938 #define regGDCSOC_RAS_LEAF1_CTRL 0x4f5c21 14939 #define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX 3 14940 #define regGDCSOC_RAS_LEAF2_CTRL 0x4f5c22 14941 #define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX 3 14942 #define regGDCSOC_RAS_LEAF3_CTRL 0x4f5c23 14943 #define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX 3 14944 #define regGDCSOC_RAS_LEAF4_CTRL 0x4f5c24 14945 #define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX 3 14946 #define regGDCSOC_RAS_LEAF2_MISC_CTRL 0x4f5c2e 14947 #define regGDCSOC_RAS_LEAF2_MISC_CTRL_BASE_IDX 3 14948 #define regGDCSOC_RAS_LEAF2_MISC_CTRL2 0x4f5c2f 14949 #define regGDCSOC_RAS_LEAF2_MISC_CTRL2_BASE_IDX 3 14950 #define regGDCSOC_RAS_LEAF0_STATUS 0x4f5c30 14951 #define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX 3 14952 #define regGDCSOC_RAS_LEAF1_STATUS 0x4f5c31 14953 #define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX 3 14954 #define regGDCSOC_RAS_LEAF2_STATUS 0x4f5c32 14955 #define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX 3 14956 #define regGDCSOC_RAS_LEAF3_STATUS 0x4f5c33 14957 #define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX 3 14958 #define regGDCSOC_RAS_LEAF4_STATUS 0x4f5c34 14959 #define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX 3 14960 14961 14962 // addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC 14963 // base address: 0x1400000 14964 #define regSHUB_PF_FLR_RST 0x4f7800 14965 #define regSHUB_PF_FLR_RST_BASE_IDX 3 14966 #define regSHUB_GFX_DRV_VPU_RST 0x4f7801 14967 #define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 3 14968 #define regSHUB_LINK_RESET 0x4f7802 14969 #define regSHUB_LINK_RESET_BASE_IDX 3 14970 #define regSHUB_HARD_RST_CTRL 0x4f7810 14971 #define regSHUB_HARD_RST_CTRL_BASE_IDX 3 14972 #define regSHUB_SOFT_RST_CTRL 0x4f7811 14973 #define regSHUB_SOFT_RST_CTRL_BASE_IDX 3 14974 #define regSHUB_SDP_PORT_RST 0x4f7812 14975 #define regSHUB_SDP_PORT_RST_BASE_IDX 3 14976 #define regSHUB_RST_MISC_TRL 0x4f7813 14977 #define regSHUB_RST_MISC_TRL_BASE_IDX 3 14978 14979 14980 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect 14981 // base address: 0x1400000 14982 #define regHST_CLK0_SW0_CL0_CNTL 0x4f3d40 14983 #define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 3 14984 #define regHST_CLK0_SW1_CL0_CNTL 0x4f3d60 14985 #define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 3 14986 14987 14988 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp 14989 // base address: 0x0 14990 #define cfgPSWUSCFG0_1_VENDOR_ID 0x0000 14991 #define cfgPSWUSCFG0_1_DEVICE_ID 0x0002 14992 #define cfgPSWUSCFG0_1_COMMAND 0x0004 14993 #define cfgPSWUSCFG0_1_STATUS 0x0006 14994 #define cfgPSWUSCFG0_1_REVISION_ID 0x0008 14995 #define cfgPSWUSCFG0_1_PROG_INTERFACE 0x0009 14996 #define cfgPSWUSCFG0_1_SUB_CLASS 0x000a 14997 #define cfgPSWUSCFG0_1_BASE_CLASS 0x000b 14998 #define cfgPSWUSCFG0_1_CACHE_LINE 0x000c 14999 #define cfgPSWUSCFG0_1_LATENCY 0x000d 15000 #define cfgPSWUSCFG0_1_HEADER 0x000e 15001 #define cfgPSWUSCFG0_1_BIST 0x000f 15002 #define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY 0x0018 15003 #define cfgPSWUSCFG0_1_IO_BASE_LIMIT 0x001c 15004 #define cfgPSWUSCFG0_1_SECONDARY_STATUS 0x001e 15005 #define cfgPSWUSCFG0_1_MEM_BASE_LIMIT 0x0020 15006 #define cfgPSWUSCFG0_1_PREF_BASE_LIMIT 0x0024 15007 #define cfgPSWUSCFG0_1_PREF_BASE_UPPER 0x0028 15008 #define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER 0x002c 15009 #define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI 0x0030 15010 #define cfgPSWUSCFG0_1_CAP_PTR 0x0034 15011 #define cfgPSWUSCFG0_1_ROM_BASE_ADDR 0x0038 15012 #define cfgPSWUSCFG0_1_INTERRUPT_LINE 0x003c 15013 #define cfgPSWUSCFG0_1_INTERRUPT_PIN 0x003d 15014 #define cfgPSWUSCFG0_1_VENDOR_CAP_LIST 0x0048 15015 #define cfgPSWUSCFG0_1_ADAPTER_ID_W 0x004c 15016 #define cfgPSWUSCFG0_1_PMI_CAP_LIST 0x0050 15017 #define cfgPSWUSCFG0_1_PMI_CAP 0x0052 15018 #define cfgPSWUSCFG0_1_PMI_STATUS_CNTL 0x0054 15019 #define cfgPSWUSCFG0_1_PCIE_CAP_LIST 0x0058 15020 #define cfgPSWUSCFG0_1_PCIE_CAP 0x005a 15021 #define cfgPSWUSCFG0_1_DEVICE_CAP 0x005c 15022 #define cfgPSWUSCFG0_1_DEVICE_CNTL 0x0060 15023 #define cfgPSWUSCFG0_1_DEVICE_STATUS 0x0062 15024 #define cfgPSWUSCFG0_1_LINK_CAP 0x0064 15025 #define cfgPSWUSCFG0_1_LINK_CNTL 0x0068 15026 #define cfgPSWUSCFG0_1_LINK_STATUS 0x006a 15027 #define cfgPSWUSCFG0_1_DEVICE_CAP2 0x007c 15028 #define cfgPSWUSCFG0_1_DEVICE_CNTL2 0x0080 15029 #define cfgPSWUSCFG0_1_DEVICE_STATUS2 0x0082 15030 #define cfgPSWUSCFG0_1_LINK_CAP2 0x0084 15031 #define cfgPSWUSCFG0_1_LINK_CNTL2 0x0088 15032 #define cfgPSWUSCFG0_1_LINK_STATUS2 0x008a 15033 #define cfgPSWUSCFG0_1_MSI_CAP_LIST 0x00a0 15034 #define cfgPSWUSCFG0_1_MSI_MSG_CNTL 0x00a2 15035 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO 0x00a4 15036 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI 0x00a8 15037 #define cfgPSWUSCFG0_1_MSI_MSG_DATA 0x00a8 15038 #define cfgPSWUSCFG0_1_MSI_MSG_DATA_64 0x00ac 15039 #define cfgPSWUSCFG0_1_SSID_CAP_LIST 0x00c0 15040 #define cfgPSWUSCFG0_1_SSID_CAP 0x00c4 15041 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15042 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15043 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 0x0108 15044 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 0x010c 15045 #define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST 0x0110 15046 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 0x0114 15047 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 0x0118 15048 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL 0x011c 15049 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS 0x011e 15050 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP 0x0120 15051 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL 0x0124 15052 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS 0x012a 15053 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP 0x012c 15054 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL 0x0130 15055 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS 0x0136 15056 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 15057 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 15058 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 15059 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15060 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS 0x0154 15061 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK 0x0158 15062 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 15063 #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS 0x0160 15064 #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK 0x0164 15065 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 15066 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG0 0x016c 15067 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG1 0x0170 15068 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG2 0x0174 15069 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG3 0x0178 15070 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 0x0188 15071 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 0x018c 15072 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 0x0190 15073 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 0x0194 15074 #define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 15075 #define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3 0x0274 15076 #define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS 0x0278 15077 #define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 15078 #define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 15079 #define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 15080 #define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 15081 #define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 15082 #define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 15083 #define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 15084 #define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 15085 #define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 15086 #define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 15087 #define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 15088 #define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 15089 #define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 15090 #define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 15091 #define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 15092 #define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 15093 #define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 15094 #define cfgPSWUSCFG0_1_PCIE_ACS_CAP 0x02a4 15095 #define cfgPSWUSCFG0_1_PCIE_ACS_CNTL 0x02a6 15096 #define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST 0x02f0 15097 #define cfgPSWUSCFG0_1_PCIE_MC_CAP 0x02f4 15098 #define cfgPSWUSCFG0_1_PCIE_MC_CNTL 0x02f6 15099 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR0 0x02f8 15100 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR1 0x02fc 15101 #define cfgPSWUSCFG0_1_PCIE_MC_RCV0 0x0300 15102 #define cfgPSWUSCFG0_1_PCIE_MC_RCV1 0x0304 15103 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 0x0308 15104 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 0x030c 15105 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 15106 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 15107 #define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST 0x0320 15108 #define cfgPSWUSCFG0_1_PCIE_LTR_CAP 0x0324 15109 #define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 15110 #define cfgPSWUSCFG0_1_PCIE_ARI_CAP 0x032c 15111 #define cfgPSWUSCFG0_1_PCIE_ARI_CNTL 0x032e 15112 #define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST 0x0400 15113 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP 0x0404 15114 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS 0x0408 15115 #define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 15116 #define cfgPSWUSCFG0_1_LINK_CAP_16GT 0x0414 15117 #define cfgPSWUSCFG0_1_LINK_CNTL_16GT 0x0418 15118 #define cfgPSWUSCFG0_1_LINK_STATUS_16GT 0x041c 15119 #define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 15120 #define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 15121 #define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 15122 #define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 15123 #define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 15124 #define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 15125 #define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 15126 #define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 15127 #define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 15128 #define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 15129 #define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 15130 #define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 15131 #define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 15132 #define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 15133 #define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 15134 #define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 15135 #define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 15136 #define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 15137 #define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 15138 #define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST 0x0440 15139 #define cfgPSWUSCFG0_1_MARGINING_PORT_CAP 0x0444 15140 #define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS 0x0446 15141 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL 0x0448 15142 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS 0x044a 15143 #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL 0x044c 15144 #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS 0x044e 15145 #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL 0x0450 15146 #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS 0x0452 15147 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL 0x0454 15148 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS 0x0456 15149 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL 0x0458 15150 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS 0x045a 15151 #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL 0x045c 15152 #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS 0x045e 15153 #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL 0x0460 15154 #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS 0x0462 15155 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL 0x0464 15156 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS 0x0466 15157 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL 0x0468 15158 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS 0x046a 15159 #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL 0x046c 15160 #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS 0x046e 15161 #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL 0x0470 15162 #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS 0x0472 15163 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL 0x0474 15164 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS 0x0476 15165 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL 0x0478 15166 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS 0x047a 15167 #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL 0x047c 15168 #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS 0x047e 15169 #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL 0x0480 15170 #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS 0x0482 15171 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL 0x0484 15172 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS 0x0486 15173 #define cfgPSWUSCFG0_1_LINK_CAP_32GT 0x0504 15174 #define cfgPSWUSCFG0_1_LINK_CNTL_32GT 0x0508 15175 #define cfgPSWUSCFG0_1_LINK_STATUS_32GT 0x050c 15176 15177 15178 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp 15179 // base address: 0x0 15180 #define cfgBIF_CFG_DEV0_RC1_VENDOR_ID 0x0000 15181 #define cfgBIF_CFG_DEV0_RC1_DEVICE_ID 0x0002 15182 #define cfgBIF_CFG_DEV0_RC1_COMMAND 0x0004 15183 #define cfgBIF_CFG_DEV0_RC1_STATUS 0x0006 15184 #define cfgBIF_CFG_DEV0_RC1_REVISION_ID 0x0008 15185 #define cfgBIF_CFG_DEV0_RC1_PROG_INTERFACE 0x0009 15186 #define cfgBIF_CFG_DEV0_RC1_SUB_CLASS 0x000a 15187 #define cfgBIF_CFG_DEV0_RC1_BASE_CLASS 0x000b 15188 #define cfgBIF_CFG_DEV0_RC1_CACHE_LINE 0x000c 15189 #define cfgBIF_CFG_DEV0_RC1_LATENCY 0x000d 15190 #define cfgBIF_CFG_DEV0_RC1_HEADER 0x000e 15191 #define cfgBIF_CFG_DEV0_RC1_BIST 0x000f 15192 #define cfgBIF_CFG_DEV0_RC1_BASE_ADDR_1 0x0010 15193 #define cfgBIF_CFG_DEV0_RC1_BASE_ADDR_2 0x0014 15194 #define cfgBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY 0x0018 15195 #define cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT 0x001c 15196 #define cfgBIF_CFG_DEV0_RC1_SECONDARY_STATUS 0x001e 15197 #define cfgBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT 0x0020 15198 #define cfgBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT 0x0024 15199 #define cfgBIF_CFG_DEV0_RC1_PREF_BASE_UPPER 0x0028 15200 #define cfgBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER 0x002c 15201 #define cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI 0x0030 15202 #define cfgBIF_CFG_DEV0_RC1_CAP_PTR 0x0034 15203 #define cfgBIF_CFG_DEV0_RC1_ROM_BASE_ADDR 0x0038 15204 #define cfgBIF_CFG_DEV0_RC1_INTERRUPT_LINE 0x003c 15205 #define cfgBIF_CFG_DEV0_RC1_INTERRUPT_PIN 0x003d 15206 #define cfgBIF_CFG_DEV0_RC1_PMI_CAP_LIST 0x0050 15207 #define cfgBIF_CFG_DEV0_RC1_PMI_CAP 0x0052 15208 #define cfgBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL 0x0054 15209 #define cfgBIF_CFG_DEV0_RC1_PCIE_CAP_LIST 0x0058 15210 #define cfgBIF_CFG_DEV0_RC1_PCIE_CAP 0x005a 15211 #define cfgBIF_CFG_DEV0_RC1_DEVICE_CAP 0x005c 15212 #define cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL 0x0060 15213 #define cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS 0x0062 15214 #define cfgBIF_CFG_DEV0_RC1_LINK_CAP 0x0064 15215 #define cfgBIF_CFG_DEV0_RC1_LINK_CNTL 0x0068 15216 #define cfgBIF_CFG_DEV0_RC1_LINK_STATUS 0x006a 15217 #define cfgBIF_CFG_DEV0_RC1_SLOT_CAP 0x006c 15218 #define cfgBIF_CFG_DEV0_RC1_SLOT_CNTL 0x0070 15219 #define cfgBIF_CFG_DEV0_RC1_SLOT_STATUS 0x0072 15220 #define cfgBIF_CFG_DEV0_RC1_DEVICE_CAP2 0x007c 15221 #define cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL2 0x0080 15222 #define cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS2 0x0082 15223 #define cfgBIF_CFG_DEV0_RC1_LINK_CAP2 0x0084 15224 #define cfgBIF_CFG_DEV0_RC1_LINK_CNTL2 0x0088 15225 #define cfgBIF_CFG_DEV0_RC1_LINK_STATUS2 0x008a 15226 #define cfgBIF_CFG_DEV0_RC1_SLOT_CAP2 0x008c 15227 #define cfgBIF_CFG_DEV0_RC1_SLOT_CNTL2 0x0090 15228 #define cfgBIF_CFG_DEV0_RC1_SLOT_STATUS2 0x0092 15229 #define cfgBIF_CFG_DEV0_RC1_MSI_CAP_LIST 0x00a0 15230 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_CNTL 0x00a2 15231 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO 0x00a4 15232 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI 0x00a8 15233 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA 0x00a8 15234 #define cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA 0x00aa 15235 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 0x00ac 15236 #define cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64 0x00ae 15237 #define cfgBIF_CFG_DEV0_RC1_SSID_CAP_LIST 0x00c0 15238 #define cfgBIF_CFG_DEV0_RC1_SSID_CAP 0x00c4 15239 #define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15240 #define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15241 #define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 0x0108 15242 #define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 0x010c 15243 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST 0x0110 15244 #define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 0x0114 15245 #define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 0x0118 15246 #define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL 0x011c 15247 #define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS 0x011e 15248 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP 0x0120 15249 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL 0x0124 15250 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS 0x012a 15251 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP 0x012c 15252 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL 0x0130 15253 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS 0x0136 15254 #define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 15255 #define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 15256 #define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 15257 #define cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15258 #define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS 0x0154 15259 #define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK 0x0158 15260 #define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY 0x015c 15261 #define cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS 0x0160 15262 #define cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK 0x0164 15263 #define cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL 0x0168 15264 #define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 0x016c 15265 #define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 0x0170 15266 #define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 0x0174 15267 #define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 0x0178 15268 #define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 0x0188 15269 #define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 0x018c 15270 #define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 0x0190 15271 #define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 0x0194 15272 #define cfgBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 15273 #define cfgBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 0x0274 15274 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS 0x0278 15275 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 15276 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 15277 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 15278 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 15279 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 15280 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 15281 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 15282 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 15283 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 15284 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 15285 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 15286 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 15287 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 15288 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 15289 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 15290 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 15291 #define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST 0x02a0 15292 #define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CAP 0x02a4 15293 #define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL 0x02a6 15294 #define cfgBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST 0x0400 15295 #define cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP 0x0404 15296 #define cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS 0x0408 15297 #define cfgBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 15298 #define cfgBIF_CFG_DEV0_RC1_LINK_CAP_16GT 0x0414 15299 #define cfgBIF_CFG_DEV0_RC1_LINK_CNTL_16GT 0x0418 15300 #define cfgBIF_CFG_DEV0_RC1_LINK_STATUS_16GT 0x041c 15301 #define cfgBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 15302 #define cfgBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 15303 #define cfgBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 15304 #define cfgBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 15305 #define cfgBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 15306 #define cfgBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 15307 #define cfgBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 15308 #define cfgBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 15309 #define cfgBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 15310 #define cfgBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 15311 #define cfgBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 15312 #define cfgBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 15313 #define cfgBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 15314 #define cfgBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 15315 #define cfgBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 15316 #define cfgBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 15317 #define cfgBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 15318 #define cfgBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 15319 #define cfgBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 15320 #define cfgBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST 0x0450 15321 #define cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP 0x0454 15322 #define cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS 0x0456 15323 #define cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL 0x0458 15324 #define cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS 0x045a 15325 #define cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL 0x045c 15326 #define cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS 0x045e 15327 #define cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL 0x0460 15328 #define cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS 0x0462 15329 #define cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL 0x0464 15330 #define cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS 0x0466 15331 #define cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL 0x0468 15332 #define cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS 0x046a 15333 #define cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL 0x046c 15334 #define cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS 0x046e 15335 #define cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL 0x0470 15336 #define cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS 0x0472 15337 #define cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL 0x0474 15338 #define cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS 0x0476 15339 #define cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL 0x0478 15340 #define cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS 0x047a 15341 #define cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL 0x047c 15342 #define cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS 0x047e 15343 #define cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL 0x0480 15344 #define cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS 0x0482 15345 #define cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL 0x0484 15346 #define cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS 0x0486 15347 #define cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL 0x0488 15348 #define cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS 0x048a 15349 #define cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL 0x048c 15350 #define cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS 0x048e 15351 #define cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL 0x0490 15352 #define cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS 0x0492 15353 #define cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL 0x0494 15354 #define cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS 0x0496 15355 #define cfgBIF_CFG_DEV0_RC1_LINK_CAP_32GT 0x0504 15356 #define cfgBIF_CFG_DEV0_RC1_LINK_CNTL_32GT 0x0508 15357 #define cfgBIF_CFG_DEV0_RC1_LINK_STATUS_32GT 0x050c 15358 15359 15360 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 15361 // base address: 0x0 15362 #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID 0x0000 15363 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID 0x0002 15364 #define cfgBIF_CFG_DEV0_EPF0_1_COMMAND 0x0004 15365 #define cfgBIF_CFG_DEV0_EPF0_1_STATUS 0x0006 15366 #define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID 0x0008 15367 #define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE 0x0009 15368 #define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS 0x000a 15369 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS 0x000b 15370 #define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE 0x000c 15371 #define cfgBIF_CFG_DEV0_EPF0_1_LATENCY 0x000d 15372 #define cfgBIF_CFG_DEV0_EPF0_1_HEADER 0x000e 15373 #define cfgBIF_CFG_DEV0_EPF0_1_BIST 0x000f 15374 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 0x0010 15375 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 0x0014 15376 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 0x0018 15377 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 0x001c 15378 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 0x0020 15379 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 0x0024 15380 #define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR 0x0028 15381 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID 0x002c 15382 #define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR 0x0030 15383 #define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR 0x0034 15384 #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE 0x003c 15385 #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN 0x003d 15386 #define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT 0x003e 15387 #define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY 0x003f 15388 #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST 0x0048 15389 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W 0x004c 15390 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST 0x0050 15391 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP 0x0052 15392 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL 0x0054 15393 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST 0x0064 15394 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP 0x0066 15395 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP 0x0068 15396 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL 0x006c 15397 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS 0x006e 15398 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP 0x0070 15399 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL 0x0074 15400 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS 0x0076 15401 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 0x0088 15402 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 0x008c 15403 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 0x008e 15404 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2 0x0090 15405 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 0x0094 15406 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 0x0096 15407 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST 0x00a0 15408 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL 0x00a2 15409 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO 0x00a4 15410 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI 0x00a8 15411 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA 0x00a8 15412 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA 0x00aa 15413 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK 0x00ac 15414 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 0x00ac 15415 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64 0x00ae 15416 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 0x00b0 15417 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING 0x00b0 15418 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 0x00b4 15419 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST 0x00c0 15420 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL 0x00c2 15421 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE 0x00c4 15422 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA 0x00c8 15423 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15424 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15425 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 0x0108 15426 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 0x010c 15427 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST 0x0110 15428 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 0x0114 15429 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 0x0118 15430 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL 0x011c 15431 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS 0x011e 15432 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP 0x0120 15433 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0x0124 15434 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0x012a 15435 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP 0x012c 15436 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0x0130 15437 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0x0136 15438 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 15439 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 15440 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 15441 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15442 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS 0x0154 15443 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK 0x0158 15444 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 15445 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS 0x0160 15446 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK 0x0164 15447 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 15448 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 0x016c 15449 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 0x0170 15450 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 0x0174 15451 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 0x0178 15452 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 0x0188 15453 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 0x018c 15454 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 0x0190 15455 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 0x0194 15456 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0x0200 15457 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP 0x0204 15458 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL 0x0208 15459 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP 0x020c 15460 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL 0x0210 15461 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP 0x0214 15462 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL 0x0218 15463 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP 0x021c 15464 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL 0x0220 15465 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP 0x0224 15466 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL 0x0228 15467 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP 0x022c 15468 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL 0x0230 15469 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 15470 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 15471 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA 0x0248 15472 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP 0x024c 15473 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0x0250 15474 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP 0x0254 15475 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 15476 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS 0x025c 15477 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL 0x025e 15478 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 15479 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 15480 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 15481 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 15482 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 15483 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 15484 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 15485 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 15486 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 15487 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 0x0274 15488 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS 0x0278 15489 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 15490 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 15491 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 15492 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 15493 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 15494 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 15495 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 15496 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 15497 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 15498 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 15499 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 15500 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 15501 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 15502 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 15503 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 15504 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 15505 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 15506 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP 0x02a4 15507 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL 0x02a6 15508 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 15509 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP 0x02d4 15510 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL 0x02d6 15511 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST 0x02f0 15512 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP 0x02f4 15513 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL 0x02f6 15514 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 0x02f8 15515 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 0x02fc 15516 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 0x0300 15517 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 0x0304 15518 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 0x0308 15519 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 0x030c 15520 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 15521 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 15522 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0x0320 15523 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP 0x0324 15524 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 15525 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP 0x032c 15526 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL 0x032e 15527 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST 0x0330 15528 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP 0x0334 15529 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL 0x0338 15530 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS 0x033a 15531 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS 0x033c 15532 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS 0x033e 15533 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS 0x0340 15534 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 15535 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 15536 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE 0x0346 15537 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID 0x034a 15538 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 15539 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 15540 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 15541 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 15542 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 15543 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 15544 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 15545 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 15546 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 15547 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0x0400 15548 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP 0x0404 15549 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS 0x0408 15550 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 15551 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT 0x0414 15552 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT 0x0418 15553 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT 0x041c 15554 #define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 15555 #define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 15556 #define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 15557 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 15558 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 15559 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 15560 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 15561 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 15562 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 15563 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 15564 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 15565 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 15566 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 15567 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 15568 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 15569 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 15570 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 15571 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 15572 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 15573 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0x0450 15574 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP 0x0454 15575 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS 0x0456 15576 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0x0458 15577 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0x045a 15578 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0x045c 15579 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0x045e 15580 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0x0460 15581 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0x0462 15582 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0x0464 15583 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0x0466 15584 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0x0468 15585 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0x046a 15586 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0x046c 15587 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0x046e 15588 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0x0470 15589 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0x0472 15590 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0x0474 15591 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0x0476 15592 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0x0478 15593 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0x047a 15594 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0x047c 15595 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0x047e 15596 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0x0480 15597 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0x0482 15598 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0x0484 15599 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0x0486 15600 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0x0488 15601 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0x048a 15602 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0x048c 15603 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0x048e 15604 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0x0490 15605 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0x0492 15606 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0x0494 15607 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0x0496 15608 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 15609 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 15610 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 15611 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 15612 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 15613 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 15614 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 15615 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 15616 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 15617 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 15618 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 15619 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 15620 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 15621 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT 0x0504 15622 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT 0x0508 15623 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT 0x050c 15624 15625 15626 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 15627 // base address: 0x0 15628 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID 0x0000 15629 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID 0x0002 15630 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND 0x0004 15631 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS 0x0006 15632 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID 0x0008 15633 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE 0x0009 15634 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS 0x000a 15635 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS 0x000b 15636 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE 0x000c 15637 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY 0x000d 15638 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER 0x000e 15639 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST 0x000f 15640 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 0x0010 15641 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 0x0014 15642 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 0x0018 15643 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 0x001c 15644 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 0x0020 15645 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 0x0024 15646 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR 0x0028 15647 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID 0x002c 15648 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR 0x0030 15649 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR 0x0034 15650 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE 0x003c 15651 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN 0x003d 15652 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT 0x003e 15653 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY 0x003f 15654 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST 0x0064 15655 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP 0x0066 15656 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP 0x0068 15657 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL 0x006c 15658 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS 0x006e 15659 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP 0x0070 15660 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL 0x0074 15661 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS 0x0076 15662 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 0x0088 15663 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 0x008c 15664 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 0x008e 15665 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 0x0090 15666 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 0x0094 15667 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 0x0096 15668 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST 0x00a0 15669 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL 0x00a2 15670 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO 0x00a4 15671 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI 0x00a8 15672 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA 0x00a8 15673 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA 0x00aa 15674 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK 0x00ac 15675 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 0x00ac 15676 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64 0x00ae 15677 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 0x00b0 15678 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING 0x00b0 15679 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 0x00b4 15680 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST 0x00c0 15681 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL 0x00c2 15682 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE 0x00c4 15683 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA 0x00c8 15684 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15685 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15686 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 0x0108 15687 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 0x010c 15688 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15689 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS 0x0154 15690 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK 0x0158 15691 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 15692 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS 0x0160 15693 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK 0x0164 15694 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 15695 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 0x016c 15696 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 0x0170 15697 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 0x0174 15698 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 0x0178 15699 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 0x0188 15700 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 0x018c 15701 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 0x0190 15702 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 0x0194 15703 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 15704 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP 0x032c 15705 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL 0x032e 15706 15707 15708 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 15709 // base address: 0x0 15710 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID 0x0000 15711 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID 0x0002 15712 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND 0x0004 15713 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS 0x0006 15714 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID 0x0008 15715 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE 0x0009 15716 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS 0x000a 15717 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS 0x000b 15718 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE 0x000c 15719 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY 0x000d 15720 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER 0x000e 15721 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST 0x000f 15722 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 0x0010 15723 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 0x0014 15724 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 0x0018 15725 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 0x001c 15726 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 0x0020 15727 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 0x0024 15728 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR 0x0028 15729 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID 0x002c 15730 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR 0x0030 15731 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR 0x0034 15732 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE 0x003c 15733 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN 0x003d 15734 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT 0x003e 15735 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY 0x003f 15736 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST 0x0064 15737 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP 0x0066 15738 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP 0x0068 15739 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL 0x006c 15740 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS 0x006e 15741 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP 0x0070 15742 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL 0x0074 15743 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS 0x0076 15744 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 0x0088 15745 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 0x008c 15746 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 0x008e 15747 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 0x0090 15748 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 0x0094 15749 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 0x0096 15750 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST 0x00a0 15751 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL 0x00a2 15752 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO 0x00a4 15753 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI 0x00a8 15754 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA 0x00a8 15755 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA 0x00aa 15756 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK 0x00ac 15757 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 0x00ac 15758 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64 0x00ae 15759 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 0x00b0 15760 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING 0x00b0 15761 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 0x00b4 15762 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST 0x00c0 15763 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL 0x00c2 15764 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE 0x00c4 15765 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA 0x00c8 15766 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15767 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15768 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 0x0108 15769 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 0x010c 15770 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15771 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS 0x0154 15772 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK 0x0158 15773 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 15774 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS 0x0160 15775 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK 0x0164 15776 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 15777 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 0x016c 15778 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 0x0170 15779 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 0x0174 15780 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 0x0178 15781 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 0x0188 15782 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 0x018c 15783 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 0x0190 15784 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 0x0194 15785 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST 0x0328 15786 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP 0x032c 15787 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL 0x032e 15788 15789 15790 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 15791 // base address: 0x0 15792 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID 0x0000 15793 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID 0x0002 15794 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND 0x0004 15795 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS 0x0006 15796 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID 0x0008 15797 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE 0x0009 15798 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS 0x000a 15799 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS 0x000b 15800 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE 0x000c 15801 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY 0x000d 15802 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER 0x000e 15803 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST 0x000f 15804 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 0x0010 15805 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 0x0014 15806 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 0x0018 15807 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 0x001c 15808 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 0x0020 15809 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 0x0024 15810 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR 0x0028 15811 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID 0x002c 15812 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR 0x0030 15813 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR 0x0034 15814 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE 0x003c 15815 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN 0x003d 15816 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT 0x003e 15817 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY 0x003f 15818 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST 0x0064 15819 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP 0x0066 15820 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP 0x0068 15821 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL 0x006c 15822 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS 0x006e 15823 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP 0x0070 15824 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL 0x0074 15825 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS 0x0076 15826 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 0x0088 15827 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 0x008c 15828 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 0x008e 15829 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 0x0090 15830 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 0x0094 15831 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 0x0096 15832 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST 0x00a0 15833 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL 0x00a2 15834 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO 0x00a4 15835 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI 0x00a8 15836 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA 0x00a8 15837 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA 0x00aa 15838 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK 0x00ac 15839 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 0x00ac 15840 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64 0x00ae 15841 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 0x00b0 15842 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING 0x00b0 15843 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 0x00b4 15844 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST 0x00c0 15845 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL 0x00c2 15846 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE 0x00c4 15847 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA 0x00c8 15848 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15849 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15850 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 0x0108 15851 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 0x010c 15852 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15853 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS 0x0154 15854 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK 0x0158 15855 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 15856 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS 0x0160 15857 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK 0x0164 15858 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 15859 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 0x016c 15860 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 0x0170 15861 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 0x0174 15862 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 0x0178 15863 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 0x0188 15864 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 0x018c 15865 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 0x0190 15866 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 0x0194 15867 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST 0x0328 15868 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP 0x032c 15869 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL 0x032e 15870 15871 15872 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 15873 // base address: 0x0 15874 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID 0x0000 15875 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID 0x0002 15876 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND 0x0004 15877 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS 0x0006 15878 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID 0x0008 15879 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE 0x0009 15880 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS 0x000a 15881 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS 0x000b 15882 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE 0x000c 15883 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY 0x000d 15884 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER 0x000e 15885 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST 0x000f 15886 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 0x0010 15887 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 0x0014 15888 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 0x0018 15889 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 0x001c 15890 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 0x0020 15891 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 0x0024 15892 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR 0x0028 15893 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID 0x002c 15894 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR 0x0030 15895 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR 0x0034 15896 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE 0x003c 15897 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN 0x003d 15898 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT 0x003e 15899 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY 0x003f 15900 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST 0x0064 15901 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP 0x0066 15902 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP 0x0068 15903 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL 0x006c 15904 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS 0x006e 15905 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP 0x0070 15906 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL 0x0074 15907 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS 0x0076 15908 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 0x0088 15909 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 0x008c 15910 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 0x008e 15911 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 0x0090 15912 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 0x0094 15913 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 0x0096 15914 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST 0x00a0 15915 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL 0x00a2 15916 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO 0x00a4 15917 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI 0x00a8 15918 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA 0x00a8 15919 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA 0x00aa 15920 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK 0x00ac 15921 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 0x00ac 15922 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64 0x00ae 15923 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 0x00b0 15924 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING 0x00b0 15925 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 0x00b4 15926 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST 0x00c0 15927 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL 0x00c2 15928 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE 0x00c4 15929 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA 0x00c8 15930 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15931 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15932 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 0x0108 15933 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 0x010c 15934 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15935 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS 0x0154 15936 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK 0x0158 15937 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 15938 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS 0x0160 15939 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK 0x0164 15940 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 15941 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 0x016c 15942 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 0x0170 15943 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 0x0174 15944 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 0x0178 15945 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 0x0188 15946 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 0x018c 15947 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 0x0190 15948 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 0x0194 15949 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST 0x0328 15950 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP 0x032c 15951 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL 0x032e 15952 15953 15954 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 15955 // base address: 0x0 15956 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID 0x0000 15957 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID 0x0002 15958 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND 0x0004 15959 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS 0x0006 15960 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID 0x0008 15961 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE 0x0009 15962 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS 0x000a 15963 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS 0x000b 15964 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE 0x000c 15965 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY 0x000d 15966 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER 0x000e 15967 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST 0x000f 15968 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 0x0010 15969 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 0x0014 15970 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 0x0018 15971 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 0x001c 15972 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 0x0020 15973 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 0x0024 15974 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR 0x0028 15975 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID 0x002c 15976 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR 0x0030 15977 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR 0x0034 15978 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE 0x003c 15979 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN 0x003d 15980 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT 0x003e 15981 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY 0x003f 15982 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST 0x0064 15983 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP 0x0066 15984 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP 0x0068 15985 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL 0x006c 15986 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS 0x006e 15987 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP 0x0070 15988 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL 0x0074 15989 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS 0x0076 15990 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 0x0088 15991 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 0x008c 15992 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 0x008e 15993 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 0x0090 15994 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 0x0094 15995 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 0x0096 15996 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST 0x00a0 15997 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL 0x00a2 15998 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO 0x00a4 15999 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI 0x00a8 16000 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA 0x00a8 16001 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA 0x00aa 16002 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK 0x00ac 16003 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 0x00ac 16004 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64 0x00ae 16005 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 0x00b0 16006 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING 0x00b0 16007 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 0x00b4 16008 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST 0x00c0 16009 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL 0x00c2 16010 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE 0x00c4 16011 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA 0x00c8 16012 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16013 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16014 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 0x0108 16015 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 0x010c 16016 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16017 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS 0x0154 16018 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK 0x0158 16019 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16020 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS 0x0160 16021 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK 0x0164 16022 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16023 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 0x016c 16024 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 0x0170 16025 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 0x0174 16026 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 0x0178 16027 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 0x0188 16028 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 0x018c 16029 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 0x0190 16030 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 0x0194 16031 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16032 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP 0x032c 16033 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL 0x032e 16034 16035 16036 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 16037 // base address: 0x0 16038 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID 0x0000 16039 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID 0x0002 16040 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND 0x0004 16041 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS 0x0006 16042 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID 0x0008 16043 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE 0x0009 16044 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS 0x000a 16045 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS 0x000b 16046 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE 0x000c 16047 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY 0x000d 16048 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER 0x000e 16049 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST 0x000f 16050 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 0x0010 16051 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 0x0014 16052 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 0x0018 16053 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 0x001c 16054 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 0x0020 16055 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 0x0024 16056 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR 0x0028 16057 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID 0x002c 16058 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR 0x0030 16059 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR 0x0034 16060 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE 0x003c 16061 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN 0x003d 16062 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT 0x003e 16063 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY 0x003f 16064 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST 0x0064 16065 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP 0x0066 16066 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP 0x0068 16067 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL 0x006c 16068 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS 0x006e 16069 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP 0x0070 16070 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL 0x0074 16071 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS 0x0076 16072 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 0x0088 16073 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 0x008c 16074 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 0x008e 16075 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 0x0090 16076 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 0x0094 16077 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 0x0096 16078 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST 0x00a0 16079 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL 0x00a2 16080 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO 0x00a4 16081 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI 0x00a8 16082 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA 0x00a8 16083 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA 0x00aa 16084 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK 0x00ac 16085 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 0x00ac 16086 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64 0x00ae 16087 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 0x00b0 16088 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING 0x00b0 16089 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 0x00b4 16090 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST 0x00c0 16091 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL 0x00c2 16092 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE 0x00c4 16093 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA 0x00c8 16094 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16095 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16096 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 0x0108 16097 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 0x010c 16098 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16099 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS 0x0154 16100 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK 0x0158 16101 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16102 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS 0x0160 16103 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK 0x0164 16104 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16105 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 0x016c 16106 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 0x0170 16107 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 0x0174 16108 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 0x0178 16109 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 0x0188 16110 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 0x018c 16111 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 0x0190 16112 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 0x0194 16113 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16114 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP 0x032c 16115 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL 0x032e 16116 16117 16118 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 16119 // base address: 0x0 16120 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID 0x0000 16121 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID 0x0002 16122 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND 0x0004 16123 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS 0x0006 16124 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID 0x0008 16125 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE 0x0009 16126 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS 0x000a 16127 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS 0x000b 16128 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE 0x000c 16129 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY 0x000d 16130 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER 0x000e 16131 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST 0x000f 16132 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 0x0010 16133 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 0x0014 16134 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 0x0018 16135 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 0x001c 16136 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 0x0020 16137 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 0x0024 16138 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR 0x0028 16139 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID 0x002c 16140 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR 0x0030 16141 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR 0x0034 16142 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE 0x003c 16143 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN 0x003d 16144 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT 0x003e 16145 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY 0x003f 16146 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST 0x0064 16147 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP 0x0066 16148 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP 0x0068 16149 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL 0x006c 16150 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS 0x006e 16151 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP 0x0070 16152 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL 0x0074 16153 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS 0x0076 16154 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 0x0088 16155 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 0x008c 16156 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 0x008e 16157 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 0x0090 16158 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 0x0094 16159 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 0x0096 16160 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST 0x00a0 16161 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL 0x00a2 16162 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO 0x00a4 16163 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI 0x00a8 16164 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA 0x00a8 16165 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA 0x00aa 16166 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK 0x00ac 16167 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 0x00ac 16168 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64 0x00ae 16169 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 0x00b0 16170 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING 0x00b0 16171 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 0x00b4 16172 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST 0x00c0 16173 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL 0x00c2 16174 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE 0x00c4 16175 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA 0x00c8 16176 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16177 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16178 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 0x0108 16179 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 0x010c 16180 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16181 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS 0x0154 16182 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK 0x0158 16183 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16184 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS 0x0160 16185 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK 0x0164 16186 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16187 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 0x016c 16188 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 0x0170 16189 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 0x0174 16190 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 0x0178 16191 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 0x0188 16192 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 0x018c 16193 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 0x0190 16194 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 0x0194 16195 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16196 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP 0x032c 16197 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL 0x032e 16198 16199 16200 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 16201 // base address: 0x0 16202 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID 0x0000 16203 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID 0x0002 16204 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND 0x0004 16205 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS 0x0006 16206 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID 0x0008 16207 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE 0x0009 16208 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS 0x000a 16209 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS 0x000b 16210 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE 0x000c 16211 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY 0x000d 16212 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER 0x000e 16213 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST 0x000f 16214 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 0x0010 16215 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 0x0014 16216 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 0x0018 16217 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 0x001c 16218 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 0x0020 16219 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 0x0024 16220 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR 0x0028 16221 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID 0x002c 16222 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR 0x0030 16223 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR 0x0034 16224 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE 0x003c 16225 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN 0x003d 16226 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT 0x003e 16227 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY 0x003f 16228 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST 0x0064 16229 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP 0x0066 16230 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP 0x0068 16231 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL 0x006c 16232 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS 0x006e 16233 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP 0x0070 16234 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL 0x0074 16235 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS 0x0076 16236 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 0x0088 16237 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 0x008c 16238 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 0x008e 16239 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 0x0090 16240 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 0x0094 16241 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 0x0096 16242 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST 0x00a0 16243 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL 0x00a2 16244 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO 0x00a4 16245 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI 0x00a8 16246 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA 0x00a8 16247 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA 0x00aa 16248 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK 0x00ac 16249 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 0x00ac 16250 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64 0x00ae 16251 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 0x00b0 16252 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING 0x00b0 16253 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 0x00b4 16254 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST 0x00c0 16255 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL 0x00c2 16256 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE 0x00c4 16257 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA 0x00c8 16258 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16259 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16260 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 0x0108 16261 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 0x010c 16262 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16263 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS 0x0154 16264 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK 0x0158 16265 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16266 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS 0x0160 16267 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK 0x0164 16268 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16269 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 0x016c 16270 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 0x0170 16271 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 0x0174 16272 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 0x0178 16273 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 0x0188 16274 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 0x018c 16275 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 0x0190 16276 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 0x0194 16277 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16278 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP 0x032c 16279 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL 0x032e 16280 16281 16282 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 16283 // base address: 0x0 16284 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID 0x0000 16285 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID 0x0002 16286 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND 0x0004 16287 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS 0x0006 16288 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID 0x0008 16289 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE 0x0009 16290 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS 0x000a 16291 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS 0x000b 16292 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE 0x000c 16293 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY 0x000d 16294 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER 0x000e 16295 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST 0x000f 16296 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 0x0010 16297 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 0x0014 16298 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 0x0018 16299 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 0x001c 16300 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 0x0020 16301 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 0x0024 16302 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR 0x0028 16303 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID 0x002c 16304 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR 0x0030 16305 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR 0x0034 16306 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE 0x003c 16307 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN 0x003d 16308 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT 0x003e 16309 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY 0x003f 16310 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST 0x0064 16311 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP 0x0066 16312 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP 0x0068 16313 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL 0x006c 16314 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS 0x006e 16315 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP 0x0070 16316 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL 0x0074 16317 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS 0x0076 16318 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 0x0088 16319 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 0x008c 16320 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 0x008e 16321 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 0x0090 16322 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 0x0094 16323 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 0x0096 16324 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST 0x00a0 16325 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL 0x00a2 16326 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO 0x00a4 16327 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI 0x00a8 16328 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA 0x00a8 16329 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA 0x00aa 16330 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK 0x00ac 16331 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 0x00ac 16332 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64 0x00ae 16333 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 0x00b0 16334 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING 0x00b0 16335 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 0x00b4 16336 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST 0x00c0 16337 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL 0x00c2 16338 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE 0x00c4 16339 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA 0x00c8 16340 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16341 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16342 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 0x0108 16343 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 0x010c 16344 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16345 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS 0x0154 16346 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK 0x0158 16347 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16348 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS 0x0160 16349 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK 0x0164 16350 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16351 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 0x016c 16352 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 0x0170 16353 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 0x0174 16354 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 0x0178 16355 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 0x0188 16356 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 0x018c 16357 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 0x0190 16358 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 0x0194 16359 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16360 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP 0x032c 16361 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL 0x032e 16362 16363 16364 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 16365 // base address: 0x0 16366 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID 0x0000 16367 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID 0x0002 16368 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND 0x0004 16369 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS 0x0006 16370 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID 0x0008 16371 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE 0x0009 16372 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS 0x000a 16373 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS 0x000b 16374 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE 0x000c 16375 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY 0x000d 16376 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER 0x000e 16377 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST 0x000f 16378 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 0x0010 16379 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 0x0014 16380 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 0x0018 16381 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 0x001c 16382 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 0x0020 16383 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 0x0024 16384 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR 0x0028 16385 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID 0x002c 16386 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR 0x0030 16387 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR 0x0034 16388 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE 0x003c 16389 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN 0x003d 16390 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT 0x003e 16391 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY 0x003f 16392 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST 0x0064 16393 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP 0x0066 16394 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP 0x0068 16395 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL 0x006c 16396 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS 0x006e 16397 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP 0x0070 16398 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL 0x0074 16399 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS 0x0076 16400 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 0x0088 16401 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 0x008c 16402 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 0x008e 16403 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 0x0090 16404 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 0x0094 16405 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 0x0096 16406 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST 0x00a0 16407 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL 0x00a2 16408 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO 0x00a4 16409 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI 0x00a8 16410 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA 0x00a8 16411 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA 0x00aa 16412 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK 0x00ac 16413 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 0x00ac 16414 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64 0x00ae 16415 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 0x00b0 16416 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING 0x00b0 16417 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 0x00b4 16418 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST 0x00c0 16419 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL 0x00c2 16420 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE 0x00c4 16421 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA 0x00c8 16422 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16423 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16424 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 0x0108 16425 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 0x010c 16426 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16427 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS 0x0154 16428 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK 0x0158 16429 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16430 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS 0x0160 16431 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK 0x0164 16432 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16433 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 0x016c 16434 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 0x0170 16435 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 0x0174 16436 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 0x0178 16437 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 0x0188 16438 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 0x018c 16439 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 0x0190 16440 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 0x0194 16441 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16442 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP 0x032c 16443 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL 0x032e 16444 16445 16446 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 16447 // base address: 0x0 16448 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID 0x0000 16449 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID 0x0002 16450 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND 0x0004 16451 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS 0x0006 16452 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID 0x0008 16453 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE 0x0009 16454 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS 0x000a 16455 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS 0x000b 16456 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE 0x000c 16457 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY 0x000d 16458 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER 0x000e 16459 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST 0x000f 16460 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 0x0010 16461 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 0x0014 16462 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 0x0018 16463 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 0x001c 16464 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 0x0020 16465 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 0x0024 16466 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR 0x0028 16467 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID 0x002c 16468 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR 0x0030 16469 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR 0x0034 16470 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE 0x003c 16471 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN 0x003d 16472 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT 0x003e 16473 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY 0x003f 16474 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST 0x0064 16475 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP 0x0066 16476 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP 0x0068 16477 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL 0x006c 16478 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS 0x006e 16479 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP 0x0070 16480 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL 0x0074 16481 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS 0x0076 16482 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 0x0088 16483 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 0x008c 16484 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 0x008e 16485 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 0x0090 16486 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 0x0094 16487 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 0x0096 16488 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST 0x00a0 16489 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL 0x00a2 16490 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO 0x00a4 16491 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI 0x00a8 16492 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA 0x00a8 16493 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA 0x00aa 16494 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK 0x00ac 16495 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 0x00ac 16496 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64 0x00ae 16497 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 0x00b0 16498 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING 0x00b0 16499 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 0x00b4 16500 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST 0x00c0 16501 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL 0x00c2 16502 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE 0x00c4 16503 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA 0x00c8 16504 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16505 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16506 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 0x0108 16507 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 0x010c 16508 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16509 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS 0x0154 16510 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK 0x0158 16511 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16512 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS 0x0160 16513 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK 0x0164 16514 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16515 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 0x016c 16516 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 0x0170 16517 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 0x0174 16518 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 0x0178 16519 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 0x0188 16520 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 0x018c 16521 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 0x0190 16522 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 0x0194 16523 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16524 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP 0x032c 16525 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL 0x032e 16526 16527 16528 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 16529 // base address: 0x0 16530 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID 0x0000 16531 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID 0x0002 16532 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND 0x0004 16533 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS 0x0006 16534 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID 0x0008 16535 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE 0x0009 16536 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS 0x000a 16537 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS 0x000b 16538 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE 0x000c 16539 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY 0x000d 16540 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER 0x000e 16541 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST 0x000f 16542 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 0x0010 16543 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 0x0014 16544 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 0x0018 16545 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 0x001c 16546 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 0x0020 16547 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 0x0024 16548 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR 0x0028 16549 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID 0x002c 16550 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR 0x0030 16551 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR 0x0034 16552 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE 0x003c 16553 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN 0x003d 16554 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT 0x003e 16555 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY 0x003f 16556 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST 0x0064 16557 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP 0x0066 16558 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP 0x0068 16559 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL 0x006c 16560 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS 0x006e 16561 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP 0x0070 16562 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL 0x0074 16563 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS 0x0076 16564 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 0x0088 16565 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 0x008c 16566 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 0x008e 16567 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 0x0090 16568 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 0x0094 16569 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 0x0096 16570 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST 0x00a0 16571 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL 0x00a2 16572 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO 0x00a4 16573 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI 0x00a8 16574 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA 0x00a8 16575 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA 0x00aa 16576 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK 0x00ac 16577 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 0x00ac 16578 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64 0x00ae 16579 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 0x00b0 16580 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING 0x00b0 16581 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 0x00b4 16582 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST 0x00c0 16583 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL 0x00c2 16584 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE 0x00c4 16585 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA 0x00c8 16586 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16587 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16588 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 0x0108 16589 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 0x010c 16590 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16591 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS 0x0154 16592 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK 0x0158 16593 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16594 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS 0x0160 16595 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK 0x0164 16596 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16597 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 0x016c 16598 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 0x0170 16599 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 0x0174 16600 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 0x0178 16601 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 0x0188 16602 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 0x018c 16603 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 0x0190 16604 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 0x0194 16605 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16606 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP 0x032c 16607 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL 0x032e 16608 16609 16610 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 16611 // base address: 0x0 16612 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID 0x0000 16613 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID 0x0002 16614 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND 0x0004 16615 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS 0x0006 16616 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID 0x0008 16617 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE 0x0009 16618 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS 0x000a 16619 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS 0x000b 16620 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE 0x000c 16621 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY 0x000d 16622 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER 0x000e 16623 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST 0x000f 16624 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 0x0010 16625 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 0x0014 16626 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 0x0018 16627 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 0x001c 16628 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 0x0020 16629 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 0x0024 16630 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR 0x0028 16631 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID 0x002c 16632 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR 0x0030 16633 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR 0x0034 16634 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE 0x003c 16635 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN 0x003d 16636 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT 0x003e 16637 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY 0x003f 16638 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST 0x0064 16639 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP 0x0066 16640 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP 0x0068 16641 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL 0x006c 16642 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS 0x006e 16643 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP 0x0070 16644 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL 0x0074 16645 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS 0x0076 16646 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 0x0088 16647 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 0x008c 16648 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 0x008e 16649 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 0x0090 16650 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 0x0094 16651 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 0x0096 16652 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST 0x00a0 16653 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL 0x00a2 16654 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO 0x00a4 16655 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI 0x00a8 16656 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA 0x00a8 16657 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA 0x00aa 16658 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK 0x00ac 16659 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 0x00ac 16660 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64 0x00ae 16661 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 0x00b0 16662 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING 0x00b0 16663 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 0x00b4 16664 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST 0x00c0 16665 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL 0x00c2 16666 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE 0x00c4 16667 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA 0x00c8 16668 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16669 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16670 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 0x0108 16671 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 0x010c 16672 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16673 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS 0x0154 16674 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK 0x0158 16675 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16676 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS 0x0160 16677 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK 0x0164 16678 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16679 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 0x016c 16680 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 0x0170 16681 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 0x0174 16682 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 0x0178 16683 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 0x0188 16684 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 0x018c 16685 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 0x0190 16686 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 0x0194 16687 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16688 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP 0x032c 16689 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL 0x032e 16690 16691 16692 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 16693 // base address: 0x0 16694 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID 0x0000 16695 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID 0x0002 16696 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND 0x0004 16697 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS 0x0006 16698 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID 0x0008 16699 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE 0x0009 16700 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS 0x000a 16701 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS 0x000b 16702 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE 0x000c 16703 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY 0x000d 16704 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER 0x000e 16705 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST 0x000f 16706 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 0x0010 16707 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 0x0014 16708 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 0x0018 16709 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 0x001c 16710 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 0x0020 16711 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 0x0024 16712 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR 0x0028 16713 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID 0x002c 16714 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR 0x0030 16715 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR 0x0034 16716 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE 0x003c 16717 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN 0x003d 16718 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT 0x003e 16719 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY 0x003f 16720 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST 0x0064 16721 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP 0x0066 16722 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP 0x0068 16723 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL 0x006c 16724 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS 0x006e 16725 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP 0x0070 16726 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL 0x0074 16727 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS 0x0076 16728 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 0x0088 16729 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 0x008c 16730 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 0x008e 16731 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 0x0090 16732 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 0x0094 16733 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 0x0096 16734 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST 0x00a0 16735 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL 0x00a2 16736 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO 0x00a4 16737 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI 0x00a8 16738 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA 0x00a8 16739 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA 0x00aa 16740 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK 0x00ac 16741 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 0x00ac 16742 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64 0x00ae 16743 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 0x00b0 16744 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING 0x00b0 16745 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 0x00b4 16746 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST 0x00c0 16747 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL 0x00c2 16748 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE 0x00c4 16749 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA 0x00c8 16750 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16751 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16752 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 0x0108 16753 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 0x010c 16754 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16755 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS 0x0154 16756 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK 0x0158 16757 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16758 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS 0x0160 16759 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK 0x0164 16760 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16761 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 0x016c 16762 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 0x0170 16763 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 0x0174 16764 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 0x0178 16765 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 0x0188 16766 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 0x018c 16767 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 0x0190 16768 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 0x0194 16769 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16770 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP 0x032c 16771 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL 0x032e 16772 16773 16774 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 16775 // base address: 0x0 16776 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID 0x0000 16777 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID 0x0002 16778 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND 0x0004 16779 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS 0x0006 16780 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID 0x0008 16781 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE 0x0009 16782 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS 0x000a 16783 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS 0x000b 16784 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE 0x000c 16785 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY 0x000d 16786 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER 0x000e 16787 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST 0x000f 16788 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 0x0010 16789 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 0x0014 16790 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 0x0018 16791 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 0x001c 16792 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 0x0020 16793 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 0x0024 16794 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR 0x0028 16795 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID 0x002c 16796 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR 0x0030 16797 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR 0x0034 16798 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE 0x003c 16799 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN 0x003d 16800 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT 0x003e 16801 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY 0x003f 16802 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST 0x0064 16803 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP 0x0066 16804 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP 0x0068 16805 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL 0x006c 16806 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS 0x006e 16807 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP 0x0070 16808 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL 0x0074 16809 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS 0x0076 16810 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 0x0088 16811 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 0x008c 16812 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 0x008e 16813 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 0x0090 16814 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 0x0094 16815 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 0x0096 16816 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST 0x00a0 16817 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL 0x00a2 16818 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO 0x00a4 16819 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI 0x00a8 16820 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA 0x00a8 16821 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA 0x00aa 16822 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK 0x00ac 16823 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 0x00ac 16824 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64 0x00ae 16825 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 0x00b0 16826 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING 0x00b0 16827 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 0x00b4 16828 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST 0x00c0 16829 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL 0x00c2 16830 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE 0x00c4 16831 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA 0x00c8 16832 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16833 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16834 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 0x0108 16835 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 0x010c 16836 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16837 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS 0x0154 16838 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK 0x0158 16839 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16840 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS 0x0160 16841 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK 0x0164 16842 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16843 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 0x016c 16844 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 0x0170 16845 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 0x0174 16846 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 0x0178 16847 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 0x0188 16848 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 0x018c 16849 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 0x0190 16850 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 0x0194 16851 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16852 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP 0x032c 16853 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL 0x032e 16854 16855 16856 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 16857 // base address: 0x0 16858 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID 0x0000 16859 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID 0x0002 16860 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND 0x0004 16861 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS 0x0006 16862 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID 0x0008 16863 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE 0x0009 16864 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS 0x000a 16865 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS 0x000b 16866 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE 0x000c 16867 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY 0x000d 16868 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER 0x000e 16869 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST 0x000f 16870 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 0x0010 16871 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 0x0014 16872 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 0x0018 16873 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 0x001c 16874 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 0x0020 16875 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 0x0024 16876 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR 0x0028 16877 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID 0x002c 16878 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR 0x0030 16879 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR 0x0034 16880 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE 0x003c 16881 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN 0x003d 16882 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT 0x003e 16883 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY 0x003f 16884 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST 0x0064 16885 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP 0x0066 16886 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP 0x0068 16887 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL 0x006c 16888 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS 0x006e 16889 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP 0x0070 16890 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL 0x0074 16891 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS 0x0076 16892 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 0x0088 16893 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 0x008c 16894 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 0x008e 16895 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 0x0090 16896 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 0x0094 16897 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 0x0096 16898 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST 0x00a0 16899 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL 0x00a2 16900 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO 0x00a4 16901 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI 0x00a8 16902 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA 0x00a8 16903 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA 0x00aa 16904 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK 0x00ac 16905 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 0x00ac 16906 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64 0x00ae 16907 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 0x00b0 16908 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING 0x00b0 16909 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 0x00b4 16910 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST 0x00c0 16911 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL 0x00c2 16912 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE 0x00c4 16913 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA 0x00c8 16914 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16915 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16916 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 0x0108 16917 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 0x010c 16918 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16919 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS 0x0154 16920 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK 0x0158 16921 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 16922 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS 0x0160 16923 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK 0x0164 16924 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 16925 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 0x016c 16926 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 0x0170 16927 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 0x0174 16928 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 0x0178 16929 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 0x0188 16930 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 0x018c 16931 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 0x0190 16932 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 0x0194 16933 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST 0x0328 16934 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP 0x032c 16935 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL 0x032e 16936 16937 16938 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 16939 // base address: 0x0 16940 #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID 0x0000 16941 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID 0x0002 16942 #define cfgBIF_CFG_DEV0_EPF1_1_COMMAND 0x0004 16943 #define cfgBIF_CFG_DEV0_EPF1_1_STATUS 0x0006 16944 #define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID 0x0008 16945 #define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE 0x0009 16946 #define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS 0x000a 16947 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS 0x000b 16948 #define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE 0x000c 16949 #define cfgBIF_CFG_DEV0_EPF1_1_LATENCY 0x000d 16950 #define cfgBIF_CFG_DEV0_EPF1_1_HEADER 0x000e 16951 #define cfgBIF_CFG_DEV0_EPF1_1_BIST 0x000f 16952 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 0x0010 16953 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 0x0014 16954 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 0x0018 16955 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 0x001c 16956 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 0x0020 16957 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 0x0024 16958 #define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR 0x0028 16959 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID 0x002c 16960 #define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR 0x0030 16961 #define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR 0x0034 16962 #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE 0x003c 16963 #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN 0x003d 16964 #define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT 0x003e 16965 #define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY 0x003f 16966 #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST 0x0048 16967 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W 0x004c 16968 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST 0x0050 16969 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP 0x0052 16970 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL 0x0054 16971 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST 0x0064 16972 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP 0x0066 16973 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP 0x0068 16974 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL 0x006c 16975 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS 0x006e 16976 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP 0x0070 16977 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL 0x0074 16978 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS 0x0076 16979 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 0x0088 16980 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 0x008c 16981 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 0x008e 16982 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2 0x0090 16983 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 0x0094 16984 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 0x0096 16985 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST 0x00a0 16986 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL 0x00a2 16987 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO 0x00a4 16988 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI 0x00a8 16989 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA 0x00a8 16990 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA 0x00aa 16991 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK 0x00ac 16992 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 0x00ac 16993 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64 0x00ae 16994 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 0x00b0 16995 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING 0x00b0 16996 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 0x00b4 16997 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST 0x00c0 16998 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL 0x00c2 16999 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE 0x00c4 17000 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA 0x00c8 17001 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 17002 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 17003 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 0x0108 17004 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 0x010c 17005 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 17006 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 17007 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 17008 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 17009 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS 0x0154 17010 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK 0x0158 17011 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 17012 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS 0x0160 17013 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK 0x0164 17014 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 17015 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 0x016c 17016 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 0x0170 17017 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 0x0174 17018 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 0x0178 17019 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 0x0188 17020 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 0x018c 17021 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 0x0190 17022 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 0x0194 17023 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0x0200 17024 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP 0x0204 17025 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL 0x0208 17026 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP 0x020c 17027 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL 0x0210 17028 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP 0x0214 17029 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL 0x0218 17030 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP 0x021c 17031 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL 0x0220 17032 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP 0x0224 17033 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL 0x0228 17034 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP 0x022c 17035 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL 0x0230 17036 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 17037 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 17038 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA 0x0248 17039 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP 0x024c 17040 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0x0250 17041 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP 0x0254 17042 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 17043 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS 0x025c 17044 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL 0x025e 17045 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 17046 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 17047 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 17048 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 17049 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 17050 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 17051 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 17052 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 17053 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 17054 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 0x0274 17055 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS 0x0278 17056 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 17057 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 17058 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 17059 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 17060 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 17061 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 17062 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 17063 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 17064 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 17065 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 17066 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 17067 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 17068 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 17069 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 17070 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 17071 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 17072 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 17073 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP 0x02a4 17074 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL 0x02a6 17075 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 17076 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP 0x02d4 17077 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL 0x02d6 17078 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST 0x02f0 17079 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP 0x02f4 17080 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL 0x02f6 17081 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 0x02f8 17082 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 0x02fc 17083 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 0x0300 17084 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 0x0304 17085 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 0x0308 17086 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 0x030c 17087 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 17088 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 17089 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST 0x0320 17090 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP 0x0324 17091 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0x0328 17092 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP 0x032c 17093 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL 0x032e 17094 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST 0x0330 17095 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP 0x0334 17096 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL 0x0338 17097 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS 0x033a 17098 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS 0x033c 17099 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS 0x033e 17100 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS 0x0340 17101 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 17102 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 17103 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE 0x0346 17104 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID 0x034a 17105 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 17106 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 17107 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 17108 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 17109 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 17110 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 17111 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 17112 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 17113 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 17114 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 17115 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 17116 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 17117 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 17118 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 17119 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 17120 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 17121 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 17122 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 17123 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 17124 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 17125 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 17126 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 17127 17128 17129 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp 17130 // base address: 0x0 17131 #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID 0x0000 17132 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID 0x0002 17133 #define cfgBIF_CFG_DEV0_EPF2_1_COMMAND 0x0004 17134 #define cfgBIF_CFG_DEV0_EPF2_1_STATUS 0x0006 17135 #define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID 0x0008 17136 #define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE 0x0009 17137 #define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS 0x000a 17138 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS 0x000b 17139 #define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE 0x000c 17140 #define cfgBIF_CFG_DEV0_EPF2_1_LATENCY 0x000d 17141 #define cfgBIF_CFG_DEV0_EPF2_1_HEADER 0x000e 17142 #define cfgBIF_CFG_DEV0_EPF2_1_BIST 0x000f 17143 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 0x0010 17144 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 0x0014 17145 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 0x0018 17146 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 0x001c 17147 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 0x0020 17148 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 0x0024 17149 #define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR 0x0028 17150 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID 0x002c 17151 #define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR 0x0030 17152 #define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR 0x0034 17153 #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE 0x003c 17154 #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN 0x003d 17155 #define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT 0x003e 17156 #define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY 0x003f 17157 #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST 0x0048 17158 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W 0x004c 17159 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST 0x0050 17160 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP 0x0052 17161 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL 0x0054 17162 #define cfgBIF_CFG_DEV0_EPF2_1_SBRN 0x0060 17163 #define cfgBIF_CFG_DEV0_EPF2_1_FLADJ 0x0061 17164 #define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD 0x0062 17165 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST 0x0064 17166 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP 0x0066 17167 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP 0x0068 17168 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL 0x006c 17169 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS 0x006e 17170 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP 0x0070 17171 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL 0x0074 17172 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS 0x0076 17173 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 0x0088 17174 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 0x008c 17175 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 0x008e 17176 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2 0x0090 17177 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 0x0094 17178 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 0x0096 17179 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST 0x00a0 17180 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL 0x00a2 17181 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO 0x00a4 17182 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI 0x00a8 17183 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA 0x00a8 17184 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA 0x00aa 17185 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK 0x00ac 17186 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 0x00ac 17187 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64 0x00ae 17188 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 0x00b0 17189 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING 0x00b0 17190 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 0x00b4 17191 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST 0x00c0 17192 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL 0x00c2 17193 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE 0x00c4 17194 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA 0x00c8 17195 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 17196 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 17197 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 0x0108 17198 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 0x010c 17199 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 17200 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS 0x0154 17201 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK 0x0158 17202 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 17203 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS 0x0160 17204 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK 0x0164 17205 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 17206 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 0x016c 17207 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 0x0170 17208 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 0x0174 17209 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 0x0178 17210 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 0x0188 17211 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 0x018c 17212 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 0x0190 17213 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 0x0194 17214 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0x0200 17215 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP 0x0204 17216 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL 0x0208 17217 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP 0x020c 17218 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL 0x0210 17219 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP 0x0214 17220 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL 0x0218 17221 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP 0x021c 17222 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL 0x0220 17223 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP 0x0224 17224 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL 0x0228 17225 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP 0x022c 17226 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL 0x0230 17227 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 17228 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 17229 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA 0x0248 17230 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP 0x024c 17231 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0x0250 17232 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP 0x0254 17233 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 17234 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS 0x025c 17235 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL 0x025e 17236 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 17237 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 17238 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 17239 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 17240 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 17241 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 17242 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 17243 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 17244 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 17245 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP 0x02a4 17246 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL 0x02a6 17247 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 17248 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP 0x02d4 17249 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL 0x02d6 17250 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0x0328 17251 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP 0x032c 17252 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL 0x032e 17253 17254 17255 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp 17256 // base address: 0x0 17257 #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID 0x0000 17258 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID 0x0002 17259 #define cfgBIF_CFG_DEV0_EPF3_1_COMMAND 0x0004 17260 #define cfgBIF_CFG_DEV0_EPF3_1_STATUS 0x0006 17261 #define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID 0x0008 17262 #define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE 0x0009 17263 #define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS 0x000a 17264 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS 0x000b 17265 #define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE 0x000c 17266 #define cfgBIF_CFG_DEV0_EPF3_1_LATENCY 0x000d 17267 #define cfgBIF_CFG_DEV0_EPF3_1_HEADER 0x000e 17268 #define cfgBIF_CFG_DEV0_EPF3_1_BIST 0x000f 17269 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 0x0010 17270 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 0x0014 17271 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 0x0018 17272 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 0x001c 17273 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 0x0020 17274 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 0x0024 17275 #define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR 0x0028 17276 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID 0x002c 17277 #define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR 0x0030 17278 #define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR 0x0034 17279 #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE 0x003c 17280 #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN 0x003d 17281 #define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT 0x003e 17282 #define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY 0x003f 17283 #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST 0x0048 17284 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W 0x004c 17285 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST 0x0050 17286 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP 0x0052 17287 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL 0x0054 17288 #define cfgBIF_CFG_DEV0_EPF3_1_SBRN 0x0060 17289 #define cfgBIF_CFG_DEV0_EPF3_1_FLADJ 0x0061 17290 #define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD 0x0062 17291 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST 0x0064 17292 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP 0x0066 17293 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP 0x0068 17294 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL 0x006c 17295 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS 0x006e 17296 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP 0x0070 17297 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL 0x0074 17298 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS 0x0076 17299 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 0x0088 17300 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 0x008c 17301 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 0x008e 17302 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2 0x0090 17303 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 0x0094 17304 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 0x0096 17305 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST 0x00a0 17306 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL 0x00a2 17307 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO 0x00a4 17308 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI 0x00a8 17309 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA 0x00a8 17310 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA 0x00aa 17311 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK 0x00ac 17312 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 0x00ac 17313 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64 0x00ae 17314 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 0x00b0 17315 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING 0x00b0 17316 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 0x00b4 17317 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST 0x00c0 17318 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL 0x00c2 17319 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE 0x00c4 17320 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA 0x00c8 17321 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 17322 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 17323 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 0x0108 17324 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 0x010c 17325 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 17326 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS 0x0154 17327 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK 0x0158 17328 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY 0x015c 17329 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS 0x0160 17330 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK 0x0164 17331 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 17332 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 0x016c 17333 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 0x0170 17334 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 0x0174 17335 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 0x0178 17336 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 0x0188 17337 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 0x018c 17338 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 0x0190 17339 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 0x0194 17340 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST 0x0200 17341 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP 0x0204 17342 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL 0x0208 17343 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP 0x020c 17344 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL 0x0210 17345 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP 0x0214 17346 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL 0x0218 17347 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP 0x021c 17348 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL 0x0220 17349 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP 0x0224 17350 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL 0x0228 17351 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP 0x022c 17352 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL 0x0230 17353 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 17354 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 17355 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA 0x0248 17356 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP 0x024c 17357 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST 0x0250 17358 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP 0x0254 17359 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 17360 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS 0x025c 17361 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL 0x025e 17362 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 17363 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 17364 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 17365 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 17366 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 17367 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 17368 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 17369 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 17370 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 17371 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP 0x02a4 17372 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL 0x02a6 17373 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 17374 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP 0x02d4 17375 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL 0x02d6 17376 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST 0x0328 17377 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP 0x032c 17378 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL 0x032e 17379 17380 17381 #endif 17382