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Searched refs:regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h79 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h49 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h82 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX … macro