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Searched refs:regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h8183 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE … macro
H A Ddcn_3_1_5_offset.h7946 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE … macro
H A Ddcn_3_1_4_offset.h15064 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE … macro
H A Ddcn_3_2_1_offset.h7332 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE … macro
H A Ddcn_3_2_0_offset.h7333 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE … macro
H A Ddcn_3_1_6_offset.h8407 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE … macro