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Searched refs:regABM3_BL1_PWM_FINAL_DUTY_CYCLE (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h8181 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE … macro
H A Ddcn_3_1_5_offset.h7944 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE … macro
H A Ddcn_3_1_4_offset.h15062 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE … macro
H A Ddcn_3_2_1_offset.h7330 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE … macro
H A Ddcn_3_2_0_offset.h7331 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE … macro
H A Ddcn_3_1_6_offset.h8405 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE … macro