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Searched refs:regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h7815 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_5_offset.h7578 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_4_offset.h14696 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_2_1_offset.h6964 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_2_0_offset.h6965 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_6_offset.h8039 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro