| /openbmc/qemu/tests/tcg/loongarch64/ |
| H A D | test_pcadd.c | 8 uint64_t rd1 = 0; \
14 : "=r"(rd1), "=r"(rd2) \
16 rm = rd2 - rd1; \
|
| /openbmc/qemu/target/arm/tcg/ |
| H A D | translate.c | 1487 int rdhi, rdlo, rd0, rd1, i; in disas_iwmmxt_insn() local
1671 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1693 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1715 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1729 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1748 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1764 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1786 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1806 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2009 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
[all …]
|
| H A D | translate-neon.c | 1683 TCGv_i32 rd0, rd1; in DO_PREWIDEN() local
1711 rd1 = tcg_temp_new_i32(); in DO_PREWIDEN()
1725 narrowfn(rd1, rn_64); in DO_PREWIDEN()
1728 write_neon_element32(rd1, a->vd, 1, MO_32); in DO_PREWIDEN()
1772 TCGv_i64 rd0, rd1, tmp; in DO_NARROW_3D() local
1799 rd1 = tcg_temp_new_i64(); in DO_NARROW_3D()
1809 opfn(rd1, rn, rm); in DO_NARROW_3D()
1817 accfn(rd1, tmp, rd1); in DO_NARROW_3D()
2937 TCGv_i32 rd0, rd1; in do_vmovn() local
2963 rd1 = tcg_temp_new_i32(); in do_vmovn()
[all …]
|
| /openbmc/linux/Documentation/translations/zh_CN/scheduler/ |
| H A D | sched-energy.rst | 92 RDs: |----rd1----|-----rd2-----|
95 每个根域包含6个CPU。这两个根域在上图中被表示为rd1和rd2。由于pd4与rd1和rd2
98 * rd1->pd: pd0 -> pd4
|
| /openbmc/qemu/tests/tcg/mips/user/isa/r5900/ |
| H A D | test_r5900_multu.c | 50 uint64_t rd1 = multu1(rs, rt); in multu_variants() local
52 assert(rd == rd1); in multu_variants()
|
| H A D | test_r5900_maddu.c | 58 int64_t rd1 = maddu1(a, rs, rt); in maddu_variants() local
60 assert(rd == rd1); in maddu_variants()
|
| H A D | test_r5900_mult.c | 50 int64_t rd1 = mult1(rs, rt); in mult_variants() local
52 assert(rd == rd1); in mult_variants()
|
| H A D | test_r5900_madd.c | 58 int64_t rd1 = madd1(a, rs, rt); in madd_variants() local
60 assert(rd == rd1); in madd_variants()
|
| /openbmc/qemu/target/riscv/ |
| H A D | xthead.decode | 14 %rd1 7:5
30 &th_pair rd1 rs rd2 sh2
42 @th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2
|
| /openbmc/linux/drivers/staging/vt6655/ |
| H A D | desc.h | 186 volatile struct vnt_rdes1 rd1; member
|
| H A D | dpc.c | 129 frame_size = le16_to_cpu(curr_rd->rd1.req_count) in vnt_receive_frame()
|
| H A D | card.c | 446 pDesc->rd1.req_count = cpu_to_le16(priv->rx_buf_sz); in CARDvSafeResetRx()
454 pDesc->rd1.req_count = cpu_to_le16(priv->rx_buf_sz); in CARDvSafeResetRx()
|
| H A D | device_main.c | 873 rd->rd1.req_count = cpu_to_le16(priv->rx_buf_sz); in device_alloc_rx_buf()
|
| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_its.c | 852 uint64_t rd1, rd2; in process_movall() local
854 rd1 = FIELD_EX64(cmdpkt[2], MOVALL_2, RDBASE1); in process_movall()
857 trace_gicv3_its_cmd_movall(rd1, rd2); in process_movall()
859 if (rd1 >= s->gicv3->num_cpu) { in process_movall()
863 __func__, rd1, s->gicv3->num_cpu); in process_movall()
874 if (rd1 == rd2) { in process_movall()
880 gicv3_redist_movall_lpis(&s->gicv3->cpu[rd1], &s->gicv3->cpu[rd2]); in process_movall()
|
| H A D | trace-events | 206 gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " R…
|
| /openbmc/linux/net/wireless/ |
| H A D | reg.c | 1334 static int reg_rules_intersect(const struct ieee80211_regdomain *rd1, in reg_rules_intersect() argument
1369 max_bandwidth1 = reg_get_max_bandwidth(rd1, rule1); in reg_rules_intersect()
1497 regdom_intersect(const struct ieee80211_regdomain *rd1, in regdom_intersect() argument
1507 if (!rd1 || !rd2) in regdom_intersect()
1518 for (x = 0; x < rd1->n_reg_rules; x++) { in regdom_intersect()
1519 rule1 = &rd1->reg_rules[x]; in regdom_intersect()
1522 if (!reg_rules_intersect(rd1, rd2, rule1, rule2, in regdom_intersect()
1535 for (x = 0; x < rd1->n_reg_rules; x++) { in regdom_intersect()
1536 rule1 = &rd1->reg_rules[x]; in regdom_intersect()
1539 r = reg_rules_intersect(rd1, rd2, rule1, rule2, in regdom_intersect()
[all …]
|
| /openbmc/linux/Documentation/scheduler/ |
| H A D | sched-energy.rst | 104 RDs: |----rd1----|-----rd2-----|
108 containing 6 CPUs. The two root domains are denoted rd1 and rd2 in the
109 above figure. Since pd4 intersects with both rd1 and rd2, it will be
112 * rd1->pd: pd0 -> pd4
|
| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_xthead.c.inc | 910 if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
925 gen_set_gpr(ctx, a->rd1, t1);
952 TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
|
| /openbmc/u-boot/drivers/net/ |
| H A D | sh_eth.h | 76 volatile u32 rd1; member
|
| H A D | sh_eth.c | 134 return port_info->rx_desc_cur->rd1 & 0xffff; in sh_eth_recv_start()
290 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; in sh_eth_rx_desc_init()
|
| /openbmc/qemu/tcg/arm/ |
| H A D | tcg-target.c.inc | 920 TCGReg rd1, TCGReg rn, TCGReg rm)
924 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
928 TCGReg rd1, TCGReg rn, TCGReg rm)
932 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
|
| /openbmc/linux/Documentation/admin-guide/ |
| H A D | md.rst | 604 So for a 3 drive array there will be rd0, rd1, rd2.
|
| H A D | ras.rst | 1017 Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs
|
| /openbmc/qemu/disas/ |
| H A D | nanomips.c | 10021 const char *rd1 = GPR(decode_gpr_gpr1(rd1_value, info), info); in MOVE_BALC() local
10025 return img_format("MOVE.BALC %s, %s, %s", rd1, rtz4, s); in MOVE_BALC()
|