| /openbmc/qemu/hw/net/ |
| H A D | smc91c111.c | 43 uint16_t rcr; member
74 VMSTATE_UINT16(rcr, smc91c111_state),
157 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) { in smc91c111_can_receive()
370 s->rcr = 0; in smc91c111_reset()
448 SET_LOW(rcr, value); in smc91c111_writeb()
451 SET_HIGH(rcr, value); in smc91c111_writeb()
452 if (s->rcr & RCR_SOFT_RST) { in smc91c111_writeb()
634 return s->rcr & 0xff; in smc91c111_readb()
636 return s->rcr >> 8; in smc91c111_readb()
805 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) in smc91c111_receive()
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| H A D | mcf_fec.c | 50 uint32_t rcr; member
309 s->rcr = 0x05ee0001; in mcf_fec_reset()
373 case 0x084: return s->rcr; in mcf_fec_read()
443 s->rcr = value & 0x07ff003f; in mcf_fec_write()
579 if (size > (s->rcr >> 16)) { in mcf_fec_receive()
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| /openbmc/u-boot/drivers/net/pfe_eth/ |
| H A D | pfe_eth.c | 53 u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; in pfe_gemac_set_speed() local
61 rcr |= EMAC_RCNTRL_RMII_10T; in pfe_gemac_set_speed()
69 rcr &= ~EMAC_RCNTRL_LOOP; in pfe_gemac_set_speed()
71 rcr |= EMAC_RCNTRL_FCE; in pfe_gemac_set_speed()
74 rcr |= EMAC_RCNTRL_MII_MODE; in pfe_gemac_set_speed()
76 writel(rcr, gemac_base + EMAC_RCNTRL_REG); in pfe_gemac_set_speed()
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| /openbmc/u-boot/arch/m68k/cpu/mcf5445x/ |
| H A D | cpu.c | 25 out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT); in do_reset()
27 setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
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| /openbmc/qemu/hw/isa/ |
| H A D | piix.c | 172 d->rcr = 0; in piix_reset()
202 s->rcr = 0; in piix4_post_load()
225 return (piix3->rcr != 0); in piix3_rcr_needed()
234 VMSTATE_UINT8(rcr, PIIXState),
264 VMSTATE_UINT8_V(rcr, PIIXState, 3),
277 d->rcr = val & 2; /* keep System Reset type only */ in rcr_write()
284 return d->rcr; in rcr_read()
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91_pdc.h | 11 u32 rcr; /* 0x104 Receive Counter Register */ member
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| H A D | at91_mc.h | 67 u32 rcr; /* 0x00 MC Remap Control Register */ member
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| /openbmc/qemu/include/hw/southbridge/ |
| H A D | piix.h | 66 uint8_t rcr; member
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| /openbmc/u-boot/drivers/net/ |
| H A D | mcffec.c | 89 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | in setFecDuplexSpeed()
94 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | in setFecDuplexSpeed()
101 fecp->rcr &= ~0x200; /* disabled 10T base */ in setFecDuplexSpeed()
109 fecp->rcr |= 0x200; /* enabled 10T base */ in setFecDuplexSpeed()
260 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); in dbgFecRegs()
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| H A D | fsl_mcdmafec.c | 119 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); in dbg_fec_regs()
156 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | in set_fec_duplex_speed()
161 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | in set_fec_duplex_speed()
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| /openbmc/u-boot/arch/m68k/cpu/mcf5227x/ |
| H A D | cpu.c | 24 setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
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| /openbmc/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | cpu.c | 33 out_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
270 out_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
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| /openbmc/u-boot/arch/m68k/cpu/mcf523x/ |
| H A D | cpu.c | 25 out_8(&ccm->rcr, CCM_RCR_SOFTRST); in do_reset()
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| /openbmc/u-boot/arch/m68k/cpu/mcf532x/ |
| H A D | cpu.c | 26 setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
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| /openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
| H A D | ssi.h | 21 u32 rcr; member
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| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | fec.h | 127 u32 rcr; /* 0x104 */ member
157 u32 rcr;
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| H A D | fsl_mcdmafec.h | 27 u32 rcr; /* 0x084 */ member
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| H A D | immap_5441x.h | 98 u8 rcr; member
319 u32 rcr; /* 0x188 */ member
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| H A D | immap_520x.h | 82 u8 rcr; member
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| H A D | immap_5235.h | 196 u8 rcr; /* 0x01 */ member
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| H A D | immap_5227x.h | 65 u8 rcr; member
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| H A D | immap_5301x.h | 140 u8 rcr; member
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| /openbmc/u-boot/arch/powerpc/cpu/mpc83xx/ |
| H A D | cpu.c | 152 immap->reset.rcr = RCR_SWHR; in do_reset()
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| /openbmc/u-boot/drivers/sysreset/ |
| H A D | sysreset_mpc83xx.c | 55 out_be32(&immap->reset.rcr, RCR_SWHR); in __do_reset()
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| /openbmc/qemu/hw/misc/ |
| H A D | npcm_clk.c | 939 uint32_t rcr; in npcm7xx_clk_perform_watchdog_reset() local
942 rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n]; in npcm7xx_clk_perform_watchdog_reset()
943 if (rcr & NPCM7XX_CLK_WDRCR_CA9C) { in npcm7xx_clk_perform_watchdog_reset()
948 __func__, rcr); in npcm7xx_clk_perform_watchdog_reset()
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