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Searched refs:qemu_set_irq (Results 1 – 25 of 278) sorted by relevance

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/openbmc/qemu/include/hw/
H A Dirq.h8 void qemu_set_irq(qemu_irq irq, int level);
12 qemu_set_irq(irq, 1); in qemu_irq_raise()
17 qemu_set_irq(irq, 0); in qemu_irq_lower()
22 qemu_set_irq(irq, 1); in qemu_irq_pulse()
23 qemu_set_irq(irq, 0); in qemu_irq_pulse()
/openbmc/qemu/hw/char/
H A Davr_usart.c48 qemu_set_irq(usart->rxc_irq, 1); in avr_usart_receive()
103 qemu_set_irq(usart->rxc_irq, 0); in avr_usart_reset()
104 qemu_set_irq(usart->txc_irq, 0); in avr_usart_reset()
105 qemu_set_irq(usart->dre_irq, 0); in avr_usart_reset()
131 qemu_set_irq(usart->rxc_irq, 0); in avr_usart_read()
176 qemu_set_irq(usart->txc_irq, 1); in avr_usart_write()
180 qemu_set_irq(usart->dre_irq, 1); in avr_usart_write()
192 qemu_set_irq(usart->txc_irq, 0); in avr_usart_write()
210 qemu_set_irq(usart->rxc_irq, in avr_usart_write()
213 qemu_set_irq(usart->txc_irq, in avr_usart_write()
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H A Drenesas_sci.c89 qemu_set_irq(sci->irq[ERI], 1); in receive()
108 qemu_set_irq(sci->irq[TEI], 0); in send_byte()
122 qemu_set_irq(sci->irq[TEI], 1); in txend()
172 qemu_set_irq(sci->irq[TEI], 0); in sci_write()
175 qemu_set_irq(sci->irq[ERI], 0); in sci_write()
193 qemu_set_irq(sci->irq[ERI], 0); in sci_write()
267 qemu_set_irq(sci->irq[ERI], 1); in sci_event()
H A Dibex_uart.c80 qemu_set_irq(s->tx_watermark, 1); in ibex_uart_update_irqs()
82 qemu_set_irq(s->tx_watermark, 0); in ibex_uart_update_irqs()
86 qemu_set_irq(s->rx_watermark, 1); in ibex_uart_update_irqs()
88 qemu_set_irq(s->rx_watermark, 0); in ibex_uart_update_irqs()
92 qemu_set_irq(s->tx_empty, 1); in ibex_uart_update_irqs()
94 qemu_set_irq(s->tx_empty, 0); in ibex_uart_update_irqs()
98 qemu_set_irq(s->rx_overflow, 1); in ibex_uart_update_irqs()
100 qemu_set_irq(s->rx_overflow, 0); in ibex_uart_update_irqs()
H A Dgoldfish_tty.c81 qemu_set_irq(s->irq, 0); in goldfish_tty_cmd()
89 qemu_set_irq(s->irq, 1); in goldfish_tty_cmd()
120 qemu_set_irq(s->irq, 0); in goldfish_tty_cmd()
189 qemu_set_irq(s->irq, 1); in goldfish_tty_receive()
H A Dsh_serial.c115 qemu_set_irq(s->txi, val & (1 << 7)); in sh_serial_write()
118 qemu_set_irq(s->rxi, 0); in sh_serial_write()
160 qemu_set_irq(s->rxi, 0); in sh_serial_write()
345 qemu_set_irq(s->rxi, 1); in sh_serial_timeout_int()
366 qemu_set_irq(s->rxi, 1); in sh_serial_receive1()
H A Dcmsdk-apb-uart.c108 qemu_set_irq(s->txint, !!(s->intstatus & R_INTSTATUS_TX_MASK)); in cmsdk_apb_uart_update()
109 qemu_set_irq(s->rxint, !!(s->intstatus & R_INTSTATUS_RX_MASK)); in cmsdk_apb_uart_update()
110 qemu_set_irq(s->txovrint, !!(s->intstatus & R_INTSTATUS_TXO_MASK)); in cmsdk_apb_uart_update()
111 qemu_set_irq(s->rxovrint, !!(s->intstatus & R_INTSTATUS_RXO_MASK)); in cmsdk_apb_uart_update()
112 qemu_set_irq(s->uartint, !!(s->intstatus)); in cmsdk_apb_uart_update()
/openbmc/qemu/hw/timer/
H A Davr_timer16.c264 qemu_set_irq(t16->ovf_irq, 1); in avr_timer16_interrupt()
278 qemu_set_irq(t16->capt_irq, 1); in avr_timer16_interrupt()
284 qemu_set_irq(t16->compa_irq, 1); in avr_timer16_interrupt()
288 qemu_set_irq(t16->compb_irq, 1); in avr_timer16_interrupt()
292 qemu_set_irq(t16->compc_irq, 1); in avr_timer16_interrupt()
305 qemu_set_irq(t16->capt_irq, 0); in avr_timer16_reset()
306 qemu_set_irq(t16->compa_irq, 0); in avr_timer16_reset()
307 qemu_set_irq(t16->compb_irq, 0); in avr_timer16_reset()
308 qemu_set_irq(t16->compc_irq, 0); in avr_timer16_reset()
309 qemu_set_irq(t16->ovf_irq, 0); in avr_timer16_reset()
H A Dibex_timer.c83 qemu_set_irq(s->irq, true); in ibex_timer_update_irqs()
90 qemu_set_irq(s->irq, false); in ibex_timer_update_irqs()
113 qemu_set_irq(s->irq, true); in ibex_timer_cb()
225 qemu_set_irq(s->irq, true); in ibex_timer_write()
/openbmc/qemu/hw/watchdog/
H A Dsbsa_gwdt.c146 qemu_set_irq(s->irq, 0); in sbsa_gwdt_write()
153 qemu_set_irq(s->irq, 0); in sbsa_gwdt_write()
160 qemu_set_irq(s->irq, 0); in sbsa_gwdt_write()
200 qemu_set_irq(s->irq, 1); in sbsa_gwdt_timer_sysinterrupt()
/openbmc/qemu/hw/misc/
H A Dmst_fpga.c98 qemu_set_irq(s->parent, s->intsetclr & s->intmskena); in mst_fpga_set_irq()
173 qemu_set_irq(s->parent, s->intsetclr & s->intmskena); in mst_fpga_writeb()
177 qemu_set_irq(s->parent, s->intsetclr & s->intmskena); in mst_fpga_writeb()
202 qemu_set_irq(s->parent, s->intsetclr & s->intmskena); in mst_fpga_post_load()
H A Davr_power.c39 qemu_set_irq(s->irq[i], 0); in avr_mask_reset()
65 qemu_set_irq(s->irq[i], (val8 & (1 << i)) != 0); in avr_mask_write()
H A Diotkit-secctl.c279 qemu_set_irq(ppc->ap[i], v); in iotkit_secctl_update_ppc_ap()
289 qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1)); in iotkit_secctl_ppc_ns_write()
310 qemu_set_irq(ppc->irq_clear, extract32(value, ppc->irq_bit_offset, 1)); in iotkit_secctl_ppc_update_irq_clear()
317 qemu_set_irq(ppc->irq_enable, extract32(value, ppc->irq_bit_offset, 1)); in iotkit_secctl_ppc_update_irq_enable()
325 qemu_set_irq(msc_irqs[i], extract32(value, i + 16, 1)); in iotkit_secctl_update_mscexp_irqs()
334 qemu_set_irq(s->msc_irq, level); in iotkit_secctl_update_msc_irq()
357 qemu_set_irq(s->nsc_cfg_irq, s->nsccfg); in iotkit_secctl_s_write()
362 qemu_set_irq(s->sec_resp_cfg, s->secrespcfg); in iotkit_secctl_s_write()
H A Dxlnx-zynqmp-apu-ctrl.c35 qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i))); in update_wfi_out()
63 qemu_set_irq(s->cpu_power_status[i], !!new); in zynqmp_apu_pwrctl_post_write()
74 qemu_set_irq(s->irq_imr, pending); in imr_update_irq()
H A Dbcm2835_mphi.c31 qemu_set_irq(s->irq, 1); in mphi_raise_irq()
36 qemu_set_irq(s->irq, 0); in mphi_lower_irq()
/openbmc/qemu/hw/intc/
H A Domap_intc.c103 qemu_set_irq(s->parent_intr[is_fiq], 1); in omap_inth_update()
265 qemu_set_irq(s->parent_intr[1], 0); in omap_inth_write()
270 qemu_set_irq(s->parent_intr[0], 0); in omap_inth_write()
362 qemu_set_irq(s->parent_intr[0], 0); in omap_inth_reset()
363 qemu_set_irq(s->parent_intr[1], 0); in omap_inth_reset()
535 qemu_set_irq(s->parent_intr[1], 0); in omap2_inth_write()
540 qemu_set_irq(s->parent_intr[0], 0); in omap2_inth_write()
H A Dimx_avic.c67 qemu_set_irq(s->fiq, !!flags); in imx_avic_update()
71 qemu_set_irq(s->irq, !!flags); in imx_avic_update()
82 qemu_set_irq(s->irq, 1); in imx_avic_update()
87 qemu_set_irq(s->irq, 0); in imx_avic_update()
H A Dloongarch_pch_msi.c36 qemu_set_irq(s->pch_msi_irq[irq_num], 1); in loongarch_msi_mem_write()
49 qemu_set_irq(s->pch_msi_irq[irq], level); in pch_msi_irq_handler()
H A Detraxfs_pic.c80 qemu_set_irq(fs->parent_irq, vector); in pic_update()
127 qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]); in nmi_handler()
/openbmc/qemu/hw/gpio/
H A Dgpio_key.c65 qemu_set_irq(s->irq, 0); in gpio_key_timer_expired()
73 qemu_set_irq(s->irq, 1); in gpio_key_set_irq()
H A Dimx_gpio.c72 qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0); in imx_gpio_update_int()
73 qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0); in imx_gpio_update_int()
75 qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0); in imx_gpio_update_int()
144 qemu_set_irq(s->output[i], extract32(s->dr, i, 1)); in imx_gpio_set_all_output_lines()
/openbmc/qemu/hw/isa/
H A Di82378.c52 qemu_set_irq(s->cpu_intr, level); in i82378_request_out0_irq()
60 qemu_set_irq(s->isa_irqs_in[irq], level); in i82378_request_pic_irq()
/openbmc/qemu/hw/cpu/
H A Drealview_mpcore.c51 qemu_set_irq(s->rvic[i][irq], level); in mpcore_rirq_set_irq()
56 qemu_set_irq(s->cpuic[irq], level); in mpcore_rirq_set_irq()
/openbmc/qemu/hw/input/
H A Dlasips2.c136 qemu_set_irq(s->irq, level); in lasips2_update_irq()
169 qemu_set_irq(lp->irq, 1); in lasips2_reg_write()
203 qemu_set_irq(lp->irq, 0); in lasips2_reg_read()
330 qemu_set_irq(s->irq, level); in lasips2_port_set_irq()
/openbmc/qemu/hw/ppc/
H A Dprep_systemio.c73 qemu_set_irq(s->softreset_irq, s->sreset); in prep_port0092_write()
209 qemu_set_irq(s->non_contiguous_io_map_irq, in prep_port0850_write()
262 qemu_set_irq(s->non_contiguous_io_map_irq, in prep_systemio_realize()

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