| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_k2g.c | 20 .ptr0 = 0x42C21590ul,
60 .ptr0 = 0x42C21590ul,
121 .ptr0 = 0x42C21590ul,
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| H A D | ddr3_cfg.c | 18 .ptr0 = 0x42C21590ul,
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| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 18 unsigned int ptr0; member
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| /openbmc/u-boot/board/imgtec/ci20/ |
| H A D | ci20.c | 293 .ptr0 = 0x002000d4,
337 .ptr0 = 0x002000d4,
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a33.h | 79 u32 ptr0; /* 0x44 */ member
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| H A D | dram_sun8i_a83t.h | 79 u32 ptr0; /* 0x44 */ member
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| H A D | dram_sun8i_a23.h | 170 u32 ptr0; /* 0x1c */ member
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| H A D | dram_sun6i.h | 163 u32 ptr0; /* 0x18 */ member
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 131 u32 ptr0; member
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| H A D | stm32mp1_ddr_regs.h | 147 u32 ptr0; /* 0x18 R/W PHY Timing 0*/ member
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| H A D | stm32mp1_ddr.c | 140 DDRPHY_REG_TIMING(ptr0),
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| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 24 debug_ddr_cfg("ptr0 0x%08X\n", ptr->ptr0); in dump_phy_config()
307 spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) | in init_ddr3param()
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| H A D | ddr3.c | 39 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
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| /openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | sdram.c | 79 writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0); in ddr_phy_init()
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| /openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/ |
| H A D | jz4780_dram.h | 440 u32 ptr0; /* PHY Timing Register 0 */ member
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun6i.c | 128 &mctl_phy->ptr0); in mctl_channel_init()
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | emit.c.inc | 618 #define FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, even, odd) \
625 fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \
630 #define FMA_SSE(uname, ptr0, ptr1, ptr2, flags) \
631 FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, flags, flags) \
636 fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \
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