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Searched refs:pss_mss_ctrl_reg (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/ppc/
H A Dpnv_chiptod.c135 val = chiptod->pss_mss_ctrl_reg; in pnv_chiptod_xscom_read()
304 chiptod->pss_mss_ctrl_reg = val & PPC_BITMASK(0, 31); in pnv_chiptod_xscom_write()
528 chiptod->pss_mss_ctrl_reg = 0; in pnv_chiptod_reset()
530 chiptod->pss_mss_ctrl_reg |= PPC_BIT(1); /* TOD is master */ in pnv_chiptod_reset()
533 chiptod->pss_mss_ctrl_reg |= PPC_BIT(2); in pnv_chiptod_reset()
/openbmc/qemu/include/hw/ppc/
H A Dpnv_chiptod.h40 uint64_t pss_mss_ctrl_reg; member