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Searched refs:prefer_i64 (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/tcg/
H A Dtcg-op-gvec.c1696 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1845 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2605 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2622 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2639 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2656 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2673 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2690 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2738 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2779 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
/openbmc/qemu/include/tcg/
H A Dtcg-op-gvec-common.h99 bool prefer_i64; member
120 bool prefer_i64; member
141 bool prefer_i64; member
162 bool prefer_i64; member
183 bool prefer_i64; member
206 bool prefer_i64; member
227 bool prefer_i64; member
/openbmc/qemu/target/arm/tcg/
H A Dgengvec.c149 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ssra()
225 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_usra()
334 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srshr()
424 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srsra()
529 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_urshr()
638 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ursra()
722 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sri()
810 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sli()
914 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mla()
946 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mls()
[all …]
H A Dgengvec64.c160 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_eor3()
186 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_bcax()
H A Dtranslate-sve.c598 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_bsl1n()
642 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_bsl2n()
671 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_nbsl()
1300 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_AND_pppp()
1338 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_BIC_pppp()
1369 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_EOR_pppp()
1416 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORR_pppp()
1447 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORN_pppp()
1475 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NOR_pppp()
1503 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NAND_pppp()
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc1358 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
/openbmc/qemu/target/i386/tcg/
H A Demit.c.inc2755 .prefer_i64 = TCG_TARGET_REG_BITS == 64