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Searched refs:prediv (Results 1 – 25 of 41) sorted by relevance

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/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c84 unsigned prediv : 6; member
97 unsigned int prediv; member
120 .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
152 u32 prediv; member
164 .prediv = 8,
170 .prediv = 6,
176 .prediv = 24,
182 .prediv = 4,
188 .prediv = 24,
194 .prediv = 3,
[all …]
/openbmc/linux/drivers/clk/mmp/
H A Dclk-audio.c120 unsigned int prediv; in audio_pll_recalc_rate() local
137 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_recalc_rate()
138 if (predivs[prediv].parent_rate != parent_rate) in audio_pll_recalc_rate()
147 val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract); in audio_pll_recalc_rate()
148 val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk); in audio_pll_recalc_rate()
149 val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk); in audio_pll_recalc_rate()
158 freq = predivs[prediv].freq_vco; in audio_pll_recalc_rate()
170 unsigned int prediv; in audio_pll_round_rate() local
174 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_round_rate()
175 if (predivs[prediv].parent_rate != *parent_rate) in audio_pll_round_rate()
[all …]
/openbmc/linux/arch/mips/ar7/
H A Dclock.c73 u32 prediv; member
100 static void approximate(int base, int target, int *prediv, in approximate() argument
111 *prediv = j; in approximate()
117 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
122 for (*prediv = 1; *prediv <= 32; (*prediv)++) { in calculate()
123 tmp_base = base / *prediv; in calculate()
133 if (base / *prediv * *mul / *postdiv != target) { in calculate()
134 approximate(base, target, prediv, postdiv, mul); in calculate()
135 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
142 *prediv, *postdiv, *mul); in calculate()
[all …]
/openbmc/u-boot/drivers/video/rockchip/
H A Drk_mipi.c203 u64 prediv = 1; in rk_mipi_phy_enable() local
276 prediv = i; in rk_mipi_phy_enable()
280 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
281 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
285 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
288 test_data[0] = prediv - 1; in rk_mipi_phy_enable()
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Ddm365_lowlevel.h16 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
17 int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
H A Dpll_defs.h19 unsigned int prediv; /* 0x114 */ member
/openbmc/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c25 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) in dm365_pll1_init() argument
57 writel(prediv, &dv_pll0_regs->prediv); in dm365_pll1_init()
102 int dm365_pll2_init(unsigned long pllm, unsigned long prediv) in dm365_pll2_init() argument
139 writel(prediv, &dv_pll1_regs->prediv); in dm365_pll2_init()
/openbmc/linux/drivers/media/dvb-frontends/
H A Dtua6100.c62 u32 prediv; in tua6100_set_params() local
105 prediv = (c->frequency * _R_VAL) / (_ri / 1000); in tua6100_set_params()
106 div = prediv / _P_VAL; in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu_mux.c21 u16 prediv = 1; in ccu_mux_get_prediv() local
30 return common->prediv; in ccu_mux_get_prediv()
43 prediv = cm->fixed_predivs[i].div; in ccu_mux_get_prediv()
55 prediv = div + 1; in ccu_mux_get_prediv()
59 return prediv; in ccu_mux_get_prediv()
H A Dccu_gate.h77 .prediv = _prediv, \
105 .prediv = _prediv, \
H A Dccu_gate.c85 rate /= cg->common.prediv; in ccu_gate_recalc_rate()
97 div = cg->common.prediv; in ccu_gate_round_rate()
H A Dccu_common.h32 u32 prediv; member
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c281 unsigned long mult = 1, prediv = 1, output_div = 2; in pll_freq_get() local
290 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; in pll_freq_get()
299 ret = ret / prediv / output_div * mult; in pll_freq_get()
331 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; in pll_freq_get()
336 ret = ((ret / prediv) * mult) / output_div; in pll_freq_get()
/openbmc/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c163 u32 value, mult, div, prediv, postdiv; in gen3_clk_get_rate64() local
293 prediv = (value >> CPG_RPC_PREDIV_OFFSET) & in gen3_clk_get_rate64()
295 if (prediv == 2) in gen3_clk_get_rate64()
297 else if (prediv == 3) in gen3_clk_get_rate64()
308 core->parent, prediv, postdiv, rate); in gen3_clk_get_rate64()
/openbmc/linux/drivers/clk/pistachio/
H A Dclk-pll.c273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
276 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
417 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_laint_recalc_rate()
425 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); in pll_gf40lp_laint_recalc_rate()
/openbmc/linux/drivers/clk/
H A Dclk-vt8500.c351 u32 *multiplier, u32 *prediv) in vt8500_find_pll_bits() argument
359 *prediv = 1; in vt8500_find_pll_bits()
364 *prediv = 2; in vt8500_find_pll_bits()
366 *prediv = 1; in vt8500_find_pll_bits()
368 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
369 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
H A Dclk-versaclock3.c245 unsigned int prediv, premul; in vc3_pfd_recalc_rate() local
249 regmap_read(vc3->regmap, pfd->offs, &prediv); in vc3_pfd_recalc_rate()
252 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
259 mdiv = VC3_PLL1_M_DIV(prediv); in vc3_pfd_recalc_rate()
262 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
270 mdiv = VC3_PLL2_M_DIV(prediv); in vc3_pfd_recalc_rate()
273 if (prediv & pfd->mdiv1_bitmsk) in vc3_pfd_recalc_rate()
276 mdiv = VC3_PLL3_M_DIV(prediv); in vc3_pfd_recalc_rate()
279 if (prediv & pfd->mdiv2_bitmsk) in vc3_pfd_recalc_rate()
/openbmc/linux/drivers/media/i2c/
H A Dtc358746.c1093 const unsigned char prediv[] = { 2, 4, 8 }; in tc358746_find_mclk_settings() local
1133 for (i = 0; i < ARRAY_SIZE(prediv); i++) { in tc358746_find_mclk_settings()
1134 postdiv = mclkdiv / prediv[i]; in tc358746_find_mclk_settings()
1140 mclk_prediv = prediv[i]; in tc358746_find_mclk_settings()
1142 best_mclk_rate = pll_rate / (prediv[i] * postdiv); in tc358746_find_mclk_settings()
1184 unsigned int prediv, postdiv; in tc358746_recalc_rate() local
1199 prediv = FIELD_GET(MCLKDIV_MASK, val); in tc358746_recalc_rate()
1200 if (prediv == MCLKDIV_8) in tc358746_recalc_rate()
1201 prediv = 8; in tc358746_recalc_rate()
1202 else if (prediv == MCLKDIV_4) in tc358746_recalc_rate()
[all …]
H A Dst-vgxy61.c459 static void compute_pll_parameters_by_freq(u32 freq, u8 *prediv, u8 *mult) in compute_pll_parameters_by_freq() argument
469 *prediv = predivs[i]; in compute_pll_parameters_by_freq()
470 if (freq / *prediv < 12 * HZ_PER_MHZ) in compute_pll_parameters_by_freq()
479 *mult = ((804 * HZ_PER_MHZ) * (*prediv) + freq / 2) / freq; in compute_pll_parameters_by_freq()
1571 u8 prediv, mult; in vgxy61_configure() local
1575 compute_pll_parameters_by_freq(sensor->clk_freq, &prediv, &mult); in vgxy61_configure()
1576 sensor_freq = (mult * sensor->clk_freq) / prediv; in vgxy61_configure()
1587 vgxy61_write_reg(sensor, VGXY61_REG_CLK_PLL_PREDIV, prediv, &ret); in vgxy61_configure()
/openbmc/linux/drivers/clk/keystone/
H A Dpll.c81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
96 prediv = (val & pll_data->plld_mask); in clk_pllclk_recalc()
109 rate /= (prediv + 1); in clk_pllclk_recalc()
/openbmc/linux/drivers/clk/imx/
H A Dclk-composite-8m.c52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
58 *prediv = 1; in imx8m_clk_composite_compute_dividers()
66 *prediv = div1; in imx8m_clk_composite_compute_dividers()
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c220 u8 prediv; member
358 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
385 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_dsidphy_mipi_mode_enable()
529 u8 prediv = 2; in inno_dsidphy_lvds_mode_enable() local
543 REG_PREDIV_MASK, REG_PREDIV(prediv)); in inno_dsidphy_lvds_mode_enable()
H A Dphy-rockchip-inno-hdmi.c253 u8 prediv; member
268 u8 prediv; member
799 RK3228_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3228_clk_set_rate()
953 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_clk_set_rate()
1071 RK3228_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3228_power_on()
1184 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_power_on()
1192 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_power_on()
/openbmc/linux/drivers/clk/ralink/
H A Dclk-mt7621.c262 u32 pll, prediv, fbdiv; in mt7621_cpu_recalc_rate() local
279 prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll); in mt7621_cpu_recalc_rate()
280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; in mt7621_cpu_recalc_rate()
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dclock_defs.h20 u32 prediv; /* 14 */ member

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