1 #ifndef CPER_SECTION_PCIE_H 2 #define CPER_SECTION_PCIE_H 3 4 #ifdef __cplusplus 5 extern "C" { 6 #endif 7 8 #include <stdio.h> 9 #include <json.h> 10 #include <libcper/Cper.h> 11 12 #define PCIE_ERROR_VALID_BITFIELD_NAMES \ 13 (const char *[]){ "portTypeValid", \ 14 "versionValid", \ 15 "commandStatusValid", \ 16 "deviceIDValid", \ 17 "deviceSerialNumberValid", \ 18 "bridgeControlStatusValid", \ 19 "capabilityStructureStatusValid", \ 20 "aerInfoValid" } 21 #define PCIE_ERROR_PORT_TYPES_KEYS (int[]){ 0, 1, 4, 5, 6, 7, 8, 9, 10 } 22 #define PCIE_ERROR_PORT_TYPES_VALUES \ 23 (const char *[]){ "PCI Express End Point", \ 24 "Legacy PCI End Point Device", \ 25 "Root Port", \ 26 "Upstream Switch Port", \ 27 "Downstream Switch Port", \ 28 "PCI Express to PCI/PCI-X Bridge", \ 29 "PCI/PCI-X Bridge to PCI Express Bridge", \ 30 "Root Complex Integrated Endpoint Device", \ 31 "Root Complex Event Collector" } 32 33 struct class_code { 34 UINT8 base; 35 UINT8 sub; 36 UINT8 programming; 37 const char *name; 38 }; 39 40 json_object *cper_section_pcie_to_ir(const UINT8 *section, UINT32 size, 41 char **desc_string); 42 void ir_section_pcie_to_cper(json_object *section, FILE *out); 43 44 /* 45 * This file is designed as a standard c header file and as a script friendly 46 * source fo the PCIe PCIe Capability and Advanced Error Registers structures. 47 * The template of each register is: 48 * 49 * 50 * * <Name of Capabaility Structure> 51 * * CAPABILITY_ID = <id of capability structure> 52 * * <Register Name> 53 * * Offset: <offset of the register in the capability structure> 54 * struct { 55 * <register width> <field name> : <field width>; 56 * <register width> <field name> : <field width>; 57 * <register width> <field name> : <field width>; 58 * } 59 */ 60 61 /* 62 * PCI Express Capability Structure 63 * CAPABILITY_ID = 0x10 64 * PCI Express Capability Structure Header 65 * Offset: 0x0 66 */ 67 typedef struct { 68 // bits [7:0] - Capability ID (should be 0x10) 69 UINT16 capability_id : 8; 70 // bits [7:0] - Next capability pointer 71 UINT16 next_capability_pointer : 8; 72 } __attribute__((packed)) pcie_capability_header_t; 73 74 /* 75 * PCI Express Capability Structure 76 * CAPABILITY_ID = 0x10 77 * PCI Express Capabilities Register 78 * Offset: 0x2 79 */ 80 typedef struct { 81 UINT16 capability_version : 4; // bits [3:0] 82 UINT16 device_port_type : 4; // bits [7:4] 83 UINT16 slot_implemented : 1; // bit [8] 84 UINT16 interrupt_message_number : 5; // bits [13:9] 85 UINT16 undefined : 1; // bit [14] 86 UINT16 flit_mode_supported : 1; // bit [15] 87 } __attribute__((packed)) pcie_capabilities_t; 88 89 static const char *device_port_type_dict[] = { 90 "PCIE", // 0x0 91 "PCI", // 0x1 92 "ROOT_PORT", // 0x4 93 "UPSTREAM", // 0x5 94 "DOWNSTREAM", // 0x6 95 "PCIE_PCI_BRIDGE", // 0x7 96 "PCI_PCIE_BRIDGE", // 0x8 97 "RCiEP", // 0x9 98 "RCEC", // 0xa 99 }; 100 101 static const size_t device_port_type_dict_size = 102 sizeof(device_port_type_dict) / sizeof(device_port_type_dict[0]); 103 104 /* 105 * Begin Of PCIe Capability Registers 106 */ 107 108 /* 109 * PCI Express Capability Structure 110 * CAPABILITY_ID = 0x10 111 * Device Capabilities Register 112 * Offset: 0x4 113 */ 114 typedef struct { 115 UINT32 max_payload_size_supported : 3; // bits [2:0] 116 UINT32 phantom_functions_supported : 2; // bits [4:3] 117 UINT32 extended_tag_field_supported : 1; // bit [5] 118 UINT32 endpoint_l0s_acceptable_latency : 3; // bits [8:6] 119 UINT32 endpoint_l1_acceptable_latency : 3; // bits [11:9] 120 UINT32 undefined : 3; // bits [14:12] 121 UINT32 role_based_error_reporting : 1; // bit [15] 122 UINT32 err_cor_subclass_capable : 1; // bit [16] 123 UINT32 rx_mps_fixed : 1; // bits [17] 124 UINT32 captured_slot_power_limit_value : 8; // bits [25:18] 125 UINT32 captured_slot_power_limit_scale : 2; // bits [27:26] 126 UINT32 function_level_reset_capability : 1; // bit [28] 127 UINT32 mixed_mps_supported : 1; // bit [29] 128 UINT32 tee_io_supported : 1; // bit [30] 129 UINT32 rsvdp : 1; // bit [31] 130 } __attribute__((packed)) device_capabilities_t; 131 132 /* 133 * PCI Express Capability Structure 134 * CAPABILITY_ID = 0x10 135 * Device Control Register 136 * Offset: 0x8 137 */ 138 typedef struct { 139 UINT16 correctable_error_reporting_enable : 1; // bit [0] 140 UINT16 non_fatal_error_reporting_enable : 1; // bit [1] 141 UINT16 fatal_error_reporting_enable : 1; // bit [2] 142 UINT16 unsupported_request_reporting_enable : 1; // bit [3] 143 UINT16 enable_relaxed_ordering : 1; // bit [4] 144 UINT16 max_payload_size : 3; // bits [7:5] 145 UINT16 extended_tag_field_enable : 1; // bit [8] 146 UINT16 phantom_functions_enable : 1; // bit [9] 147 UINT16 aux_power_pm_enable : 1; // bit [10] 148 UINT16 enable_no_snoop : 1; // bit [11] 149 UINT16 max_read_request_size : 3; // bits [14:12] 150 UINT16 function_level_reset : 1; // bit [15] 151 } __attribute__((packed)) device_control_t; 152 153 /* 154 * PCI Express Capability Structure 155 * CAPABILITY_ID = 0x10 156 * Device Status Register 157 * Offset: 0xA 158 */ 159 typedef struct { 160 UINT16 correctable_error_detected : 1; // bit [0] 161 UINT16 non_fatal_error_detected : 1; // bit [1] 162 UINT16 fatal_error_detected : 1; // bit [2] 163 UINT16 unsupported_request_detected : 1; // bit [3] 164 UINT16 aux_power_detected : 1; // bit [4] 165 UINT16 transactions_pending : 1; // bit [5] 166 UINT16 emergency_power_reduction : 2; // bits [7:6] (PCIe 4.0+) 167 UINT16 rsvdz : 8; // bits [15:8] 168 } __attribute__((packed)) device_status_t; 169 170 /* 171 * PCI Express Capability Structure 172 * CAPABILITY_ID = 0x10 173 * Link Capabilities Register 174 * Offset: 0xC 175 */ 176 typedef struct { 177 UINT32 max_link_speed : 4; // bits [3:0] 178 UINT32 maximum_link_width : 6; // bits [9:4] 179 UINT32 aspm_support : 2; // bits [11:10] 180 UINT32 l0s_exit_latency : 3; // bits [14:12] 181 UINT32 l1_exit_latency : 3; // bits [17:15] 182 UINT32 clock_power_management : 1; // bit [18] 183 UINT32 surprise_down_error_reporting_capable : 1; // bit [19] 184 UINT32 data_link_layer_link_active_reporting_capable : 1; // bit [20] 185 UINT32 link_bandwidth_notification_capability : 1; // bit [21] 186 UINT32 aspm_optionality_compliance : 1; // bit [22] 187 UINT32 rsvdp : 1; // bit [23] 188 UINT32 port_number : 8; // bits [31:24] 189 } __attribute__((packed)) link_capabilities_t; 190 191 /* 192 * PCI Express Capability Structure 193 * CAPABILITY_ID = 0x10 194 * Link Control Register 195 * Offset: 0x10 196 */ 197 typedef struct { 198 UINT16 aspm_control : 2; // bits [1:0] 199 // ptm_propagation_delay_adaptation_interpretation_bit 200 UINT16 ptm_prop_delay_adaptation_interpretation : 1; // bit [2] 201 UINT16 read_completion_boundary : 1; // bit [3] 202 UINT16 link_disable : 1; // bit [4] 203 UINT16 retrain_link : 1; // bit [5] 204 UINT16 common_clock_configuration : 1; // bit [6] 205 UINT16 extended_synch : 1; // bit [7] 206 UINT16 enable_clock_power_management : 1; // bit [8] 207 UINT16 hardware_autonomous_width_disable : 1; // bit [9] 208 UINT16 link_bandwidth_management_interrupt_enable : 1; // bit [10] 209 UINT16 link_autonomous_bandwidth_interrupt_enable : 1; // bit [11] 210 UINT16 sris_clocking : 1; // bit [12] 211 UINT16 flit_mode_disable : 1; // bit [13] 212 UINT16 drs_signaling_control : 1; // bits [15:14] 213 } __attribute__((packed)) link_control_t; 214 215 /* 216 * PCI Express Capability Structure 217 * CAPABILITY_ID = 0x10 218 * Link Status Register 219 * Offset: 0x12 220 */ 221 typedef struct { 222 UINT16 current_link_speed : 4; // bits [3:0] 223 UINT16 negotiated_link_width : 6; // bits [9:4] 224 UINT16 undefined : 1; // bit [10] 225 UINT16 link_training : 1; // bit [11] 226 UINT16 slot_clock_configuration : 1; // bit [12] 227 UINT16 data_link_layer_link_active : 1; // bit [13] 228 UINT16 link_bandwidth_management_status : 1; // bit [14] 229 UINT16 link_autonomous_bandwidth_status : 1; // bit [15] 230 } __attribute__((packed)) link_status_t; 231 232 /* 233 * PCI Express Capability Structure 234 * CAPABILITY_ID = 0x10 235 * Slot Capabilities Register 236 * Offset: 0x14 237 */ 238 typedef struct { 239 UINT32 attention_button_present : 1; // bit [0] 240 UINT32 power_controller_present : 1; // bit [1] 241 UINT32 mrl_sensor_present : 1; // bit [2] 242 UINT32 attention_indicator_present : 1; // bit [3] 243 UINT32 power_indicator_present : 1; // bit [4] 244 UINT32 hot_plug_surprise : 1; // bit [5] 245 UINT32 hot_plug_capable : 1; // bit [6] 246 UINT32 slot_power_limit_value : 8; // bits [14:7] 247 UINT32 slot_power_limit_scale : 2; // bits [16:15] 248 UINT32 electromechanical_interlock_present : 1; // bit [17] 249 UINT32 no_command_completed_support : 1; // bit [18] 250 UINT32 physical_slot_number : 13; // bits [31:19] 251 } __attribute__((packed)) slot_capabilities_t; 252 253 /* 254 * PCI Express Capability Structure 255 * CAPABILITY_ID = 0x10 256 * Slot Control Register 257 * Offset: 0x18 258 */ 259 typedef struct { 260 UINT16 attention_button_pressed_enable : 1; // bit [0] 261 UINT16 power_fault_detected_enable : 1; // bit [1] 262 UINT16 mrl_sensor_changed_enable : 1; // bit [2] 263 UINT16 presence_detect_changed_enable : 1; // bit [3] 264 UINT16 command_completed_interrupt_enable : 1; // bit [4] 265 UINT16 hot_plug_interrupt_enable : 1; // bit [5] 266 UINT16 attention_indicator_control : 2; // bits [7:6] 267 UINT16 power_indicator_control : 2; // bits [9:8] 268 UINT16 power_controller_control : 1; // bit [10] 269 UINT16 electromechanical_interlock_control : 1; // bit [11] 270 UINT16 data_link_layer_state_changed_enable : 1; // bit [12] 271 UINT16 auto_slot_power_limit_disable : 1; // bit [13] 272 UINT16 in_band_pd_disable : 1; // bit [14] 273 UINT16 rsvdp : 1; // bit [15] 274 } __attribute__((packed)) slot_control_t; 275 276 /* 277 * PCI Express Capability Structure 278 * CAPABILITY_ID = 0x10 279 * Slot Status Register 280 * Offset: 0x1A 281 */ 282 typedef struct { 283 UINT16 attention_button_pressed : 1; // bit [0] 284 UINT16 power_fault_detected : 1; // bit [1] 285 UINT16 mrl_sensor_changed : 1; // bit [2] 286 UINT16 presence_detect_changed : 1; // bit [3] 287 UINT16 command_completed : 1; // bit [4] 288 UINT16 mrl_sensor_state : 1; // bit [5] 289 UINT16 presence_detect_state : 1; // bit [6] 290 UINT16 electromechanical_interlock_status : 1; // bit [7] 291 UINT16 data_link_layer_state_changed : 1; // bit [8] 292 UINT16 rsvdz : 7; // bits [15:9] 293 } __attribute__((packed)) slot_status_t; 294 295 /* 296 * PCI Express Capability Structure 297 * CAPABILITY_ID = 0x10 298 * Root Control Register 299 * Offset: 0x1C 300 */ 301 typedef struct { 302 UINT16 system_error_on_correctable_error_enable : 1; // bit [0] 303 UINT16 system_error_on_non_fatal_error_enable : 1; // bit [1] 304 UINT16 system_error_on_fatal_error_enable : 1; // bit [2] 305 UINT16 pme_interrupt_enable : 1; // bit [3] 306 UINT16 configuration_rrs_software_visibility_enable : 1; // bit [4] 307 UINT16 no_nfm_subtree_below_this_root_port : 1; // bit [5] 308 UINT16 rsvdp : 10; // bits [15:6] 309 } __attribute__((packed)) root_control_t; 310 311 /* 312 * PCI Express Capability Structure 313 * CAPABILITY_ID = 0x10 314 * Root Capabilities Register 315 * Offset: 0x1E 316 */ 317 typedef struct { 318 UINT16 configuraton_rrs_software_visibility : 1; // bit [0] 319 UINT16 rsvdp : 15; // bits [15:1] 320 } __attribute__((packed)) root_capabilities_t; 321 322 /* 323 * PCI Express Capability Structure 324 * CAPABILITY_ID = 0x10 325 * Root Status Register 326 * Offset: 0x20 327 */ 328 typedef struct { 329 UINT32 pme_requester_id : 16; // bits [15:0] 330 UINT32 pme_status : 1; // bit [16] 331 UINT32 pme_pending : 1; // bit [17] 332 UINT32 rsvdp : 14; // bits [31:18] 333 } __attribute__((packed)) root_status_t; 334 335 /* 336 * PCI Express Capability Structure 337 * CAPABILITY_ID = 0x10 338 * Device Capabilities 2 Register 339 * Offset: 0x24 340 */ 341 typedef struct { 342 UINT32 completion_timeout_ranges_supported : 4; // bits [3:0] 343 UINT32 completion_timeout_disable_supported : 1; // bit [4] 344 UINT32 ari_forwarding_supported : 1; // bit [5] 345 UINT32 atomic_op_routing_supported : 1; // bit [6] 346 UINT32 _32_bit_atomicop_completer_supported : 1; // bit [7] 347 UINT32 _64_bit_atomicop_completer_supported : 1; // bit [8] 348 UINT32 _128_bit_cas_completer_supported : 1; // bit [9] 349 UINT32 no_ro_enabled_pr_pr_passing : 1; // bit [10] 350 UINT32 ltr_mechanism_supported : 1; // bit [11] 351 UINT32 tph_completer_supported : 2; // bits [13:12] 352 UINT32 undefined : 2; // bit [15:14] 353 UINT32 _10_bit_tag_completer_supported : 1; // bit [16] 354 UINT32 _10_bit_tag_requester_supported : 1; // bit [17] 355 UINT32 obff_supported : 2; // bits [19:18] 356 UINT32 extended_fmt_field_supported : 1; // bit [20] 357 UINT32 end_end_tlp_prefix_supported : 1; // bit [21] 358 UINT32 max_end_end_tlp_prefixes : 2; // bits [23:22] 359 UINT32 emergency_power_reduction_supported : 2; // bits [25:24] 360 // emergency_power_reduction_initialization_required 361 UINT32 emergency_power_reduction_init_required : 1; // bit [26] 362 UINT32 rsvdp : 1; // bit [27] 363 UINT32 dmwr_completer_supported : 1; // bit [28] 364 UINT32 dmwr_lengths_supported : 2; // bits [30:29] 365 UINT32 frs_supported : 1; // bit [31] 366 } __attribute__((packed)) device_capabilities2_t; 367 368 /* 369 * PCI Express Capability Structure 370 * CAPABILITY_ID = 0x10 371 * Device Control 2 Register 372 * Offset: 0x28 373 */ 374 typedef struct { 375 UINT16 completion_timeout_value : 4; // bits [3:0] 376 UINT16 completion_timeout_disable : 1; // bit [4] 377 UINT16 ari_forwarding_enable : 1; // bit [5] 378 UINT16 atomicop_requester_enable : 1; // bit [6] 379 UINT16 atomicop_egress_blocking : 1; // bit [7] 380 UINT16 ido_request_enable : 1; // bit [8] 381 UINT16 ido_completion_enable : 1; // bit [9] 382 UINT16 ltr_mechanism_enable : 1; // bit [10] 383 UINT16 emergency_power_reduction_request : 1; // bit [11] 384 UINT16 bit_tag_requester_10_enable : 1; // bit [12] 385 UINT16 obff_enable : 2; // bits [14:13] 386 UINT16 end_end_tlp_prefix_blocking : 1; // bit [15] 387 } __attribute__((packed)) device_control2_t; 388 389 /* 390 * PCI Express Capability Structure 391 * CAPABILITY_ID = 0x10 392 * Device Status 2 Register 393 * Offset: 0x2A 394 */ 395 typedef struct { 396 UINT16 rsvdz : 16; // bits [15:0] 397 } __attribute__((packed)) device_status2_t; 398 399 /* 400 * PCI Express Capability Structure 401 * CAPABILITY_ID = 0x10 402 * Link Capabilities 2 Register 403 * Offset: 0x2C 404 */ 405 typedef struct { 406 UINT32 rsvdp : 1; // bit [0] 407 union { 408 struct { 409 UINT32 l_2_5g_supported : 1; 410 UINT32 l_5g_supported : 1; 411 UINT32 l_8g_supported : 1; 412 UINT32 l_16g_supported : 1; 413 UINT32 l_32g_supported : 1; 414 UINT32 reserved1 : 1; 415 UINT32 reserved2 : 1; 416 } __attribute__((packed)) supported_link_speeds; 417 UINT32 supported_link_speeds_register : 7; // bits [7:1] 418 }; 419 420 UINT32 crosslink_supported : 1; // bit [8] 421 UINT32 lower_skp_os_generation_supported : 7; // bit [15:9] 422 UINT32 lower_skp_os_reception_supported : 7; // bit [22:16] 423 UINT32 retimer_presence_detect_supported : 1; // bit [23] 424 UINT32 two_retimers_presence_detect_supported : 1; // bit [24] 425 UINT32 reserved : 6; // bits [30:25] 426 UINT32 drs_supported : 1; // bit [31] 427 } __attribute__((packed)) link_capabilities2_t; 428 429 /* 430 * PCI Express Capability Structure 431 * CAPABILITY_ID = 0x10 432 * Link Control 2 Register 433 * Offset: 0x30 434 */ 435 typedef struct { 436 UINT16 target_link_speed : 4; // bits [3:0] 437 UINT16 enter_compliance : 1; // bit [4] 438 UINT16 hardware_autonomous_speed_disable : 1; // bit [5] 439 UINT16 selectable_de_emphasis : 1; // bit [6] 440 UINT16 transmit_margin : 3; // bits [9:7] 441 UINT16 enter_modified_compliance : 1; // bit [10] 442 UINT16 compliance_sos : 1; // bit [11] 443 UINT16 compliance_preset_de_emphasis : 4; // bits [15:12] 444 } __attribute__((packed)) link_control2_t; 445 446 /* 447 * PCI Express Capability Structure 448 * CAPABILITY_ID = 0x10 449 * Link Status 2 Register 450 * Offset: 0x32 451 */ 452 typedef struct { 453 UINT16 current_de_emphasis_level : 1; // bit [0] 454 UINT16 equalization_8gts_complete : 1; // bit [1] 455 UINT16 equalization_8gts_phase1_successful : 1; // bit [2] 456 UINT16 equalization_8gts_phase2_successful : 1; // bit [3] 457 UINT16 equalization_8gts_phase3_successful : 1; // bit [4] 458 UINT16 link_equalization_request_8gts : 1; // bit [5] 459 UINT16 retimer_presence_detected : 1; // bit [6] 460 UINT16 two_retimers_presence_detected : 1; // bit [7] 461 UINT16 crosslink_resolution : 2; // bits [9:8] 462 UINT16 flit_mode_status : 1; // bit [10] 463 UINT16 rsvdz : 1; // bit [11] 464 UINT16 downstream_component_presence : 3; // bits [14:12] 465 UINT16 drs_message_received : 1; // bit [15] 466 } __attribute__((packed)) link_status2_t; 467 468 /* 469 * PCI Express Capability Structure 470 * CAPABILITY_ID = 0x10 471 * Slot Capabilities 2 Register 472 * Offset: 0x34 473 */ 474 typedef struct { 475 UINT32 rsvdp : 32; // bits [31:0] 476 } __attribute__((packed)) slot_capabilities2_t; 477 478 /* 479 * PCI Express Capability Structure 480 * CAPABILITY_ID = 0x10 481 * Slot Control 2 Register 482 * Offset: 0x38 483 */ 484 typedef struct { 485 UINT16 rsvdp : 16; // bits [15:0] 486 } __attribute__((packed)) slot_control2_t; 487 488 /* 489 * PCI Express Capability Structure 490 * CAPABILITY_ID = 0x10 491 * Slot Status 2 Register 492 * Offset: 0x3A 493 */ 494 typedef struct { 495 UINT16 rsvdp : 16; // bits [15:0] 496 } __attribute__((packed)) slot_status2_t; 497 498 /* 499 * End Of PCIe Capability Registers 500 */ 501 502 /* 503 * Begin Of AER Registers 504 */ 505 506 /* 507 * PCI Express Advanced Error Reporting Capability Structure 508 * CAPABILITY_ID = 0x01 509 * AER Capability Header 510 * Offset: 0x0 511 */ 512 typedef struct { 513 UINT16 capability_id : 16; // bits [15:0] 514 UINT16 capability_version : 4; // bits [19:16] 515 UINT16 next_capability_offset : 12; // bits [31:20] 516 } __attribute__((packed)) capability_header_t; 517 518 /* 519 * PCI Express Advanced Error Reporting Capability Structure 520 * CAPABILITY_ID = 0x01 521 * Uncorrectable Error Status Register 522 * Offset: 0x4 523 */ 524 typedef struct { 525 UINT32 undefined : 1; // bits [0] 526 UINT32 rsvdz1 : 3; // bits [3:1] 527 UINT32 data_link_protocol_error_status : 1; // bit [4] 528 UINT32 surprise_down_error_status : 1; // bit [5] 529 UINT32 rsvdz2 : 6; // bits [11:6] 530 UINT32 poisoned_tlp_received : 1; // bit [12] 531 UINT32 flow_control_protocol_error_status : 1; // bit [13] 532 UINT32 completion_timeout_status : 1; // bit [14] 533 UINT32 completer_abort_status : 1; // bit [15] 534 UINT32 unexpected_completion_status : 1; // bit [16] 535 UINT32 receiver_overflow_status : 1; // bit [17] 536 UINT32 malformed_tlp_status : 1; // bit [18] 537 UINT32 ecrc_error_status : 1; // bit [19] 538 UINT32 unsupported_request_error_status : 1; // bit [20] 539 UINT32 acs_violation_status : 1; // bit [21] 540 UINT32 uncorrectable_internal_error_status : 1; // bit [22] 541 UINT32 mc_blocked_tlp_status : 1; // bit [23] 542 UINT32 atomicop_egress_blocked_status : 1; // bit [24] 543 UINT32 tlp_prefix_blocked_error_status : 1; // bit [25] 544 UINT32 poisoned_tlp_egress_blocked_status : 1; // bit [26] 545 UINT32 dmwr_request_egress_blocked_status : 1; // bit [27] 546 UINT32 ide_check_failed_status : 1; // bit [28] 547 UINT32 misrouted_ide_tlp_status : 1; // bit [29] 548 UINT32 pcrc_check_failed_status : 1; // bit [30] 549 UINT32 tlp_translation_egress_blocked_status : 1; // bit [31] 550 } __attribute__((packed)) uncorrectable_error_status_t; 551 552 /* 553 * PCI Express Advanced Error Reporting Capability Structure 554 * CAPABILITY_ID = 0x01 555 * Uncorrectable Error Mask Register 556 * Offset: 0x8 557 */ 558 typedef struct { 559 UINT32 undefined : 1; // bits [0] 560 UINT32 rsvdz1 : 3; // bits [3:1] 561 UINT32 data_link_protocol_error_mask : 1; // bit [4] 562 UINT32 surprise_down_error_mask : 1; // bit [5] 563 UINT32 rsvdz2 : 6; // bits [11:6] 564 UINT32 poisoned_tlp_received_mask : 1; // bit [12] 565 UINT32 flow_control_protocol_error_mask : 1; // bit [13] 566 UINT32 completion_timeout_mask : 1; // bit [14] 567 UINT32 completer_abort_mask : 1; // bit [15] 568 UINT32 unexpected_completion_mask : 1; // bit [16] 569 UINT32 receiver_overflow_mask : 1; // bit [17] 570 UINT32 malformed_tlp_mask : 1; // bit [18] 571 UINT32 ecrc_error_mask : 1; // bit [19] 572 UINT32 unsupported_request_error_mask : 1; // bit [20] 573 UINT32 acs_violation_mask : 1; // bit [21] 574 UINT32 uncorrectable_internal_error_mask : 1; // bit [22] 575 UINT32 mc_blocked_tlp_mask : 1; // bit [23] 576 UINT32 atomicop_egress_blocked_mask : 1; // bit [24] 577 UINT32 tlp_prefix_blocked_error_mask : 1; // bit [25] 578 UINT32 poisoned_tlp_egress_blocked_mask : 1; // bit [26] 579 UINT32 dmwr_request_egress_blocked_mask : 1; // bit [27] 580 UINT32 ide_check_failed_mask : 1; // bit [28] 581 UINT32 misrouted_ide_tlp_mask : 1; // bit [29] 582 UINT32 pcrc_check_failed_mask : 1; // bit [30] 583 UINT32 tlp_translation_egress_blocked_mask : 1; // bit [31] 584 } __attribute__((packed)) uncorrectable_error_mask_t; 585 586 static const char *severity_dict[] = { 587 "NonFatal", // 0x0 588 "Fatal", // 0x1 589 }; 590 591 static const size_t severity_dict_size = 592 sizeof(severity_dict) / sizeof(severity_dict[0]); 593 594 static const char *supported_dict[] = { 595 "NotSupported", // 0x0 596 "Supported", // 0x1 597 }; 598 599 static const size_t supported_dict_size = 600 sizeof(severity_dict) / sizeof(severity_dict[0]); 601 602 static const char *enabled_dict[] = { 603 "Disabled", // 0x0 604 "Enabled", // 0x1 605 }; 606 607 static const size_t enabled_dict_size = 608 sizeof(enabled_dict) / sizeof(enabled_dict[0]); 609 610 static const char *passing_dict[] = { 611 "Failed", // 0x0 612 "Passing", // 0x1 613 }; 614 615 static const size_t passing_dict_size = 616 sizeof(passing_dict) / sizeof(passing_dict[0]); 617 618 /* 619 * PCI Express Advanced Error Reporting Capability Structure 620 * CAPABILITY_ID = 0x01 621 * Uncorrectable Error Severity Register 622 * Offset: 0xC 623 */ 624 typedef struct { 625 UINT32 undefined : 1; // bits [0] 626 UINT32 rsvdz1 : 3; // bits [3:1] 627 UINT32 data_link_protocol_error_severity : 1; // bit [4] 628 UINT32 surprise_down_error_severity : 1; // bit [5] 629 UINT32 rsvdz2 : 6; // bits [11:6] 630 UINT32 poisoned_tlp_received_severity : 1; // bit [12] 631 UINT32 flow_control_protocol_error_severity : 1; // bit [13] 632 UINT32 completion_timeout_severity : 1; // bit [14] 633 UINT32 completer_abort_severity : 1; // bit [15] 634 UINT32 unexpected_completion_severity : 1; // bit [16] 635 UINT32 receiver_overflow_severity : 1; // bit [17] 636 UINT32 malformed_tlp_severity : 1; // bit [18] 637 UINT32 ecrc_error_severity : 1; // bit [19] 638 UINT32 unsupported_request_error_severity : 1; // bit [20] 639 UINT32 acs_violation_severity : 1; // bit [21] 640 UINT32 uncorrectable_internal_error_severity : 1; // bit [22] 641 UINT32 mc_blocked_tlp_severity : 1; // bit [23] 642 UINT32 atomicop_egress_blocked_severity : 1; // bit [24] 643 UINT32 tlp_prefix_blocked_error_severity : 1; // bit [25] 644 UINT32 poisoned_tlp_egress_blocked_severity : 1; // bit [26] 645 UINT32 dmwr_request_egress_blocked_severity : 1; // bit [27] 646 UINT32 ide_check_failed_severity : 1; // bit [28] 647 UINT32 misrouted_ide_tlp_severity : 1; // bit [29] 648 UINT32 pcrc_check_failed_severity : 1; // bit [30] 649 UINT32 tlp_translation_egress_blocked_severity : 1; // bit [31] 650 } __attribute__((packed)) uncorrectable_error_severity_t; 651 652 /* 653 * PCI Express Advanced Error Reporting Capability Structure 654 * CAPABILITY_ID = 0x01 655 * Correctable Error Status Register 656 * Offset: 0x10 657 */ 658 typedef struct { 659 UINT32 receiver_error_status : 1; // bit [0] 660 UINT32 rsvdz1 : 5; // bits [5:1] 661 UINT32 bad_tlp_status : 1; // bit [6] 662 UINT32 bad_dllp_status : 1; // bit [7] 663 UINT32 replay_num_rollover_status : 1; // bit [8] 664 UINT32 rsvdz2 : 3; // bits [11:9] 665 UINT32 replay_timer_timeout_status : 1; // bit [12] 666 UINT32 advisory_non_fatal_error_status : 1; // bit [13] 667 UINT32 corrected_internal_error_status : 1; // bit [14] 668 UINT32 header_log_overflow_status : 1; // bit [15] 669 UINT32 rsvdz3 : 16; // bits [31:16] 670 } __attribute__((packed)) correctable_error_status_t; 671 672 /* 673 * PCI Express Advanced Error Reporting Capability Structure 674 * CAPABILITY_ID = 0x01 675 * Correctable Error Mask Register 676 * Offset: 0x14 677 */ 678 typedef struct { 679 UINT32 receiver_error_mask : 1; // bit [0] 680 UINT32 rsvdz1 : 5; // bits [5:1] 681 UINT32 bad_tlp_mask : 1; // bit [6] 682 UINT32 bad_dllp_mask : 1; // bit [7] 683 UINT32 replay_num_rollover_mask : 1; // bit [8] 684 UINT32 rsvdz2 : 3; // bits [11:9] 685 UINT32 replay_timer_timeout_mask : 1; // bit [12] 686 UINT32 advisory_non_fatal_error_mask : 1; // bit [13] 687 UINT32 corrected_internal_error_mask : 1; // bit [14] 688 UINT32 header_log_overflow_mask : 1; // bit [15] 689 UINT32 rsvdz3 : 16; // bits [31:16] 690 } __attribute__((packed)) correctable_error_mask_t; 691 692 /* 693 * PCI Express Advanced Error Reporting Capability Structure 694 * CAPABILITY_ID = 0x01 695 * Advanced Error Capabilities and Control Register 696 * Offset: 0x18 697 */ 698 typedef struct { 699 UINT32 first_error_pointer : 5; // bits [4:0] 700 UINT32 ecrc_generation_capable : 1; // bit [5] 701 UINT32 ecrc_generation_enable : 1; // bit [6] 702 UINT32 ecrc_check_capable : 1; // bit [7] 703 UINT32 ecrc_check_enable : 1; // bit [8] 704 UINT32 multiple_header_recording_capable : 1; // bit [9] 705 UINT32 multiple_header_recording_enable : 1; // bit [10] 706 UINT32 tlp_prefix_log_present : 1; // bit [11] 707 UINT32 completion_timeout_prefix_header_log_capable : 1; // bit [12] 708 UINT32 header_log_size : 5; // bits [17:13] 709 UINT32 logged_tlp_was_flit_mode : 1; // bit [18] 710 UINT32 logged_tlp_size : 5; // bits [23:19] 711 UINT32 rsvdp : 8; // bits [31:24] 712 } __attribute__((packed)) advanced_error_capabilities_and_control_t; 713 714 /* 715 * PCI Express Advanced Error Reporting Capability Structure 716 * CAPABILITY_ID = 0x01 717 * Root Error Command Register 718 * Offset: 0x2C 719 */ 720 typedef struct { 721 UINT32 correctable_error_reporting_enable : 1; // bit [0] 722 UINT32 non_fatal_error_reporting_enable : 1; // bit [1] 723 UINT32 fatal_error_reporting_enable : 1; // bit [2] 724 UINT32 rsvdp : 29; // bits [31:3] 725 } __attribute__((packed)) root_error_command_t; 726 727 /* 728 * PCI Express Advanced Error Reporting Capability Structure 729 * CAPABILITY_ID = 0x01 730 * Root Error Status Register 731 * Offset: 0x30 732 */ 733 typedef struct { 734 UINT32 err_cor_received : 1; // bit [0] 735 UINT32 multiple_err_cor_received : 1; // bit [1] 736 UINT32 err_fatal_nonfatal_received : 1; // bit [2] 737 UINT32 multiple_err_fatal_nonfatal_received : 1; // bit [3] 738 UINT32 first_uncorrectable_fatal : 1; // bit [4] 739 UINT32 non_fatal_error_messages_received : 1; // bit [5] 740 UINT32 fatal_error_messages_received : 1; // bit [6] 741 UINT32 err_cor_subclass : 2; // bit [8:7] 742 UINT32 rsvdz : 16; // bit [9:26] 743 UINT32 advanced_error_interrupt_message_number : 5; // bits [31:27] 744 } __attribute__((packed)) root_error_status_t; 745 746 /* 747 * PCI Express Advanced Error Reporting Capability Structure 748 * CAPABILITY_ID = 0x01 749 * Error Source Identification Register 750 * Offset: 0x34 751 */ 752 typedef struct { 753 UINT32 err_cor_source_identification : 16; // bits [15:0] 754 UINT32 err_fatal_nonfatal_source_identification : 16; // bits [31:16] 755 } __attribute__((packed)) error_source_id_t; 756 757 typedef struct { 758 pcie_capability_header_t pcie_capability_header; 759 pcie_capabilities_t pcie_capabilities; 760 device_capabilities_t device_capabilities; 761 device_control_t device_control; 762 device_status_t device_status; 763 link_capabilities_t link_capabilities; 764 link_control_t link_control; 765 link_status_t link_status; 766 slot_capabilities_t slot_capabilities; 767 slot_control_t slot_control; 768 slot_status_t slot_status; 769 root_control_t root_control; 770 root_capabilities_t root_capabilities; 771 root_status_t root_status; 772 // "2" postfixed only valid when pcie_capabilities_fields.cap_version >= 2 773 device_capabilities2_t device_capabilities2; 774 device_control2_t device_control2; 775 device_status2_t device_status2; 776 link_capabilities2_t link_capabilities2; 777 link_control2_t link_control2; 778 link_status2_t link_status2; 779 slot_capabilities2_t slot_capabilities2; 780 slot_control2_t slot_control2; 781 slot_status2_t slot_status2; 782 } __attribute__((packed)) capability_registers; 783 784 typedef struct { 785 capability_header_t capability_header; 786 uncorrectable_error_status_t uncorrectable_error_status; 787 uncorrectable_error_mask_t uncorrectable_error_mask; 788 uncorrectable_error_severity_t uncorrectable_error_severity; 789 correctable_error_status_t correctable_error_status; 790 correctable_error_mask_t correctable_error_mask; 791 advanced_error_capabilities_and_control_t 792 advanced_error_capabilities_and_control; 793 UINT32 tlp_header[4]; 794 root_error_command_t root_error_command; 795 root_error_status_t root_error_status; 796 error_source_id_t error_source_id; 797 union { 798 struct { // Non-flit mode TLP prefix logs 799 UINT32 log[4]; 800 } non_flit_logs; 801 struct { // Flit mode TLP header logs 802 UINT32 header[10]; 803 } flit_tlp_header_logs; 804 } tlp_pfrefix; 805 } __attribute__((packed)) aer_info_registers; 806 807 #ifdef __cplusplus 808 } 809 #endif 810 811 #endif 812