Searched refs:postdiv (Results 1 – 6 of 6) sorted by relevance
| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mtk.c | 83 u32 fin, u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
103 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
112 static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) in mtk_pll_set_rate_regs() argument
121 val |= (ffs(postdiv) - 1) << pll->pd_shift; in mtk_pll_set_rate_regs()
148 static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
161 *postdiv = 1 << val; in mtk_pll_calc_values()
162 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
176 u32 postdiv; in mtk_apmixedsys_set_rate() local
178 mtk_pll_calc_values(clk, &pcw, &postdiv, rate); in mtk_apmixedsys_set_rate()
179 mtk_pll_set_rate_regs(clk, pcw, postdiv); in mtk_apmixedsys_set_rate()
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| /openbmc/u-boot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen3.c | 163 u32 value, mult, div, prediv, postdiv; in gen3_clk_get_rate64() local
302 postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) & in gen3_clk_get_rate64()
304 rate /= postdiv + 1; in gen3_clk_get_rate64()
308 core->parent, prediv, postdiv, rate); in gen3_clk_get_rate64()
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| /openbmc/u-boot/arch/arm/mach-davinci/include/mach/ |
| H A D | pll_defs.h | 24 unsigned int postdiv; /* 0x128 */ member
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| H A D | hardware.h | 406 dv_reg postdiv; member
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| /openbmc/u-boot/arch/arm/mach-davinci/ |
| H A D | da850_lowlevel.c | 94 ®->postdiv); in da850_pll_init()
97 ®->postdiv); in da850_pll_init()
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| H A D | dm365_lowlevel.c | 71 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); in dm365_pll1_init()
141 writel(PLL_POSTDEN, &dv_pll1_regs->postdiv); in dm365_pll2_init()
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