/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_pll.c | 92 ref_div_max = min(100 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div() 135 unsigned post_div_min, post_div_max, post_div; in amdgpu_pll_compute() local 163 post_div_min = pll->post_div; in amdgpu_pll_compute() 164 post_div_max = pll->post_div; in amdgpu_pll_compute() 208 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in amdgpu_pll_compute() 213 (ref_div * post_div)); in amdgpu_pll_compute() 218 post_div_best = post_div; in amdgpu_pll_compute() 222 post_div = post_div_best; in amdgpu_pll_compute() 253 (ref_div * post_div * 10); in amdgpu_pll_compute() 255 *post_div_p = post_div; in amdgpu_pll_compute() [all …]
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H A D | atombios_crtc.c | 584 u32 post_div, in amdgpu_atombios_crtc_program_pll() argument 611 args.v1.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 621 args.v2.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 631 args.v3.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 648 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 678 args.v6.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 825 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local 851 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll() 854 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll() 861 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
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H A D | amdgpu_atombios.h | 28 u32 post_div; member 68 u32 post_div; member
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H A D | atombios_crtc.h | 51 u32 post_div,
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/openbmc/u-boot/drivers/clk/aspeed/ |
H A D | clk_ast2500.c | 49 unsigned int post_div; member 70 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) in ast2500_get_mpll_rate() local 73 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_mpll_rate() 89 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) in ast2500_get_hpll_rate() local 107 const ulong post_div = (dpll_reg >> 13) & 0x3f; in ast2500_get_dpll_rate() local 124 const ulong post_div = (d2pll_reg >> 13) & 0x3f; in ast2500_get_d2pll_rate() local 302 for (it.post_div = 0; it.post_div <= max_vals.post_div; in ast2500_calc_clock_config() 303 ++it.post_div) { in ast2500_calc_clock_config() 311 / (it.post_div + 1); in ast2500_calc_clock_config() 344 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) in ast2500_configure_ddr() [all …]
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H A D | clk_ast2400.c | 32 unsigned int post_div; member 275 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, 328 for (it.post_div = 0; it.post_div <= max_vals.post_div; in ast2400_calc_clock_config() 329 ++it.post_div) { in ast2400_calc_clock_config() 330 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) in ast2400_calc_clock_config() 337 / (it.post_div + 1); in ast2400_calc_clock_config() 362 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), in ast2400_configure_ddr() 370 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) in ast2400_configure_ddr()
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | radeon_clocks.c | 59 if (post_div == 2) in radeon_legacy_get_engine_clock() 61 else if (post_div == 3) in radeon_legacy_get_engine_clock() 63 else if (post_div == 4) in radeon_legacy_get_engine_clock() 89 if (post_div == 2) in radeon_legacy_get_memory_clock() 91 else if (post_div == 3) in radeon_legacy_get_memory_clock() 93 else if (post_div == 4) in radeon_legacy_get_memory_clock() 364 *post_div = 8; in calc_eng_mem_clock() 367 *post_div = 4; in calc_eng_mem_clock() 370 *post_div = 2; in calc_eng_mem_clock() 373 *post_div = 1; in calc_eng_mem_clock() [all …]
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H A D | radeon_display.c | 1050 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in radeon_compute_pll_avivo() 1055 (ref_div * post_div)); in radeon_compute_pll_avivo() 1064 post_div = post_div_best; in radeon_compute_pll_avivo() 1097 *post_div_p = post_div; in radeon_compute_pll_avivo() 1135 uint32_t post_div; in radeon_compute_pll_legacy() local 1175 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { in radeon_compute_pll_legacy() 1183 if ((post_div == 5) || in radeon_compute_pll_legacy() 1184 (post_div == 7) || in radeon_compute_pll_legacy() 1185 (post_div == 9) || in radeon_compute_pll_legacy() 1186 (post_div == 10) || in radeon_compute_pll_legacy() [all …]
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H A D | radeon_legacy_tv.c | 857 int post_div; in get_post_div() local 859 case 1: post_div = 0; break; in get_post_div() 860 case 2: post_div = 1; break; in get_post_div() 861 case 3: post_div = 4; break; in get_post_div() 862 case 4: post_div = 2; break; in get_post_div() 863 case 6: post_div = 6; break; in get_post_div() 864 case 8: post_div = 3; break; in get_post_div() 865 case 12: post_div = 7; break; in get_post_div() 867 default: post_div = 5; break; in get_post_div() 869 return post_div; in get_post_div()
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H A D | rv730_dpm.c | 62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value() 63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value() 78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value() 79 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value() 140 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value() 141 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value() 153 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_mclk_value() 154 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_mclk_value()
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H A D | rv740_dpm.c | 142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value() 148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value() 159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value() 216 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value() 233 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value() 246 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
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H A D | radeon_uvd.c | 912 unsigned post_div = vco_freq / target_freq; in radeon_uvd_calc_upll_post_div() local 915 if (post_div < pd_min) in radeon_uvd_calc_upll_post_div() 916 post_div = pd_min; in radeon_uvd_calc_upll_post_div() 919 if ((vco_freq / post_div) > target_freq) in radeon_uvd_calc_upll_post_div() 920 post_div += 1; in radeon_uvd_calc_upll_post_div() 923 if (post_div > pd_even && post_div % 2) in radeon_uvd_calc_upll_post_div() 924 post_div += 1; in radeon_uvd_calc_upll_post_div() 926 return post_div; in radeon_uvd_calc_upll_post_div()
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H A D | radeon_legacy_crtc.c | 756 } *post_div, post_divs[] = { in radeon_set_pll() local 822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll() 823 if (post_div->divider == post_divider) in radeon_set_pll() 827 if (!post_div->divider) in radeon_set_pll() 828 post_div = &post_divs[0]; in radeon_set_pll() 843 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
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H A D | rs780_dpm.c | 89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state() 454 (min_dividers.post_div != max_dividers.post_div) || in rs780_set_engine_clock_scaling() 456 (max_dividers.post_div != current_max_dividers.post_div)) in rs780_set_engine_clock_scaling() 989 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_debugfs_print_current_performance_level() local 992 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level() 1011 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_get_current_sclk() local 1014 (post_div * ref_div); in rs780_dpm_get_current_sclk()
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H A D | atombios_crtc.c | 824 u32 post_div, in atombios_crtc_program_pll() argument 851 args.v1.ucPostDiv = post_div; in atombios_crtc_program_pll() 861 args.v2.ucPostDiv = post_div; in atombios_crtc_program_pll() 871 args.v3.ucPostDiv = post_div; in atombios_crtc_program_pll() 888 args.v5.ucPostDiv = post_div; in atombios_crtc_program_pll() 917 args.v6.ucPostDiv = post_div; in atombios_crtc_program_pll() 1089 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll() 1094 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll() 1097 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll() 1100 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll() [all …]
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/openbmc/u-boot/drivers/spi/ |
H A D | mxc_spi.c | 135 u32 pre_div = 0, post_div = 0; in spi_cfg_mxc() local 153 post_div = fls(pre_div); in spi_cfg_mxc() 154 if (post_div > 4) { in spi_cfg_mxc() 155 post_div -= 4; in spi_cfg_mxc() 156 if (post_div >= 16) { in spi_cfg_mxc() 161 pre_div >>= post_div; in spi_cfg_mxc() 163 post_div = 0; in spi_cfg_mxc() 167 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); in spi_cfg_mxc() 173 MXC_CSPICTRL_POSTDIV(post_div); in spi_cfg_mxc()
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/openbmc/u-boot/arch/arm/mach-davinci/ |
H A D | cpu.c | 58 int post_div; in clk_get() local 88 post_div = (readl(pll_base + PLLC_POSTDIV) & in clk_get() 91 pll_out /= post_div; in clk_get()
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/openbmc/u-boot/arch/arm/mach-imx/mx6/ |
H A D | clock.c | 552 u32 post_div) in enable_pll_video() argument 568 switch (post_div) { in enable_pll_video() 626 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local 663 for (post_div = 2; post_div <= 4; post_div <<= 1) { in mxs_set_lcdclk() 664 if ((temp * post_div) > min) { in mxs_set_lcdclk() 665 freq *= post_div; in mxs_set_lcdclk() 670 if (post_div > 4) { in mxs_set_lcdclk() 710 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk() 747 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
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/openbmc/u-boot/arch/arm/mach-imx/mx7/ |
H A D | clock.c | 474 enum root_post_div post_div; in get_ddrc_clk() local 484 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK; in get_ddrc_clk() 486 return freq / (post_div + 1) / 2; in get_ddrc_clk() 776 u32 post_div) in enable_pll_video() argument 794 switch (post_div) { in enable_pll_video() 898 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local 909 post_div = i; in mxs_set_lcdclk() 946 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
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H A D | clock_slice.c | 672 enum root_post_div post_div, enum clk_root_src clock_src) in clock_root_cfg() argument 698 if (post_div > CLK_ROOT_POST_DIV7) { in clock_root_cfg() 705 if (post_div != CLK_ROOT_POST_DIV1) { in clock_root_cfg() 716 post_div << CLK_ROOT_POST_DIV_SHIFT | in clock_root_cfg()
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/openbmc/linux/drivers/clk/ |
H A D | clk-stm32f4.c | 1764 post_div = &post_div_data[n]; in stm32f4_rcc_init() 1767 post_div->parent, in stm32f4_rcc_init() 1768 post_div->flag, in stm32f4_rcc_init() 1769 base + post_div->offset, in stm32f4_rcc_init() 1770 post_div->shift, in stm32f4_rcc_init() 1771 post_div->width, in stm32f4_rcc_init() 1772 post_div->flag_div, in stm32f4_rcc_init() 1773 post_div->div_table, in stm32f4_rcc_init() 1774 clks[post_div->pll_idx], in stm32f4_rcc_init() 1777 if (post_div->idx != NO_IDX) in stm32f4_rcc_init() [all …]
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | mcp77.c | 55 u32 post_div = 0; in read_pll() local 61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll() 64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll() 74 clock = clock / post_div; in read_pll()
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/openbmc/u-boot/board/gdsys/common/ |
H A D | osd.c | 80 unsigned int *post_div, unsigned int *feedback_div) in mpc92469ac_calc_parameters() argument 82 unsigned int n = *post_div; in mpc92469ac_calc_parameters() 100 *post_div = n; in mpc92469ac_calc_parameters()
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/openbmc/linux/drivers/video/fbdev/aty/ |
H A D | radeon_base.c | 1527 } *post_div, in radeon_calc_pll_regs() local 1596 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs() 1597 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs() 1601 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs() 1610 if ( !post_div->divider ) { in radeon_calc_pll_regs() 1611 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs() 1612 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs() 1620 if ( !post_div->divider ) { in radeon_calc_pll_regs() 1621 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs() 1622 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs() [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx7/ |
H A D | clock_slice.h | 111 enum root_post_div post_div, enum clk_root_src clock_src);
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