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Searched refs:pmic_clrsetbits (Results 1 – 25 of 26) sorted by relevance

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/openbmc/u-boot/board/st/stm32mp1/
H A Dboard.c67 ret = pmic_clrsetbits(dev, in board_ddr_power_init()
75 ret = pmic_clrsetbits(dev, in board_ddr_power_init()
83 ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG, in board_ddr_power_init()
91 ret = pmic_clrsetbits(dev, in board_ddr_power_init()
H A Dspl.c27 pmic_clrsetbits(dev, in spl_board_init()
/openbmc/u-boot/board/freescale/mx6sllevk/
H A Dmx6sllevk.c78 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); in power_init_board()
81 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); in power_init_board()
84 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); in power_init_board()
87 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); in power_init_board()
/openbmc/u-boot/drivers/power/regulator/
H A Drk8xx.c113 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); in _buck_set_value()
124 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 0, 3 << (buck * 2)); in _buck_set_enable()
127 ret = pmic_clrsetbits(pmic, REG_DCDC_UV_ACT, 1 << buck, 0); in _buck_set_enable()
132 return pmic_clrsetbits(pmic, REG_DCDC_EN, mask, enable ? mask : 0); in _buck_set_enable()
224 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); in ldo_set_value()
234 return pmic_clrsetbits(dev->parent, REG_LDO_EN, mask, in ldo_set_enable()
260 return pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, in switch_set_enable()
375 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); in rk818_spl_configure_usb_input_current()
386 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, in rk818_spl_configure_usb_chrg_shutdown()
H A Dstpmu1.c165 return pmic_clrsetbits(dev->parent, in stpmu1_buck_set_value()
201 ret = pmic_clrsetbits(dev->parent, in stpmu1_buck_set_enable()
224 return pmic_clrsetbits(dev->parent, in stpmu1_buck_set_mode()
344 return pmic_clrsetbits(dev->parent, in stpmu1_ldo_set_value()
380 ret = pmic_clrsetbits(dev->parent, in stpmu1_ldo_set_enable()
502 ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG, in stpmu1_vref_ddr_set_enable()
564 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, in stpmu1_boost_set_enable()
630 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, in stpmu1_pwr_sw_set_enable()
635 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, in stpmu1_pwr_sw_set_enable()
639 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, in stpmu1_pwr_sw_set_enable()
H A Dact8846.c106 return pmic_clrsetbits(dev->parent, addr_vol[reg], LDO_VOL_MASK, val); in reg_set_value()
113 return pmic_clrsetbits(dev->parent, addr_ctl[reg], LDO_EN_MASK, in reg_set_enable()
H A Das3722_regulator.c34 ret = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd); in stepdown_set_enable()
82 ret = pmic_clrsetbits(pmic, ctrl_reg, !enable << ldo, enable << ldo); in ldo_set_enable()
H A Dpfuze100.c363 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_mode()
367 val = pmic_clrsetbits(dev->parent, in pfuze100_regulator_mode()
373 val = pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_mode()
494 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_val()
501 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_val()
H A Ds5m8767.c124 ret = pmic_clrsetbits(dev->parent, param->vol_addr, in reg_set_value()
179 ret = pmic_clrsetbits(dev->parent, param->reg_enaddr, in reg_set_enable()
H A Dfan53555.c145 return pmic_clrsetbits(dev, pdata->vol_reg, GENMASK(6, 0), vol); in fan53555_regulator_set_value()
/openbmc/u-boot/board/k+p/kp_imx53/
H A Dkp_imx53.c113 pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708, in power_init()
117 pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708, in power_init()
121 pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708, in power_init()
/openbmc/u-boot/board/freescale/mx6sxsabreauto/
H A Dmx6sxsabreauto.c156 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); in power_init_board()
159 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); in power_init_board()
162 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); in power_init_board()
165 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); in power_init_board()
/openbmc/u-boot/drivers/power/pmic/
H A Dmc34708.c75 pmic_clrsetbits(dev, MC34708_REG_SW12_OPMODE, in mc34708_probe()
79 pmic_clrsetbits(dev, MC34708_REG_SW345_OPMODE, in mc34708_probe()
H A Ds5m8767.c49 return pmic_clrsetbits(dev, S5M8767_EN32KHZ_CP, 0, 1 << 1); in s5m8767_enable_32khz_cp()
H A Dpmic_tps65910_dm.c73 return pmic_clrsetbits(dev, TPS65910_REG_DEVICE_CTRL, 0, in pmic_tps65910_probe()
H A Dpmic-uclass.c167 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) in pmic_clrsetbits() function
/openbmc/u-boot/board/samsung/common/
H A Dexynos5-dt.c72 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0, in exynos_power_init()
76 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0, in exynos_power_init()
/openbmc/u-boot/board/freescale/mx6slevk/
H A Dmx6slevk.c183 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); in power_init_board()
186 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); in power_init_board()
189 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); in power_init_board()
192 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); in power_init_board()
/openbmc/u-boot/drivers/gpio/
H A Dpm8916_gpio.c61 ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, in pm8916_gpio_set_direction()
99 return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0, in pm8916_gpio_set_direction()
156 return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL, in pm8916_gpio_set_value()
/openbmc/u-boot/board/toradex/apalis-tk1/
H A Dapalis-tk1.c78 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd); in as3722_sd_enable()
101 err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo); in as3722_ldo_enable()
/openbmc/u-boot/board/toradex/colibri_imx7/
H A Dcolibri_imx7.c286 pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); in power_init_board()
294 pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); in power_init_board()
302 pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); in power_init_board()
/openbmc/u-boot/board/nvidia/jetson-tk1/
H A Djetson-tk1.c47 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd); in as3722_sd_enable()
/openbmc/u-boot/board/freescale/mx7dsabresd/
H A Dmx7dsabresd.c338 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); in power_init_board()
344 pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); in power_init_board()
/openbmc/u-boot/test/dm/
H A Dpmic.c123 pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9); in dm_test_power_pmic_mc34708_rw_val()
/openbmc/u-boot/include/power/
H A Dpmic.h298 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set);

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