Searched refs:pllckselr (Results 1 – 1 of 1) sorted by relevance
130 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */ member350 uint32_t pllckselr = 0; in configure_clocks() local393 pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE; in configure_clocks()394 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; in configure_clocks()395 writel(pllckselr, ®s->pllckselr); in configure_clocks()505 switch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) { in stm32_get_PLL1_rate()527 divm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK; in stm32_get_PLL1_rate()