Searched refs:pllc0 (Results 1 – 3 of 3) sorted by relevance
74 writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); in cm_basic_init()96 writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); in cm_basic_init()244 clock /= (readl(&clock_manager_base->main_pll.pllc0) & in cm_get_mpu_clk_hz()250 clock /= (readl(&clock_manager_base->per_pll.pllc0) & in cm_get_mpu_clk_hz()
94 u32 pllc0; member121 u32 pllc0; member
484 clock-output-names = "system", "pllc0", "pllc1",