| /openbmc/linux/arch/arm/boot/dts/vt8500/ |
| H A D | wm8650.dtsi | 85 plla: plla { label
123 clocks = <&plla>;
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| H A D | wm8850.dtsi | 88 plla: plla { label
140 clocks = <&plla>;
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| H A D | wm8505.dtsi | 88 plla: plla { label
119 clocks = <&plla>;
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| H A D | wm8750.dtsi | 91 plla: plla { label
129 clocks = <&plla>;
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | vt8500.txt | 59 plla: plla {
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| H A D | renesas,cpg-clocks.yaml | 138 - const: plla
158 - const: plla
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| /openbmc/u-boot/drivers/clk/at91/ |
| H A D | Makefile | 6 obj-y += clk-slow.o clk-main.o clk-plla.o clk-plladiv.o clk-master.o
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | at91sam9g20.dtsi | 43 plla: pllack@0 { label
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| H A D | sama5d2.dtsi | 93 plla: pllack@0 { label
107 clocks = <&plla>;
532 clocks = <&main>, <&plla>, <&utmi>, <&mck>;
|
| H A D | at91sam9261.dtsi | 601 plla: pllack@0 { label
628 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
646 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
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| H A D | at91sam9260.dtsi | 138 plla: pllack@0 { label
165 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
183 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
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| H A D | at91sam9rl.dtsi | 838 plla: pllack@0 { label
862 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
873 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
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| H A D | at91sam9263.dtsi | 118 plla: pllack@0 { label
146 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
164 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
| H A D | at91sam9n12.dtsi | 131 plla: pllack@0 { label
152 clocks = <&plla>;
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| H A D | at91sam9x5.dtsi | 140 plla: pllack@0 { label
161 clocks = <&plla>;
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| H A D | at91sam9g45.dtsi | 138 plla: pllack@0 { label
159 clocks = <&plla>;
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| H A D | sama5d3.dtsi | 973 plla: pllack@0 { label
988 clocks = <&plla>;
|
| H A D | sama5d4.dtsi | 407 plla: pllack@0 { label
422 clocks = <&plla>;
|
| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra210.c | 831 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) in tegra210_plla_set_defaults() argument
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
836 plla->params->defaults_set = true; in tegra210_plla_set_defaults()
845 plla->params->defaults_set = false; in tegra210_plla_set_defaults()
852 _pll_misc_chk_default(clk_base, plla->params, 0, val, in tegra210_plla_set_defaults()
856 _pll_misc_chk_default(clk_base, plla->params, 2, val, in tegra210_plla_set_defaults()
860 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
863 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
871 writel_relaxed(val, clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
873 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
[all …]
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| /openbmc/linux/arch/arm/boot/dts/renesas/ |
| H A D | r8a7778.dtsi | 496 clock-output-names = "plla", "pllb", "b",
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| H A D | r8a7779.dtsi | 580 clock-output-names = "plla", "z", "zs", "s",
|