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Searched refs:pll_set (Results 1 – 19 of 19) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk-hsdk-cgu.c271 static ulong pll_set(struct clk *, ulong);
285 { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
287 { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
288 { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
305 { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
309 { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
477 static ulong pll_set(struct clk *sclk, ulong rate) in pll_set() function
528 ret = pll_set(sclk, rate); in cpu_clk_set()
558 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
568 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv1a.c34 .pll_set = nv04_devinit_pll_set,
H A Dpriv.h14 int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq); member
H A Dgm107.c49 .pll_set = gf100_devinit_pll_set,
H A Dg98.c55 .pll_set = nv50_devinit_pll_set,
H A Dmcp89.c56 .pll_set = gt215_devinit_pll_set,
H A Dg84.c56 .pll_set = nv50_devinit_pll_set,
H A Dnv20.c71 .pll_set = nv04_devinit_pll_set,
H A Dga100.c69 .pll_set = ga100_devinit_pll_set,
H A Dgv100.c70 .pll_set = gv100_devinit_pll_set,
H A Dnv10.c105 .pll_set = nv04_devinit_pll_set,
H A Dtu102.c103 .pll_set = tu102_devinit_pll_set,
H A Dgf100.c109 .pll_set = gf100_devinit_pll_set,
H A Dbase.c40 return init->func->pll_set(init, type, khz); in nvkm_devinit_pll_set()
H A Dgt215.c141 .pll_set = gt215_devinit_pll_set,
H A Dnv05.c135 .pll_set = nv04_devinit_pll_set,
H A Dnv50.c166 .pll_set = nv50_devinit_pll_set,
H A Dgm200.c183 .pll_set = gf100_devinit_pll_set,
H A Dnv04.c457 .pll_set = nv04_devinit_pll_set,