Searched refs:pll_rates (Results 1 – 2 of 2) sorted by relevance
50 unsigned int pll_rates[2]; member81 u32 pll_rates[2]; member181 if (!(rate % 8000) && priv->pll_rates[J721E_CLK_PARENT_48000]) in j721e_configure_refclk()183 else if (!(rate % 11025) && priv->pll_rates[J721E_CLK_PARENT_44100]) in j721e_configure_refclk()191 if (priv->pll_rates[clk_id] / scki <= J721E_MAX_CLK_HSDIV) { in j721e_configure_refclk()518 .pll_rates = {527 .pll_rates = {536 .pll_rates = {567 priv->pll_rates[J721E_CLK_PARENT_44100] = in j721e_calculate_rate_range()568 match_data->pll_rates[J721E_CLK_PARENT_44100]; in j721e_calculate_rate_range()[all …]
28 unsigned long pll_rates[] = { in mtk_pll_early_init() local45 for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { in mtk_pll_early_init()48 ret = clk_set_rate(&clk, pll_rates[i]); in mtk_pll_early_init()