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Searched refs:pll_hz (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_pic32.c321 ulong rate, pll_hz; in pic32_clk_init() local
326 pll_hz = pic32_get_pll_rate(priv); in pic32_clk_init()
334 pic32_set_refclk(priv, i, pll_hz, rate, ROCLK_SRC_SPLL); in pic32_clk_init()
370 ulong pll_hz; in pic32_set_rate() local
374 pll_hz = pic32_get_pll_rate(priv); in pic32_set_rate()
375 pic32_set_refclk(priv, clk->id, pll_hz, rate, ROCLK_SRC_SPLL); in pic32_set_rate()
/openbmc/u-boot/drivers/mmc/
H A Dsunxi_mmc.c111 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; in mmc_set_mod_clk() local
129 pll_hz = 24000000; in mmc_set_mod_clk()
133 pll_hz = clock_get_pll4_periph0(); in mmc_set_mod_clk()
136 pll_hz = clock_get_pll6() * 2; in mmc_set_mod_clk()
139 pll_hz = clock_get_pll6(); in mmc_set_mod_clk()
143 div = pll_hz / hz; in mmc_set_mod_clk()
144 if (pll_hz % hz) in mmc_set_mod_clk()
205 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div); in mmc_set_mod_clk()