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Searched refs:pll_ddr_num (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c160 num = ccm_anatop->pll_ddr_num; in decode_pll()
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h96 uint32_t pll_ddr_num; /* offset 0x0090 */ member