Searched refs:pll_ctl_val (Results 1 – 1 of 1) sorted by relevance
746 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init() local749 if (pll_ctl_val & 0x10) { in omap1_clk_init()751 if (pll_ctl_val & 0xf80) in omap1_clk_init()752 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; in omap1_clk_init()753 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; in omap1_clk_init()756 switch (pll_ctl_val & 0xc) { in omap1_clk_init()