| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | vlv_dsi_pll.c | 123 u32 pll_ctl, pll_div; in vlv_dsi_pclk() local
128 pll_ctl = config->dsi_pll.ctrl; in vlv_dsi_pclk()
132 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; in vlv_dsi_pclk()
133 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); in vlv_dsi_pclk()
143 while (pll_ctl) { in vlv_dsi_pclk()
144 pll_ctl = pll_ctl >> 1; in vlv_dsi_pclk()
324 u32 pll_ctl, pll_div; in vlv_dsi_get_pclk() local
329 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in vlv_dsi_get_pclk()
333 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; in vlv_dsi_get_pclk()
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| /openbmc/linux/drivers/ata/ |
| H A D | pata_pdc2027x.c | 503 u16 pll_ctl; in pdc_adjust_pll() local
521 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
523 dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl); in pdc_adjust_pll()
556 pll_ctl = (R << 8) | F; in pdc_adjust_pll()
558 dev_dbg(host->dev, "Writing pll_ctl[%X]\n", pll_ctl); in pdc_adjust_pll()
560 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
570 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
572 dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl); in pdc_adjust_pll()
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| /openbmc/linux/sound/soc/codecs/ |
| H A D | tscs42xx.c | 947 struct pll_ctl { struct
973 static const struct pll_ctl pll_ctls[] = {
1048 const struct pll_ctl *pll_ctl = NULL; in get_pll_ctl() local
1052 pll_ctl = &pll_ctls[i]; in get_pll_ctl()
1056 return pll_ctl; in get_pll_ctl()
1064 const struct pll_ctl *pll_ctl; in set_pll_ctl_from_input_freq() local
1066 pll_ctl = get_pll_ctl(input_freq); in set_pll_ctl_from_input_freq()
1067 if (!pll_ctl) { in set_pll_ctl_from_input_freq()
1076 pll_ctl->settings[i].addr, in set_pll_ctl_from_input_freq()
1077 pll_ctl->settings[i].mask, in set_pll_ctl_from_input_freq()
[all …]
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| H A D | tscs454.c | 509 struct pll_ctl { struct
532 static const struct pll_ctl pll_ctls[] = { argument
604 static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in) in get_pll_ctl()
607 struct pll_ctl const *pll_ctl = NULL; in get_pll_ctl() local
611 pll_ctl = &pll_ctls[i]; in get_pll_ctl()
615 return pll_ctl; in get_pll_ctl()
628 struct pll_ctl const *pll_ctl; in set_sysclk() local
637 pll_ctl = get_pll_ctl(freq); in set_sysclk()
638 if (!pll_ctl) { in set_sysclk()
647 pll_ctl->settings[i].addr, in set_sysclk()
[all …]
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| H A D | sgtl5000.c | 989 int pll_ctl; in sgtl5000_set_clock() local
1008 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | in sgtl5000_set_clock()
1011 snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl); in sgtl5000_set_clock()
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| /openbmc/u-boot/drivers/video/exynos/ |
| H A D | exynos_dp_lowlevel.c | 114 writel(reg, &dp_regs->pll_ctl); in exynos_dp_init_analog_param()
257 reg = readl(&dp_regs->pll_ctl); in exynos_dp_set_pll_power()
263 writel(reg, &dp_regs->pll_ctl); in exynos_dp_set_pll_power()
283 reg = readl(&dp_regs->pll_ctl); in exynos_dp_init_analog_func()
285 writel(reg, &dp_regs->pll_ctl); in exynos_dp_init_analog_func()
290 reg = readl(&dp_regs->pll_ctl); in exynos_dp_init_analog_func()
292 writel(reg, &dp_regs->pll_ctl); in exynos_dp_init_analog_func()
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| /openbmc/linux/arch/arm/mach-rpc/include/mach/ |
| H A D | acornfb.h | 133 vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div); in acornfb_vidc20_find_rates()
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | acornfb.h | 76 u_int pll_ctl; member
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| H A D | acornfb.c | 162 vidc_writel(0xd0000000 | vidc.pll_ctl); in acornfb_set_timing()
239 printk(KERN_DEBUG " PLL Ctrl (D) : 0x%08X\n", vidc.pll_ctl); in acornfb_set_timing()
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| /openbmc/linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-mio-defs.h | 1698 uint64_t pll_ctl:10; member
1728 uint64_t pll_ctl:10;
1821 uint64_t pll_ctl:10; member
1855 uint64_t pll_ctl:10;
1862 uint64_t pll_ctl:10; member
1898 uint64_t pll_ctl:10;
1905 uint64_t pll_ctl:10; member
1939 uint64_t pll_ctl:10;
1946 uint64_t pll_ctl:10; member
1992 uint64_t pll_ctl:10;
[all …]
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | dp.h | 131 unsigned int pll_ctl; member
|