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/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
100 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); in decode_sscg_pll()
115 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2); in decode_sscg_pll()
122 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2); in decode_sscg_pll()
129 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2); in decode_sscg_pll()
224 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >> in decode_sscg_pll()
226 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >> in decode_sscg_pll()
703 pll_cfg2 = &ana_pll->sys_pll1_cfg2; in sscg_pll_init()
718 pll_cfg2 = &ana_pll->sys_pll2_cfg2; in sscg_pll_init()
733 pll_cfg2 = &ana_pll->sys_pll3_cfg2; in sscg_pll_init()
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