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Searched refs:pll_cfg1 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c20 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
66 divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >> in decode_frac_pll()
68 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
99 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
114 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
121 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
128 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
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