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Searched refs:pll_cfg1 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c20 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
660 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
678 writel(val_cfg1, pll_cfg1); in frac_pll_init()
702 pll_cfg1 = &ana_pll->sys_pll1_cfg1; in sscg_pll_init()
717 pll_cfg1 = &ana_pll->sys_pll2_cfg1; in sscg_pll_init()
732 pll_cfg1 = &ana_pll->sys_pll3_cfg1; in sscg_pll_init()
749 writel(val_cfg1, pll_cfg1); in sscg_pll_init()
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