Searched refs:pllSSPLL_DIV_0 (Results 1 – 3 of 3) sorted by relevance
612 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0); in radeon_pm_save_regs()1597 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]); in radeon_pm_m10_enable_lvds_spread_spectrum()2178 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */); in radeon_reinitialize_M9P()
1937 #define pllSSPLL_DIV_0 0x0032 macro
1941 #define pllSSPLL_DIV_0 0x0032 macro