Searched refs:pll1divr (Results 1 – 1 of 1) sorted by relevance
132 u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */ member351 uint32_t pll1divr = 0; in configure_clocks() local397 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; in configure_clocks()398 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; in configure_clocks()399 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; in configure_clocks()400 pll1divr |= (sys_pll_psc.divn - 1); in configure_clocks()401 writel(pll1divr, ®s->pll1divr); in configure_clocks()530 divn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1; in stm32_get_PLL1_rate()532 divp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK; in stm32_get_PLL1_rate()535 divq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK; in stm32_get_PLL1_rate()[all …]