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Searched refs:pll1_c0_cfg (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun8i_a83t.c90 &ccm->pll1_c0_cfg); in clock_set_pll1()
H A Dclock_sun9i.c98 &ccm->pll1_c0_cfg); in clock_set_pll1()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h12 u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ member
H A Dclock_sun8i_a83t.h17 u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ member