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Searched refs:phy_ctrl0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_gen5.c396 writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0); in sdr_load_regs()
454 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0); in sdram_mmr_init_full()
H A Dsequencer.c3647 writel(reg, &sdr_ctrl->phy_ctrl0); in initialize_hps_phy()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h77 u32 phy_ctrl0; /* 0x150 */ member
120 u32 phy_ctrl0; member
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_sdram_config.c186 .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,