Home
last modified time | relevance | path

Searched refs:phy_base (Results 1 – 15 of 15) sorted by relevance

/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dddrphy-ld4.c31 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) in uniphier_ld4_ddrphy_init() argument
48 writel(0x0300c473, phy_base + PHY_PGCR1); in uniphier_ld4_ddrphy_init()
49 writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); in uniphier_ld4_ddrphy_init()
50 writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1); in uniphier_ld4_ddrphy_init()
51 writel(0x00083DEF, phy_base + PHY_PTR2); in uniphier_ld4_ddrphy_init()
52 writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3); in uniphier_ld4_ddrphy_init()
53 writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4); in uniphier_ld4_ddrphy_init()
54 writel(0xF004001A, phy_base + PHY_DSGCR); in uniphier_ld4_ddrphy_init()
57 tmp = readl(phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
60 writel(tmp, phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
[all …]
H A Dumc-pxs2.c59 static void ddrphy_fifo_reset(void __iomem *phy_base) in ddrphy_fifo_reset() argument
63 tmp = readl(phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
65 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
70 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
75 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) in ddrphy_vt_ctrl() argument
79 tmp = readl(phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
86 writel(tmp, phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
89 while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP)) in ddrphy_vt_ctrl()
94 static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step) in ddrphy_dqs_delay_fixup() argument
98 void __iomem *dx_base = phy_base + MPHY_DX_BASE; in ddrphy_dqs_delay_fixup()
[all …]
H A Dddrphy-training.c21 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
23 void __iomem *dx_base = phy_base + PHY_DX_BASE; in ddrphy_prepare_training()
37 tmp = readl(phy_base + PHY_DTCR); in ddrphy_prepare_training()
46 writel(tmp, phy_base + PHY_DTCR); in ddrphy_prepare_training()
107 int ddrphy_training(void __iomem *phy_base) in ddrphy_training() argument
123 writel(init_flag, phy_base + PHY_PIR); in ddrphy_training()
131 pgsr0 = readl(phy_base + PHY_PGSR0); in ddrphy_training()
H A Dcmd_ddrmphy.c73 void __iomem *phy_base, *dx_base; in dump_loop() local
77 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
78 dx_base = phy_base + MPHY_DX_BASE; in dump_loop()
87 iounmap(phy_base); in dump_loop()
93 void __iomem *phy_base, *zq_base; in zq_dump() local
101 phy_base = ioremap(param->phy[phy].base, SZ_4K); in zq_dump()
102 zq_base = phy_base + MPHY_ZQ_BASE; in zq_dump()
123 iounmap(phy_base); in zq_dump()
229 { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
236 void __iomem *reg = phy_base + ofst; \
[all …]
H A Dddrphy-init.h12 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
13 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
14 int ddrphy_training(void __iomem *phy_base);
H A Dcmd_ddrphy.c88 void __iomem *phy_base, *dx_base; in dump_loop() local
92 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
93 dx_base = phy_base + PHY_DX_BASE; in dump_loop()
102 iounmap(phy_base); in dump_loop()
203 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
211 void __iomem *reg = phy_base + ofst; \
218 void __iomem *phy_base; in reg_dump() local
224 phy_base = ioremap(param->phy[phy].base, SZ_4K); in reg_dump()
227 phy, ptr_to_uint(phy_base)); in reg_dump()
260 iounmap(phy_base); in reg_dump()
H A Dumc-pro4.c134 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
146 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
150 ddrphy_prepare_training(phy_base, phy); in umc_ch_init()
151 ret = ddrphy_training(phy_base); in umc_ch_init()
155 phy_base += 0x00001000; in umc_ch_init()
H A Dumc-ld4.c147 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
156 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
160 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
161 ret = ddrphy_training(phy_base); in umc_ch_init()
H A Dumc-sld8.c150 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
159 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
163 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
164 ret = ddrphy_training(phy_base); in umc_ch_init()
/openbmc/u-boot/drivers/usb/host/
H A Dxhci-exynos5.c37 fdt_addr_t phy_base; member
80 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in xhci_usb_ofdata_to_platdata()
81 if (plat->phy_base == FDT_ADDR_T_NONE) { in xhci_usb_ofdata_to_platdata()
212 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base; in xhci_usb_probe()
H A Dehci-exynos.c30 fdt_addr_t phy_base; member
71 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in ehci_usb_ofdata_to_platdata()
72 if (plat->phy_base == FDT_ADDR_T_NONE) { in ehci_usb_ofdata_to_platdata()
220 ctx->usb = (struct exynos_usb_phy *)plat->phy_base; in ehci_usb_probe()
/openbmc/u-boot/drivers/phy/
H A Domap-usb2-phy.c35 void *phy_base; member
139 val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1); in omap_usb2_phy_init()
141 writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1); in omap_usb2_phy_init()
186 priv->phy_base = (void *)base; in omap_usb2_phy_probe()
/openbmc/u-boot/drivers/net/mscc_eswitch/
H A Docelot_switch.c163 phys_addr_t phy_base[TARGET_MAX]; in ocelot_mdiobus_init() local
189 phy_base[i] = ofnode_translate_address(mdio_node, &faddr); in ocelot_mdiobus_init()
194 miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]); in ocelot_mdiobus_init()
195 miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]); in ocelot_mdiobus_init()
H A Dluton_switch.c216 phys_addr_t phy_base[NUM_PHY]; in luton_mdiobus_init() local
242 phy_base[i] = ofnode_translate_address(mdio_node, &faddr); in luton_mdiobus_init()
247 miim[mdiobus_id].regs = ioremap(phy_base[mdiobus_id], in luton_mdiobus_init()
/openbmc/u-boot/drivers/net/
H A Dmvpp2.c4722 fdt_addr_t phy_base; in phy_info_parse() local
4731 phy_base = ofnode_get_addr(phy_ofnode); in phy_info_parse()
4732 port->mdio_base = (void *)phy_base; in phy_info_parse()