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Searched refs:phb (Results 1 – 18 of 18) sorted by relevance

/openbmc/qemu/hw/pci-host/
H A Dpnv_phb4.c26 #define phb_error(phb, fmt, ...) \ argument
28 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)
34 static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) in pnv_phb4_find_cfg_dev() argument
36 PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); in pnv_phb4_find_cfg_dev()
37 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; in pnv_phb4_find_cfg_dev()
57 static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off, in pnv_phb4_config_write() argument
63 pdev = pnv_phb4_find_cfg_dev(phb); in pnv_phb4_config_write()
67 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; in pnv_phb4_config_write()
92 static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, in pnv_phb4_config_read() argument
99 pdev = pnv_phb4_find_cfg_dev(phb); in pnv_phb4_config_read()
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H A Dpnv_phb3.c26 #define phb3_error(phb, fmt, ...) \ argument
28 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)
30 static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb) in pnv_phb3_find_cfg_dev() argument
32 PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); in pnv_phb3_find_cfg_dev()
33 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; in pnv_phb3_find_cfg_dev()
49 static void pnv_phb3_config_write(PnvPHB3 *phb, unsigned off, in pnv_phb3_config_write() argument
55 pdev = pnv_phb3_find_cfg_dev(phb); in pnv_phb3_config_write()
59 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; in pnv_phb3_config_write()
84 static uint64_t pnv_phb3_config_read(PnvPHB3 *phb, unsigned off, in pnv_phb3_config_read() argument
91 pdev = pnv_phb3_find_cfg_dev(phb); in pnv_phb3_config_read()
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H A Dpnv_phb.c65 static Object *pnv_phb_user_get_parent(PnvChip *chip, PnvPHB *phb, Error **errp) in pnv_phb_user_get_parent() argument
67 if (phb->version == 3) { in pnv_phb_user_get_parent()
68 return OBJECT(pnv_chip_add_phb(chip, phb)); in pnv_phb_user_get_parent()
70 return OBJECT(pnv_pec_add_phb(chip, phb, errp)); in pnv_phb_user_get_parent()
80 static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp) in pnv_phb_user_device_init() argument
83 PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); in pnv_phb_user_device_init()
87 error_setg(errp, "invalid chip id: %d", phb->chip_id); in pnv_phb_user_device_init()
91 parent = pnv_phb_user_get_parent(chip, phb, errp); in pnv_phb_user_device_init()
102 OBJECT(phb), phb->phb_id, errp)) { in pnv_phb_user_device_init()
111 PnvPHB *phb = PNV_PHB(dev); in pnv_phb_realize() local
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H A Dpnv_phb3_pbcq.c25 (pbcq)->phb->chip_id, (pbcq)->phb->phb_id, ## __VA_ARGS__)
52 return pnv_phb3_reg_read(pbcq->phb, in pnv_pbcq_spci_xscom_read()
86 pnv_phb3_update_regions(pbcq->phb); in pnv_pbcq_update_map()
118 pnv_phb3_update_regions(pbcq->phb); in pnv_pbcq_update_map()
148 pnv_phb3_remap_irqs(pbcq->phb); in pnv_pbcq_nest_xscom_write()
153 pnv_phb3_remap_irqs(pbcq->phb); in pnv_pbcq_nest_xscom_write()
157 pnv_phb3_remap_irqs(pbcq->phb); in pnv_pbcq_nest_xscom_write()
196 pnv_phb3_reg_write(pbcq->phb, pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR], in pnv_pbcq_spci_xscom_write()
241 PnvPHB3 *phb = pbcq->phb; in pnv_pbcq_default_bars() local
243 mm0 = 0x3d00000000000ull + 0x4000000000ull * phb->chip_id + in pnv_pbcq_default_bars()
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H A Dgrackle.c53 PCIHostState *phb = PCI_HOST_BRIDGE(dev); in grackle_realize() local
55 phb->bus = pci_register_root_bus(dev, NULL, in grackle_realize()
63 pci_create_simple(phb->bus, 0, "grackle"); in grackle_realize()
70 PCIHostState *phb = PCI_HOST_BRIDGE(obj); in grackle_init() local
79 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, in grackle_init()
81 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, in grackle_init()
84 sysbus_init_mmio(sbd, &phb->conf_mem); in grackle_init()
85 sysbus_init_mmio(sbd, &phb->data_mem); in grackle_init()
H A Dpnv_phb3_msi.c20 static uint64_t phb3_msi_ive_addr(PnvPHB3 *phb, int srcno) in phb3_msi_ive_addr() argument
22 uint64_t ivtbar = phb->regs[PHB_IVT_BAR >> 3]; in phb3_msi_ive_addr()
23 uint64_t phbctl = phb->regs[PHB_CONTROL >> 3]; in phb3_msi_ive_addr()
45 static bool phb3_msi_read_ive(PnvPHB3 *phb, int srcno, uint64_t *out_ive) in phb3_msi_read_ive() argument
49 ive_addr = phb3_msi_ive_addr(phb, srcno); in phb3_msi_read_ive()
70 ive_addr = phb3_msi_ive_addr(msi->phb, srcno); in phb3_msi_set_p()
87 ive_addr = phb3_msi_ive_addr(msi->phb, srcno); in phb3_msi_set_q()
105 if (!phb3_msi_read_ive(msi->phb, srcno, &ive)) { in phb3_msi_try_send()
170 if (!phb3_msi_read_ive(msi->phb, src, &ive)) { in pnv_phb3_msi_send()
190 msi->phb->regs[PHB_FFI_LOCK >> 3] = 0; in pnv_phb3_msi_ffi()
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H A Dsh_pci.c54 PCIHostState *phb = PCI_HOST_BRIDGE(pcic); in sh_pci_reg_write() local
71 pci_data_write(phb->bus, pcic->par, val, 4); in sh_pci_reg_write()
79 PCIHostState *phb = PCI_HOST_BRIDGE(pcic); in sh_pci_reg_read() local
91 return pci_data_read(phb->bus, pcic->par, 4); in sh_pci_reg_read()
122 PCIHostState *phb = PCI_HOST_BRIDGE(s); in sh_pcic_host_realize() local
128 phb->bus = pci_register_root_bus(dev, "pci", in sh_pcic_host_realize()
145 s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host"); in sh_pcic_host_realize()
H A Dpnv_phb4_pec.c138 PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp) in pnv_pec_add_phb() argument
141 int chip_id = phb->chip_id; in pnv_pec_add_phb()
142 int index = phb->phb_id; in pnv_pec_add_phb()
145 if (phb->version == 4) { in pnv_pec_add_phb()
149 } else if (phb->version == 5) { in pnv_pec_add_phb()
166 pec->phbs[j] = phb; in pnv_pec_add_phb()
167 phb->pec = pec; in pnv_pec_add_phb()
183 PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB)); in pnv_pec_default_phb_realize() local
186 object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); in pnv_pec_default_phb_realize()
187 object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), in pnv_pec_default_phb_realize()
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H A Ddino.c98 PCIHostState *phb = PCI_HOST_BRIDGE(s); in dino_chip_read_with_attrs() local
108 ioaddr = phb->config_reg + (addr & 3); in dino_chip_read_with_attrs()
191 PCIHostState *phb = PCI_HOST_BRIDGE(s); in dino_chip_write_with_attrs() local
203 ioaddr = phb->config_reg + (addr & 3); in dino_chip_write_with_attrs()
416 PCIHostState *phb = PCI_HOST_BRIDGE(dev); in dino_pcihost_realize() local
423 memory_region_init_io(&phb->conf_mem, OBJECT(phb), in dino_pcihost_realize()
426 memory_region_init_io(&phb->data_mem, OBJECT(phb), in dino_pcihost_realize()
430 &phb->conf_mem); in dino_pcihost_realize()
432 &phb->data_mem); in dino_pcihost_realize()
437 phb->bus = pci_register_root_bus(DEVICE(s), "pci", in dino_pcihost_realize()
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H A Di440fx.c225 PCIHostState *phb = PCI_HOST_BRIDGE(obj); in i440fx_pcihost_initfn() local
227 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, in i440fx_pcihost_initfn()
229 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, in i440fx_pcihost_initfn()
253 PCIHostState *phb = PCI_HOST_BRIDGE(dev); in i440fx_pcihost_realize() local
260 memory_region_add_subregion(s->io_memory, 0xcf8, &phb->conf_mem); in i440fx_pcihost_realize()
263 memory_region_add_subregion(s->io_memory, 0xcfc, &phb->data_mem); in i440fx_pcihost_realize()
267 memory_region_set_flush_coalesced(&phb->data_mem); in i440fx_pcihost_realize()
268 memory_region_add_coalescing(&phb->conf_mem, 0, 4); in i440fx_pcihost_realize()
272 phb->bus = b; in i440fx_pcihost_realize()
H A Dsabre.c253 PCIHostState *phb = PCI_HOST_BRIDGE(s); in sabre_pci_config_write() local
256 pci_data_write(phb->bus, addr, val, size); in sabre_pci_config_write()
264 PCIHostState *phb = PCI_HOST_BRIDGE(s); in sabre_pci_config_read() local
266 ret = pci_data_read(phb->bus, addr, size); in sabre_pci_config_read()
373 PCIHostState *phb = PCI_HOST_BRIDGE(dev); in sabre_realize() local
380 phb->bus = pci_register_root_bus(dev, "pci", in sabre_realize()
386 pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); in sabre_realize()
391 pci_setup_iommu(phb->bus, &sabre_iommu_ops, s->iommu); in sabre_realize()
397 pci_realize_and_unref(pci_dev, phb->bus, &error_fatal); in sabre_realize()
402 pci_realize_and_unref(pci_dev, phb->bus, &error_fatal); in sabre_realize()
H A Dgt64120.c997 PCIHostState *phb = PCI_HOST_BRIDGE(s); in bswap() local
999 bool is_phb_dev0 = extract32(phb->config_reg, 11, 13) == 0; in bswap()
1196 PCIHostState *phb = PCI_HOST_BRIDGE(dev); in gt64120_realize() local
1202 phb->bus = pci_root_bus_new(dev, "pci", in gt64120_realize()
1207 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); in gt64120_realize()
1208 memory_region_init_io(&phb->conf_mem, OBJECT(phb), in gt64120_realize()
1212 &phb->conf_mem, 1); in gt64120_realize()
1214 memory_region_init_io(&phb->data_mem, OBJECT(phb), in gt64120_realize()
1218 &phb->data_mem, 1); in gt64120_realize()
H A Duninorth.c83 PCIHostState *phb = PCI_HOST_BRIDGE(s); in unin_data_write() local
85 pci_data_write(phb->bus, in unin_data_write()
86 unin_get_config_reg(phb->config_reg, addr), in unin_data_write()
94 PCIHostState *phb = PCI_HOST_BRIDGE(s); in unin_data_read() local
97 val = pci_data_read(phb->bus, in unin_data_read()
98 unin_get_config_reg(phb->config_reg, addr), in unin_data_read()
H A Dastro.c430 PCIHostState *phb = PCI_HOST_BRIDGE(dev); in elroy_pcihost_realize() local
439 memory_region_init_io(&phb->conf_mem, obj, in elroy_pcihost_realize()
442 memory_region_init_io(&phb->data_mem, obj, in elroy_pcihost_realize()
446 &phb->conf_mem); in elroy_pcihost_realize()
448 &phb->data_mem); in elroy_pcihost_realize()
456 phb->bus = pci_register_root_bus(DEVICE(s), "pci", in elroy_pcihost_realize()
/openbmc/openpower-hw-diags/test/
H A Dpdbg-test.dts1932 compatible = "ibm,power10-phb";
1937 ATTR_PHYS_DEV_PATH = "physical:sys-0/node-0/proc-0/pec-0/phb-0";
1942 compatible = "ibm,power10-phb";
1947 ATTR_PHYS_DEV_PATH = "physical:sys-0/node-0/proc-0/pec-0/phb-1";
1952 compatible = "ibm,power10-phb";
1957 ATTR_PHYS_DEV_PATH = "physical:sys-0/node-0/proc-0/pec-0/phb-2";
1982 compatible = "ibm,power10-phb";
1987 ATTR_PHYS_DEV_PATH = "physical:sys-0/node-0/proc-0/pec-1/phb-0";
1992 compatible = "ibm,power10-phb";
1997 ATTR_PHYS_DEV_PATH = "physical:sys-0/node-0/proc-0/pec-1/phb-1";
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/openbmc/qemu/include/hw/pci-host/
H A Dspapr.h105 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
/openbmc/qemu/hw/alpha/
H A Dtyphoon.c829 PCIHostState *phb; in typhoon_init() local
836 phb = PCI_HOST_BRIDGE(dev); in typhoon_init()
896 phb->bus = b; in typhoon_init()
/openbmc/qemu/tests/qtest/
H A Dmeson.build309 'spapr-phb-test.c',