Home
last modified time | relevance | path

Searched refs:per_pll_cntr5clk (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_s10.h53 u32 per_pll_cntr5clk; member
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c150 writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk); in cm_basic_init()