Searched refs:pbcq (Results 1 – 3 of 3) sorted by relevance
23 #define phb3_pbcq_error(pbcq, fmt, ...) \ argument25 (pbcq)->phb->chip_id, (pbcq)->phb->phb_id, ## __VA_ARGS__)30 PnvPBCQState *pbcq = PNV_PBCQ(opaque); in pnv_pbcq_nest_xscom_read() local33 return pbcq->nest_regs[offset]; in pnv_pbcq_nest_xscom_read()39 PnvPBCQState *pbcq = PNV_PBCQ(opaque); in pnv_pbcq_pci_xscom_read() local42 return pbcq->pci_regs[offset]; in pnv_pbcq_pci_xscom_read()48 PnvPBCQState *pbcq = PNV_PBCQ(opaque); in pnv_pbcq_spci_xscom_read() local52 return pnv_phb3_reg_read(pbcq->phb, in pnv_pbcq_spci_xscom_read()53 pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR], 8); in pnv_pbcq_spci_xscom_read()55 return pbcq->spci_regs[offset]; in pnv_pbcq_spci_xscom_read()[all …]
121 PnvPBCQState *pbcq = &phb->pbcq; in pnv_phb3_check_m32() local137 if (memory_region_is_mapped(&pbcq->mmbar0) && in pnv_phb3_check_m32()138 base >= pbcq->mmio0_base && in pnv_phb3_check_m32()139 (base + size) <= (pbcq->mmio0_base + pbcq->mmio0_size)) { in pnv_phb3_check_m32()140 parent = &pbcq->mmbar0; in pnv_phb3_check_m32()141 base -= pbcq->mmio0_base; in pnv_phb3_check_m32()142 } else if (memory_region_is_mapped(&pbcq->mmbar1) && in pnv_phb3_check_m32()143 base >= pbcq->mmio1_base && in pnv_phb3_check_m32()144 (base + size) <= (pbcq->mmio1_base + pbcq->mmio1_size)) { in pnv_phb3_check_m32()145 parent = &pbcq->mmbar1; in pnv_phb3_check_m32()[all …]
157 PnvPBCQState pbcq; member