/openbmc/linux/arch/powerpc/platforms/cell/ |
H A D | spu_priv1_mmio.c | 31 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); in int_mask_and() 39 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); in int_mask_or() 44 out_be64(&spu->priv1->int_mask_RW[class], mask); in int_mask_set() 54 out_be64(&spu->priv1->int_stat_RW[class], stat); in int_stat_clear() 77 out_be64(&spu->priv1->int_route_RW, route); in cpu_affinity_set() 92 out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); in mfc_dsisr_set() 97 out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1)); in mfc_sdr_setup() 102 out_be64(&spu->priv1->mfc_sr1_RW, sr1); in mfc_sr1_set() 112 out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id); in mfc_tclass_id_set() 122 out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); in tlb_invalidate() [all …]
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H A D | interrupt.c | 74 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); in iic_eoi() 107 out_be64(&node_iic->iic_is, ack); in iic_ioexc_cascade() 116 out_be64(&node_iic->iic_is, ack); in iic_ioexc_cascade() 151 out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff); in iic_setup_cpu() 171 out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4); in iic_message_pass() 288 out_be64(&iic->regs->prio, 0); in init_one_iic() 341 out_be64(&node_iic->iic_ir, in setup_iic() 348 out_be64(&node_iic->iic_is, 0xfffffffffffffffful); in setup_iic() 389 out_be64(&iic_regs->iic_ir, iic_ir); in iic_set_interrupt_routing()
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H A D | cbe_thermal.c | 133 out_be64(&pmd_regs->tm_tpr.val, reg_value); in store_throttle() 353 out_be64(&pmd_regs->tm_str2, str2); in init_default_values() 354 out_be64(&pmd_regs->tm_str1.val, str1.val); in init_default_values() 355 out_be64(&pmd_regs->tm_tpr.val, tpr.val); in init_default_values() 356 out_be64(&pmd_regs->tm_cr1.val, cr1.val); in init_default_values() 357 out_be64(&pmd_regs->tm_cr2, cr2); in init_default_values()
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H A D | spu_base.c | 72 out_be64(&priv2->slb_invalidate_all_W, 0UL); in spu_invalidate_slbs() 127 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); in spu_restart_dma() 141 out_be64(&priv2->slb_index_W, slbe); in spu_load_slb() 143 out_be64(&priv2->slb_esid_RW, 0); in spu_load_slb() 145 out_be64(&priv2->slb_vsid_RW, slb->vsid); in spu_load_slb() 147 out_be64(&priv2->slb_esid_RW, slb->esid); in spu_load_slb() 455 out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel); in spu_init_channels() 457 out_be64(&priv2->spu_chnldata_RW, 0); in spu_init_channels() 462 out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel); in spu_init_channels() 463 out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count); in spu_init_channels()
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H A D | iommu.c | 147 out_be64(reg, val); in invalidate_tce_cache() 253 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); in ioc_interrupt() 396 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, in cell_iommu_enable_hardware() 398 out_be64(iommu->xlate_regs + IOC_IO_ExcpMask, in cell_iommu_enable_hardware() 410 out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); in cell_iommu_enable_hardware() 415 out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); in cell_iommu_enable_hardware() 701 out_be64(xregs + IOC_IOST_Origin, 0); in cell_disable_iommus() 705 out_be64(cregs + IOC_IOCmd_Cfg, val); in cell_disable_iommus()
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H A D | pervasive.c | 119 out_be64(®s->pmcr, in_be64(®s->pmcr) | in cbe_pervasive_init()
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H A D | ras.c | 289 out_be64(®s->ras_esc_0, 0); in cbe_sysreset_hack()
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H A D | pmu.c | 39 out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \
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/openbmc/linux/drivers/cpufreq/ |
H A D | ppc_cbe_cpufreq_pervasive.c | 59 out_be64(&mic_tm_regs->slow_fast_timer_0, MIC_Slow_Fast_Timer_table[pmode]); in cbe_cpufreq_set_pmode() 60 out_be64(&mic_tm_regs->slow_fast_timer_1, MIC_Slow_Fast_Timer_table[pmode]); in cbe_cpufreq_set_pmode() 62 out_be64(&mic_tm_regs->slow_next_timer_0, MIC_Slow_Next_Timer_table[pmode]); in cbe_cpufreq_set_pmode() 63 out_be64(&mic_tm_regs->slow_next_timer_1, MIC_Slow_Next_Timer_table[pmode]); in cbe_cpufreq_set_pmode() 71 out_be64(&pmd_regs->pmcr, value); in cbe_cpufreq_set_pmode()
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/openbmc/linux/arch/powerpc/platforms/cell/spufs/ |
H A D | switch.c | 271 out_be64(&priv2->mfc_control_RW, in halt_mfc_decr() 303 out_be64(&prob->spc_mssync_RW, 1UL); in do_mfc_mssync() 464 out_be64(&priv2->mfc_control_RW, in purge_mfc_queue() 529 out_be64(&priv2->spu_privcntl_RW, 0UL); in reset_spu_privcntl() 625 out_be64(&priv2->spu_chnlcntptr_RW, 1); in save_ch_part1() 636 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in save_ch_part1() 655 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in save_spu_mb() 783 out_be64(&prob->mfc_ea_W, ea); in send_mfc_dma() 1076 out_be64(&priv2->spu_chnlcntptr_RW, 1); in reset_ch_part1() 1077 out_be64(&priv2->spu_chnldata_RW, 0UL); in reset_ch_part1() [all …]
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H A D | hw_ops.c | 146 out_be64(&priv2->spu_cfg_RW, tmp); in spu_hw_signal1_type_set() 167 out_be64(&priv2->spu_cfg_RW, tmp); in spu_hw_signal2_type_set() 198 out_be64(&ctx->spu->priv2->spu_privcntl_RW, val); in spu_hw_privcntl_write() 282 out_be64(&prob->mfc_ea_W, cmd->ea); in spu_hw_send_mfc_command() 305 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); in spu_hw_restart_dma()
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H A D | run.c | 109 out_be64(mfc_cntl, MFC_CNTL_PURGE_DMA_REQUEST); in spu_setup_isolated() 122 out_be64(mfc_cntl, 0); in spu_setup_isolated()
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/openbmc/u-boot/drivers/core/ |
H A D | regmap.c | 340 #if defined(out_le64) && defined(out_be64) && defined(writeq) 352 out_be64(addr, *val); in __write_64() 388 #if defined(out_le64) && defined(out_be64) && defined(writeq) in regmap_raw_write_range()
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/openbmc/linux/arch/powerpc/platforms/powernv/ |
H A D | vas.h | 458 out_be64(regptr, val); in write_uwc_reg() 469 out_be64(regptr, val); in write_hvwc_reg()
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H A D | ocxl.c | 549 out_be64(arva + PNV_OCXL_ATSD_AVA, val); in pnv_ocxl_tlb_invalidate() 579 out_be64(arva + PNV_OCXL_ATSD_LNCH, val); in pnv_ocxl_tlb_invalidate()
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H A D | eeh-powernv.c | 111 out_be64(phb->regs + offset, val); in pnv_eeh_dbgfs_set()
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/openbmc/linux/drivers/misc/cxl/ |
H A D | debugfs.c | 23 out_be64((u64 __iomem *)data, val); in debugfs_io_u64_set()
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H A D | cxl.h | 785 out_be64(_cxl_p1_addr(cxl, reg), val); in cxl_p1_write() 805 out_be64(_cxl_p1n_addr(afu, reg), val); in cxl_p1n_write() 824 out_be64(_cxl_p2n_addr(afu, reg), val); in cxl_p2n_write()
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/openbmc/linux/arch/powerpc/include/asm/ |
H A D | io.h | 195 DEF_MMIO_OUT_D(out_be64, 64, std); 206 out_be64(addr, swab64(val)); in out_le64() 218 static inline void out_be64(volatile u64 __iomem *addr, u64 val) in out_be64() function 560 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
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/openbmc/linux/drivers/dma/ |
H A D | fsldma.h | 204 #define fsl_iowrite64be(v, p) out_be64(p, v)
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/openbmc/linux/drivers/edac/ |
H A D | cell_edac.c | 117 out_be64(&priv->regs->mic_fir, fir); in cell_edac_check()
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/openbmc/linux/arch/powerpc/platforms/85xx/ |
H A D | smp.c | 252 out_be64((u64 *)(&spin_table->addr_h), in smp_85xx_start_cpu()
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/openbmc/linux/arch/powerpc/sysdev/xive/ |
H A D | common.c | 237 out_be64(xd->eoi_mmio + offset, data); in xive_esb_write() 434 out_be64(xd->trig_mmio, 0); in xive_do_source_eoi() 1069 out_be64(xd->trig_mmio, 0); in xive_cause_ipi()
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/openbmc/u-boot/arch/mips/include/asm/ |
H A D | io.h | 561 #define out_be64(a, v) out_arch(q, be64, a, v) macro
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/openbmc/linux/drivers/misc/ocxl/ |
H A D | link.c | 133 out_be64(spa->reg_tfc, reg); in ack_irq()
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