Searched refs:optimal_dcfclk_for_uclk (Results 1 – 5 of 5) sorted by relevance
203 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box() local263 &optimal_dcfclk_for_uclk[i], NULL); in dcn302_fpu_update_bw_bounding_box()264 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()265 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()271 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn302_fpu_update_bw_bounding_box()283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn302_fpu_update_bw_bounding_box()287 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_fpu_update_bw_bounding_box()288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()302 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_fpu_update_bw_bounding_box()303 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
199 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box() local257 &optimal_dcfclk_for_uclk[i], NULL); in dcn303_fpu_update_bw_bounding_box()258 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box()259 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()265 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn303_fpu_update_bw_bounding_box()277 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn303_fpu_update_bw_bounding_box()281 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_fpu_update_bw_bounding_box()282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()297 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_fpu_update_bw_bounding_box()298 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
701 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu() local747 &optimal_dcfclk_for_uclk[i], NULL); in dcn321_update_bw_bounding_box_fpu()748 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()749 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu()756 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn321_update_bw_bounding_box_fpu()768 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn321_update_bw_bounding_box_fpu()772 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()773 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()787 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()788 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
2097 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local2153 &optimal_dcfclk_for_uclk[i], NULL); in dcn30_update_bw_bounding_box()2155 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()2156 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()2163 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn30_update_bw_bounding_box()2175 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn30_update_bw_bounding_box()2179 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2180 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()2194 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2195 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2790 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu() local2843 &optimal_dcfclk_for_uclk[i], NULL); in dcn32_update_bw_bounding_box_fpu()2844 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()2845 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu()2852 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn32_update_bw_bounding_box_fpu()2864 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn32_update_bw_bounding_box_fpu()2868 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()2869 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn32_update_bw_bounding_box_fpu()2883 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()2884 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn32_update_bw_bounding_box_fpu()