| /openbmc/qemu/target/arm/tcg/ |
| H A D | cpu64.c | 481 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
486 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
489 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
492 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
495 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
498 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
502 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
506 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
514 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
[all …]
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| /openbmc/qemu/target/arm/ |
| H A D | cortex-regs.c | 31 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
39 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
45 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
48 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
54 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
60 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
66 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
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| H A D | helper.c | 651 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
888 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
2109 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
2122 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
2136 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
2149 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
2161 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
2172 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
2186 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
2199 .opc0
[all...] |
| H A D | debug_helper.c | 952 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
960 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
971 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
981 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
985 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
990 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0,
999 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
1014 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
1020 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
1027 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
[all …]
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| H A D | cpregs.h | 862 uint8_t opc0; member
1076 static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1, in arm_cpreg_encoding_in_idspace() argument
1080 return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) && in arm_cpreg_encoding_in_idspace()
1091 arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, in arm_cpreg_in_idspace()
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_cpuif.c | 2443 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0,
2455 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 0,
2461 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1,
2467 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 2,
2473 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3,
2480 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 4,
2488 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0,
2495 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1,
2501 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 3,
2507 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5,
[all …]
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| H A D | arm_gicv3_kvm.c | 734 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
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| /openbmc/linux/arch/s390/kernel/ |
| H A D | uprobes.c | 226 u8 opc0; member
275 ilen = insn_length(insn->opc0); in handle_insn_ril()
277 switch (insn->opc0) { in handle_insn_ril()
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